An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of index address registers (612) and a full adder...http://www.google.com.tw/patents/US5712999?utm_source=gb-gplus-share專利 US5712999 - Address generator employing selective merge of two independent addresses
