A method and structure for wafer level testing of integrated circuit dice. A plurality of conductive paths are formed from a sacrificial metal layer and routed through the scribing lanes of the wafer. These conductive paths extend from selected I/O pads of the integrated circuit dice to an other portion...http://www.google.com.tw/patents/US5532174?utm_source=gb-gplus-share專利 US5532174 - Wafer level integrated circuit testing with a sacrificial metal layer
