In integrated circuit testing, a system is provided for reducing testing time by decreasing the number of test vectors or patterns while maintaining high fault coverage through utilizing lists of undetected faults in an integrated circuit to determine the optimal weighting for a weighted random pattern...http://www.google.com.tw/patents/US5414716?utm_source=gb-gplus-share專利 US5414716 - Weighting system for testing of circuits utilizing determination of undetected faults
