A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be...http://www.google.com.tw/patents/US6625765?utm_source=gb-gplus-share專利 US6625765 - Memory based phase locked loop
