Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal....http://www.google.com.tw/patents/US7068080?utm_source=gb-gplus-share專利 US7068080 - Method and apparatus for reducing power consumption within a logic device
