The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock...http://www.google.com.tw/patents/US7716036?utm_source=gb-gplus-share專利 US7716036 - Method and apparatus to use clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator
