Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and...http://www.google.com.tw/patents/US20100226176?utm_source=gb-gplus-share專利 US20100226176 - Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations
