A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When...http://www.google.com.tw/patents/US7080238?utm_source=gb-gplus-share專利 US7080238 - Non-blocking, multi-context pipelined processor
