A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region...http://www.google.com.tw/patents/US7074672?utm_source=gb-gplus-share專利 US7074672 - Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
