A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages....http://www.google.com.tw/patents/US20030061465?utm_source=gb-gplus-share專利 US20030061465 - Issue and retirement mechanism in processor having different pipeline lenghths
