A first load vector instruction signal V1 is read from an instruction buffer into an instruction read register. V1 is decoded and routed simultaneously to scalar and vector processor instruction issue registers. V1 is next routed to a vector instruction stage register and from there to a vector load...http://www.google.com.tw/patents/US4722049?utm_source=gb-gplus-share專利 US4722049 - Apparatus for out-of-order program execution
