The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates a plurality of transfer signals with a plurality of sampling signals based on a CAS latency...http://www.google.com.tw/patents/US6707759?utm_source=gb-gplus-share專利 US6707759 - Latency control circuit and method of latency control
