A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided...http://www.google.com.tw/patents/US6049238?utm_source=gb-gplus-share專利 US6049238 - Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements
