A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten...http://www.google.com.tw/patents/US5293621?utm_source=gb-gplus-share專利 US5293621 - Varying wait interval retry apparatus and method for preventing bus lockout
