A semiconductor memory circuit contains an array of memory cells, each of which contains a data latch formed of cross-coupled two inverters. First and second gate elements connected in series are placed between an output end of the latch and a reference point. Third and fourth gate elements connected...http://www.google.com.tw/patents/US5493536?utm_source=gb-gplus-share專利 US5493536 - Dual-port random access memory having memory cell controlled by write data lines and read enable line
