A parallel processor utilizing a memory cell array for rapidly performing parallel processing by switching between SIMD and MIMD operations depending on the type of problems to be solved. Where SIMD and MIMD operations are mixed in an application, the time loss in the switching therebetween is eliminated...http://www.google.com.tw/patents/US5535410?utm_source=gb-gplus-share專利 US5535410 - Parallel processor having decoder for selecting switch from the group of switches and concurrently inputting MIMD instructions while performing SIMD operation
