A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal....http://www.google.com.tw/patents/US7398447?utm_source=gb-gplus-share專利 US7398447 - Intercommunicating apparatus for duplex system capable of detecting failure thereof
