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FOREIGN PATENT DOCUMENTS
0 666 529 Al 1/1995 European Pat. Off. . WO 90/04296 4/1990 WIPO .
Communications Chip Interlaces With Most Microproces-
sors by Sam Travis, National Semiconductor Corp., Santa
Clara, California Electronics, Mar. 16, 1978.
INWAS: Interlacing With Asynchronous Serial Node by
David G. Larsen, Peter R. Rony and Jonathan A. Titus, IEEE
Transactions On Industrial Electronics and Control Instru-
mentation, vol., IECI-24, No. 1, Feb. 1977.
Primary Examiner—Ayaz R. Sheikh
Assistant Examiner—Eric S. Thlang
Attorney, Agent, or Firm—-Jenkins & Gilchrist, PC.
A UART including a logic unit is disclosed, wherein the logic unit automatically enables or disables the UART receiver port whenever data is being processed by the UART for wireless transmission. More specifically, a logic unit is connected to a data store, to a transmit FIFO and to a UART processing unit as well as to an external CPU, wherein the logic unit analyzes the logic states of each of the signals from each of the specified connections to determine whether to enable or disable the receiver unit. An inventive method is also disclosed wherein the logic unit only enables the receiver when the data store is empty and the transmitter FIFO is empty and a receiver enable flag is set to true and a half duplex mode of operation has been specified by an external CPU. Otherwise, the logic enables the receiver only when a full duplex mode of operation has been specified and the receiver enable flag is set to a logic one.
10 Claims, 4 Drawing Sheets