FAST ADAPTIVE WIDEBAND POWER
AMPLIFIER FEED FORWARD LINEARIZER
USING A RLS PARAMETER TRACKING
 Inventors: Jiunn-Tsair Chen, New Brunswick;
Young-Kai Chen, Berkeley Heights;
Huan-Shang Tsai, Parsippany, all of
 Assignee: Lucent Technologies Inc., Murray Hill, N.J.
 Appl. No.: 09/053,407  Filed: Apr. 1, 1998
 Int. C I. H03F 1 00
 U.S. CI 330/151; 330/149
 Field of Search 330/151, 149;
 References Cited
U.S. PATENT DOCUMENTS
5,049,832 9/1991 Cavers 330/149
5,489,875 2/1996 Cavers 330/151
5,508,657 4/1996 Behan 330/151
5,617,061 4/1997 Fukuchi 330/151
5,789,976 8/1998 Ghannouchi et al 330/52
5,808,512 9/1998 Bainvoll et al 330/151
FOREIGN PATENT DOCUMENTS
675594A1 4/1995 European Pat. Off. .
729228A1 8/1996 European Pat. Off. .
Cavers, J.K. "Adaption behavior of a feedforward amplifier linearizer," IEEE Trans, on Veh. Tech., Feb. 1995, vol. 44, No. 1, pp. 31^10.
Grant, S.J., et al., "A DSP controlled adaptive feedforward amplifier linearizer," 5th International Conference on Universal Personal Communications, Cambridge. MA, vol. 2, pp. 788-792.
European Search Report for Application No. 99301791 dated Jun. 30, 1999.
Primary Examiner—Robert Pascal
Assistant Examiner—Henry Choe
A feedforward linearizer for amplifying an input signal comprises a signal cancellation circuit which has a first branch and a second branch. A first amplifier provided in the first branch receives the input signal intended to be amplified and generates an output signal received by a signal cancellation vector modulator. A signal cancellation adder receives the signal generated by the signal cancellation vector modulator and the input signal via the second branch and provides an error signal. The feedforward linearizer also comprises an error cancellation circuit that has a first branch and a second branch. An error cancellation adder in the first branch receives the output signal provided by the first amplifier and generates the output signal of the linearizer. An error cancellation vector modulator in the second branch receives an error signal provided by the signal cancellation adder and provides an error adjusted signal to a second auxiliary amplifier. The second auxiliary amplifier provides an input signal to the error cancellation adder. A digital signal processor provides a signal cancellation adjustment signal, a, to the signal cancellation vector modulator and an error cancellation adjustment signal, (3, to the error cancellation vector modulator respectively, such that the output signal of the signal cancellation adder is a signal that substantially represents the error components provided by the first amplifier, and the output signal of the error cancellation adder is an amplified version of the input signal, with substantially no internmodulation components.
17 Claims, 3 Drawing Sheets