US006150710A [ii] Patent Number: 6,150,710 [45] Date of Patent: Nov. 21,2000
[54] TRANSVERSE HYBRID LOC PACKAGE
[75] Inventor: David J. Corisis, Meridian, Id.
[73] Assignee: Micron Technology, Inc., Boise, Id.
[21] Appl. No.: 09/302,196
[22] Filed: Apr. 29, 1999
Related U.S. Application Data
[62] Division of application No. 09/137,782, Aug. 20, 1998.
[51] Int. CI.7 H01L 23/495
[52] U.S. CI 257/666; 257/676
[58] Field of Search 257/666, 676
[56] References Cited
U.S. PATENT DOCUMENTS
A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of inner leads is off-die wire bonded to some of the bond pads, and a second portion of inner leads is insulatively attached as LOC leads between the bond pads along the opposed die edges. The hybrid package results in shorter inner leads of increased pitch enabling improved line yield at wire bond and encapsulation, as well as improved electrical performance, particularly for packages with very small dice.
14 Claims, 5 Drawing Sheets
