US006405323B1
(io) Patent No.: US 6,405,323 Bl (45) Date of Patent: Jun. 11,2002
(54) DEFECT MANAGEMENT FOR INTERFACE TO ELECTRICALLY-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
(75) Inventors: Frank Fong-Long Lin, Milpitas;
Dongsheng Xing, Fremont, both of CA
(US)
Silicon Storage Technology, Inc.,
Sunnyvale, CA (US)
Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/281,357
(22) Filed: Mar. 30, 1999
(51) Int. C I. G06F 11/00
(52) U.S. CI 714/8; 711/152
(58) Field of Search 714/8, 7-4, 2,
714/13, 25, 30, 31, 39, 42, 44; 711/103,
104, 152
(56) References Cited
U.S. PATENT DOCUMENTS
5,438,573 A * 8/1995 Mangan et al 714/711
5,471,478 A * 11/1995 Mangan et al 714/711
5,509,018 A * 4/1996 Niijima et al 714/710
5,541,903 A * 7/1996 Funahashi et al 369/54
5,546,402 A * 8/1996 Niijima et al 714/710
A circuit interfaces a host processor to an electricallyerasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read. Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid. Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.
24 Claims, 3 Drawing Sheets
