Nonvolatile power management apparatus for integrated circuit application

(54) NONVOLATILE POWER MANAGEMENT APPARATUS FOR INTEGRATED CIRCUIT APPLICATION

(76) Inventors: Larry D. Webster, 8129 Rhoda Ave., Dublin, CA (US) 94568; Ehud Pardo, 121 Buckingham Dr. #33, Santa Clara, CA (US) 95051

( * ) Notice: Under 35 U.S.C. 154(b), the term of this patent shall be extended for 0 days.

(21) Appl. No.: 08/287,670

(22) Filed: Aug. 9, 1994

(51) Int. CI. G06F 1/26

(52) U.S. CI 713/330

(58) Field of Search 395/750; 364/707;

713/300, 320, 330

(56) References Cited

U.S. PATENT DOCUMENTS

4,593,349 * 6/1986 Chase et al 364/200

4,906,862 * 3/1990 Itano et al 307/296.3

4,950,921 * 8/1990 Takada 307/296.1

4,952,817 * 8/1990 Bolan et al 307/39

* cited by examiner

Primary Examiner—Glenn A. Auve (57) ABSTRACT

A nonvolatile power management apparatus that controls the use of power within an integrated circuit. The embodiment varies the power applied to a functional circuit within the integrated circuit. At nominal power, the functional circuit operates normally per nominal operational specifications. Under reduced power, the integrated circuit retains all of its internal states, but has its I/O nets isolated from external circuitry. This prevents latch-up of the functional circuit operating from reduced power (low power input voltage) and prevents external circuitry connected to the integrated circuit from being overloaded.

3 Claims, 4 Drawing Sheets