System for distributed priority arbitration among several processing units ...

[54] SYSTEM FOR DISTRIBUTED PRIORITY ARBITRATION AMONG SEVERAL PROCESSING UNITS COMPETING FOR ACCESS TO A COMMON DATA CHANNEL

[75] Inventors: Volmer Chiarottino, Villanova C. Se;

Cesare Poggio, both of Turin; Aldo
Reali, Caselle, all of Italy

[73] Assignee: Cselt Centro Studi E Laboratori

Telecommunicazioni S.p.A., Turin,
Italy

[21] Appl. No.: 318,254
[22] Filed: Nov. 4, 1981

[30] Foreign Application Priority Data

Nov. 6, 1980 [IT] Italy 68691 A/80

[51] Int. CI.' G06F 15/16; G06F 9/46

[52] U.S. CI 364/200; 370/85;

370/94

[58] Field of Search ... 364/200 MS File, 900 MS File;

370/94, 85, 104; 375/119

[56] References Cited

U.S. PATENT DOCUMENTS

3,818,447 6/1974 Craft 364/200

4.071.706 1/1978 Warren 179/15 AL

4,156,277 5/1979 Seitz et al 364/200

4,209,838 6/1980 Alcorn, Jr. et al 364/200

4,229,791 10/1980 Levy et al 364/200

4,232,294 11/1980 Burke et al 340/147 LP

4,292,623 9/1981 Eswaran et al 340/147 R

4,320,502 3/1982 De Veer 370/85

4,330,857 5/1982 Alvarez 370/104

4.357.707 11/1982 Delury 375/119

4,373,183 2/1983 Means et al 364/200

4,385,350 5/1983 Hansen et al 364/200

4,387,425 6/1983 El-Gohary 364/200

FOREIGN PATENT DOCUMENTS 1480208 7/1977 United Kingdom .

A system for the exchange of messages among a multiplicity of processing units includes a data channel and a service line interconnecting respective interfaces of these units. Each interface includes a busy-state detector determining during a test phase of a recurrent time slot whether the service line is available, a logic network connectable in a subsequent acquisition phase the service line in the event of its avai lability to emit successive bits of an address characterizing the respective processing unit, and a comparator determining during the aquisition phase whether an emitted address bit of a particular logic level ("1") coincides with another bit of a higher-priority level ("0") concurrently sent over the line by some other unit. If a higher-priority address bit is encountered, the emission of the address is aborted and restarted in a subsequent time slot. If there is no conflict, an outgoing message is delivered to the data channel by way of a concurrently enabled driver; should that message require more than one time slot for its transmission, the service line is seized by the emission of a busy bit in the test phases of one or more subsequent time slots preceding the last time slot occupied by that message.

6 Claims, 3 Drawing Figures

4,470,

SYSTEM FOR DISTRIBUTED PRIORITY ARBITRATION AMONG SEVERAL PROCESSING UNITS COMPETING FOR ACCESS TO A

COMMON DATA CHANNEL 5

FIELD OF THE INVENTION

Our present invention relates to a data-handling system with a multiplicity of processing units of different character, disposed not too far apart, dialoguing with 10 one another by an exchange of messages.

BACKGROUND OF THE INVENTION

With a relatively small number of such units it is not too inconvenient to provide them with individual con- 15 nections enabling the exchange of messages between any two of them. In a more elaborate system it is known to use time-division multiplexing by assigning to each unit a respective time slot in a recurrent frame; such a system, however, does not operate efficiently when 20 data are emitted by the several units at irregular intervals in the form of packets or bursts so that the average rate of utilization of each time slot is low. A further alternative, using a single bus for communication among all the processing units, requires rather complex 25 logical circuitry for arbitrating, on the basis of different priority levels, among simultaneous requests for access to the bus by several such units.

An arrangement of the latter type, in which a common communication channel or bus is randomly acces- 30 sible to the various processing units exchanging messages with a centralized station, is known as the Aloha System described by Norman Abramson and Franklin F. Kuo in Computer-Communication Networks published 1973 by Prentice-Hall, Inc. In that system the 35 problem of possible interference between concurrently emitted messages is solved by blocking the transmission of any overlapping packets and thereafter attempting their retransmission at different times. As the likelihood of collisions increases with the number of processing 40 units, the channel may remain unused for extended periods in a multi-unit system of this type.

OBJECT OF THE INVENTION

The object of our present invention, therefore, is to 45 provide means in such a data-handling system for facilitating the orderly exchange of messages among processing units of different ranks.

SUMMARY OF THE INVENTION 50

The processing units of our improved data-handling system have individual interfaces interconnected by two signal links, namely a common data channel and a common service line, a synchronizing signal being emitted over the service line by a timer during an initial 55 phase of a periodically recurring time slot. Each interface comprises message-transmitting means and message-receiving means inserted between the data channel and the associated processing unit, storage means containing a combination of address bits which characterize 60 the associated unit, a time base connected to the service line for detecting the initial phase of a time slot and establishing an acquisition phase following its initial phase, signal-generating means having an input connected to the storage means and an output connected to 65 the service line while being controlled by the time base and responsive to commands from the associated processing unit for sending out the address bits during the

110

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acquisition phase preparatorily to the emission of data via the aforementioned message-transmitting means, and comparison means connected to the service line and to the output of the signal-generating means for discovering during each of several bit periods of the acquisition phase a possible difference between the logic levels of an outgoing address bit emitted by the signal-generating means and an incoming address bit appearing concurrently on the service line. In the presence of such a concurrent incoming address bit, the emission of further address bits by the signal-generating means is prevented for the remainder of the time slot by the comparison means in the event of a predetermined difference between these bits indicating a higher priority of the incoming address bit. A connection between the signalgenerating means and the message-transmitting means enables the latter to be activated upon emission of the last address bit to deliver outgoing data to the channel in one or more subsequent time slots under the control of the time base.

If an outgoing message is to occupy more than one time slot, the interface may be further provided with discriminating means connected to the service line and with a down counter settable by the associated processing unit to a number k— 1 where k is the number of time slots required for a message to be sent out. The down counter controls the signal-generating means to cause the emission of a busy bit to the service line in a test phase (prior to the acquisition phase) of any time slot preceding the last time slot required by the outgoing message which is in the process of being transmitted, the down counter being decremented upon the emission of each busy bit. The time base controls the discriminating means to inhibit the signal-generating means during the acquisition phase of a time slot in whose test phase a busy bit is detected on the service line.

In the embodiment more particularly described hereinafter, an address bit having the logic level "0" takes priority over a logic level "1" of a concurrent address bit. Thus, the emission of further address bits by the signal-generating means of a given interface is prevented only if the outgoing address bit has the value "1" while the incoming address bit has the dominant value "0". This is particularly advantageous where the service line is constituted by a wire which can be grounded, e.g. through a transistor of the open-collector type, by a signal of logical value "0" emitted from any interface connected thereto. In principle, however, the logical value "1" could also be designated as the dominant one, as where that service line is an optical fiber illuminated by a high-level signal.

The addresses of the several intercommunicating processing units should, of course, be coded in conformity with their respective ranks on a scale of priorities. If the system includes two or more units of equal rank, the assignment of priorities to them will necessarily be somewhat arbitrary. In such a case we prefer to insert an inverter in the output of the signal-generating means which, in response to a command from the associated processing unit, complements an emitted address bit so that its code assumes a different rank in the priority scale; such complementation, of course, must not result in an address code duplicating that of another unit. The address codes will also have to be different from the bit combination representing the synchronizing signal.