United States Patent   Patent Number: 5,121,359
Steele  Date of Patent: Jun. 9, 1992
4,710.905 12/1987 Uzhida 365/229
Primary Examiner—Joseph A. Popek
Attorney, Agent, or Firm—Kenneth C. Hill; Lisa K.
Jorgenson; Richard K. Robinson
A programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information. A circuit is provided as part of the device for detecting loss of power on a supply input pin. When power loss is detected, a backup voltage supply, packaged with the programmable logic device as a unit, is connected thereto. The backup power is used to supply voltage only to those portions of the device having volatile memory elements containing configuration information. Backup power is not provided to input and output buffers of the device, thereby preventing excess loads being placed upon the backup device because of events which may occur external to the programmable logic device.
4 Claims, 2 Drawing Sheets
CONFIGURATION MEMORY FOR
PROGRAMMABLE LOGIC DEVICE
CROSS-REFERENCE TO RELATED
The present application is a continuation-in-part of U.S. patent Ser. No. 414,712, filed Sep. 29, 1989, titled CONFIGURATION MEMORY FOR PROGRAMMABLE LOGIC DEVICE, by Randy C. Steele, which is assigned to the assignee hereof.
The present application contains subject matter in common with co-pending U.S. application Ser. No. 414.695, titled LOGIC BLOCK FOR PROGRAMMABLE LOGIC DEVICE, by Randy C. Steele, filed on Sep. 29. 1989, now issued as U.S. Pat. No. 4,975,601 and U.S. application Ser. No. 502,572, filed on even date herewith, titled SRAM BASED CELL FOR PROGRAMMABLE LOGIC DEVICES, by Randy C. 2Q Steele, both of which are assigned to the assignee hereof and both of which are hereby incorporated by reference hereinto.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related generally to integrated circuit devices, and more specifically to programmable logic devices.
2. Description of the Prior Art 30 Programmable logic devices are becoming increasingly popular in the electronics industry because of their flexibility. These devices allow a user to configure
an integrated circuit chip, having a standard design, to perform the user's desired logic functions. Use of a 35 standard design to perform many different logic functions greatly decreases the cost per logic gate compared to custom designs, especially at smaller volumes. If changes or updates are needed to the programmed logic function, some types of devices can be reprogrammed. 40
One time programmable logic devices are very common. The user can program the devices, or have them programmed late in the production cycle at the semiconductor foundry. Such parts provide a low cost, but cannot be reprogrammed. Typical one time program- 45 mable logic devices are programmed using a final metal mask or fusible links.
Reprogrammable devices use non-volatile memory to retain configuration information. This information is used to define the logic functions performed by the 50 device, and to configure input and output buffers. Technologies commonly used for fabrication of such devices use EPROMS and EEPROMS for storage of configuration information. Since EPROMS are typically erased by exposing them to ultraviolet light, they are difficult 55 to reprogram without physically removing the integrated circuit from the system. EEPROMS are easier to reprogram, but still require the use of special programming voltages in external circuitry suitable for performing the reprogramming process. Reprogramming and 60 testing of both EPROMS and EEPROMS is relatively slow.
A few integrated circuit designs utilize static random access memories (SRAMs) for storage of configuration information. Use of RAMs to perform logic functions is 65 well known in the art. One technique for using SRAMs in programmable logic devices is to provide an array of SRAM blocks interconnected by switching matrices.
The switching matrices are also programmable, and are used to switch signals to various portions of the device.
A significant problem with the use of SRAM based programmable logic devices is the fact that these devices must be reconfigured whenever a system containing them is powered up. This requires that the system incorporating SRAM-based programmable logic devices includes some form of external non-volatile memory for storing configuration information and a mechanism for reloading such configuration information from the non-volatile memory into the programmable logic device on power up. These devices cannot retain their programming for later ready to use installation in a system.
It would be desirable to provide a programmable logic device which provide the flexibility of SRAMbased logic with the configuration retention properties of non-volatile memory devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a programmable logic device which utilizes random access memory for performing logic functions.
It is a further object of the present invention to provide such a programmable logic device which will retain configuration information without requiring that power be applied to the integrated circuit device.
Therefore, according to the present invention, a programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information. A circuit is provided as part of the device for detecting loss of power on a supply input pin. When power loss is detected, a backup voltage supply, packaged with the programmable logic device as a unit, is connected thereto. The backup power is used to supply voltage only to those portions of the device having volatile memory elements containing configuration information. Backup power is not provided to input and output buffers of the device, thereby preventing excess loads being placed upon the backup device because of events which may occur external to the programmable logic device.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a block diagram of an SRAM used to perform logic functions;
FIG. 2 is a block diagram of a portion of a programmable logic device utilizing the SRAM of FIG. 1;
FIG. 3 is a block diagram of a programmable logic device in accordance with the present invention; and
FIG. 4 is a block diagram of a programmable logic device in accordance with an alternative embodiment of the present invention.
DESCRIPTION OF THE PREFERRED
FIG. 1 illustrates a block diagram for a logic block 10 suitable for use on programmable logic devices. These logic blocks 10 are typically referred to as macrocells. A plurality of macrocells 10 are typically used on a