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US007068080B1
(12) United States Patent ao) Patent No.: Us 7,068,080 Bi
Sanders (45) Date of Patent: Jun. 27,2006
(54) METHOD AND APPARATUS FOR
REDUCING POWER CONSUMPTION
WITHIN A LOGIC DEVICE
(75) Inventor: Lester S. Sanders, Albuquerque, NM (US)
(73) Assignee: Xilinx, Inc., San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 10/347,054
(22) Filed: Jan. 17, 2003
(51) Int. CI.
mm n/oo (2006.01)
(52) U.S. CI 327/99; 327/544; 327/141;
326/93
(58) Field of Classification Search 326/37 41,
326/93, 95, 98; 327/199, 295, 291, 298, 327/403, 404, 407, 99, 544 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
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5,818,273 A * 10/1998 Orgill et al 327/199
5,844,844 A 12/1998 Bauer et al.
5,883,529 A * 3/1999 Kumata et al 326/93
6,072,348 A * 6/2000 New et al 327/295
6,204,695 Bl 3/2001 Alfke et al.
6,348,828 Bl * 2/2002 Barnes 327/298
6,466,049 Bl * 10/2002 Diba et al 326/37
6,472,904 Bl * 10/2002 Andrews et al 326/38
6,556,043 Bl * 4/2003 Garcia 326/40
OTHER PUBLICATIONS
Tomas Lang et al.; "Individual Flip-Flops with Gated Clocks for Low Power Datapaths"; IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing: vol. 44, No, 6; Jun. 1987; pp. 507-516.
A. Gago et al.; "Reduced Implementation of D-Type DET Flip-Flops"; IEEE Journal of Solid-State Circuits; vol. 28, No. 3; Mar. 1993; pp. 400-402.
Antonio G.M. Strollo et al.; "Analysis of Power Dissipation in Double Edge-Triggered Flip-Flops"; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 8, No. 5; Oct. 2000; pp. 624-629.
* cited by examiner
Primary Examiner—Vibol Tan
(74) Attorney, Agent, or Firm—W. Eric Webostad; Kim Kanzaki
