(54) MULTI-QUEUE FIFO MEMORY DEVICES
THAT SUPPORT FLOW-THROUGH OF
WRITE AND READ COUNTER UPDATES
USING MULTI-PORT FLAG COUNTER
(75) Inventors: Jason Zhi-Cheng Mo, Fremont, CA
(US); Prashant Shamarao, Alpharetta,
GA (US); Jianghui Su, Cupertino, CA
(73) Assignee: Integrated Device Technology, Inc.,
San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 328 days.
(21) Appl.No.: 11/080,704
(22) Filed: Mar. 15, 2005
Related U.S. Application Data
(60) Provisional application No. 60/555,716, filed on Mar. 23, 2004.
(51) Int. CI.
G06F 3/00 (2006.01)
G06F 5/10 (2006.01)
(52) U.S. CI 710/52; 710/53; 710/54;
710/55; 710/56; 710/57; 711/131; 711/142
(58) Field of Classification Search 710/14;
711/131, 142 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
4,486,854 A 12/1984 Yuni
Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.
7 Claims, 9 Drawing Sheets