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(12) United States Patent ao) Patent No.: Us 7,239,163 Bi

Ralston-Good et al. (45) Date of Patent: Jul. 3,2007

(54) DIE-LEVEL PROCESS MONITOR AND METHOD

(75) Inventors: Jeremy John Ralston-Good, Tucson, AZ (US); Philipp S. Spuhler, Tucson, AZ (US); Bert M. Vermeire, Phoenix, AZ (US); Douglas Leonard Goodman,

Tucson, AZ (US)

(73) Assignee: Ridgetop Group, Inc., Tucson, AZ (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.

(21) Appl. No.: 11/156,022

(22) Filed: Jun. 17, 2005

Related U.S. Application Data

(60) Provisional application No. 60/581,811, filed on Jun. 23, 2004.

(51) Int. CI.

G01R 31/02 (2006.01)

(52) U.S. CI 324/763; 324/765; 438/18;

257/48

(58) Field of Classification Search 324/763,

324/765, 158.1; 438/15-18; 257/48; 716/4, 716/116; 714/733-734 See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

4,243,937 A * 1/1981 Multani et al 324/765

4,413,271 A * 11/1983 Gontowski et al 257/48

5,039,602 A * 8/1991 Merrill et al 438/11

5,068,547 A * 11/1991 Gascoyne 326/16

5,631,596 A * 5/1997 Sporck et al 327/378

5,838,163 A * 11/1998 Rostoker et al 324/763

5,903,012 A * 5/1999 Boerstler 257/48

5,929,650 A * 7/1999 Pappert et al 324/763

6,124,143 A * 9/2000 Sugasawara 438/18

6,239,603 Bl * 5/2001 Ukei et al 324/763

6,476,414 Bl* 11/2002 Sekine 257/48

6,544,807 Bl * 4/2003 Bach 438/18

6,759,863 B2 * 7/2004 Moore 324/765

6,836,133 B2* 12/2004 Kinoshita 324/765

6,876,218 Bl * 4/2005 Simmons et al 324/763

6,891,389 Bl * 5/2005 Walker et al 324/763

OTHER PUBLICATIONS

Kazuo Terada et al., A Test Circuit for Measuring MOSFET Threshold Voltage Mismatch, IEEE, 2003, ICMTS 03-227-ICMTS 03-231.

J.A. Croon et al., A comparison of extraction techniques for threshold voltage mismatch, Proc. IEEE 2002 Int. Conference on Microelectronic Test Structures, Apr. 2002, vol. 15, pp. 235-240. T. Himeno et al., A New Technique for Measuring Threshold Voltage Distribution in Flash EEPROM Devices, Proc. IEEE 1995 Int. Conference on Microelectronic Test Structures, Mar. 1995, vol. 8, pp. 283-287.

* cited by examiner

Primary Examiner—Ha Tran Nguyen

Assistant Examiner—Arleen M. Vazquez

(74) Attorney, Agent, or Firm—Eric A. Gifford

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A die-level process monitor (DLPM) provides a means for independently determining whether an IC malfunction is a result of the design or the manufacturing processing and further for gathering data on specific process parameters. The DLPM senses parameter variations that result from manufacturing process drift and outputs a measure of the process parameter. The DLPM will typically sense the mismatch of process parameters between two or more test devices as a measure of process variation between a like pair of production devices. The DLPM may be used as a diagnostic tool to determine why an IC failed to perform within specification or to gather statistics on measured process parameters for a given foundry or process.

29 Claims, 8 Drawing Sheets

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