QUASI-SYNCHRONOUS INFORMATION TRANSFER AND PHASE ALIGNMENT MEANS FOR ENABLING SAME
BACKGROUND OF THE INVENTION 5
The invention generally refers to a method of quasisynchronously transferring clocking-, data-, and/or control signals between two or more data processing units and to a phase alignment means for enabling same.
FIGS. 1A-C show a block diagram and timing dia- 10 grams of how a synchronous and an asynchronous interface work. Since they are widely known, only the important summary points are dealt with in the following:
Synchronous Interface (FIG. 1A, B) 15 The clock signals of units A and B have the same
frequency and the same phase relationship. One data transfer can occur every cycle via connecting cables 1 and/or 2. Any interface delays must be adjusted to exactly align 20 the internal clocks of both units. For a system involving a cable and interface drivers, this may be a very difficult job to realize. As can be seen from FIG. IB, a synchronous interface can be used to send data from unit A to unit B or 25 vice versa without waiting to see if unit B or A received each data transfer successfully (correctly). The synchronous interface, however, requires that the sender and receiver be in a "lock-step" with one another which means that the receiver reads the data at the same time 30 the sender sends the data.
FIG. IB shows an example, where a section of six clock cycles 1A ... 6A, IB ... 6B respectively are used to transfer six data units (bits, bytes, words, etc. depending on the number of parallel lines) Dl... D6, D10 .. 35 . D15 respectively from unit A to unit B and/or vice versa.
The clock pulses of the internal clock of unit A and unit B have the same frequency and phase, as can be seen from FIG. IB. Data unit Dl which is sent during 40 clock cycle 1A of unit's A internal clock via cable 1 will be received at unit B during the next clock cycle 2B of unit's B internal clock. Data unit D10 which is sent from unit B over cable 2 at the same time as data unit Dl will be received at unit A during clock cycle 2A of unit's A 45 internal clock.
Asynchronous Interface (FIG. 1A, C)
The clock signals of units A and B have different frequencies and different phase relationships.
Multiple cycles are required for every data transfer. 50
Any interface delays can exist, within the required limits of propagation delay and skew. For this reason, many external interfaces from box to box are done asynchronously.
Using an asynchronous interface, unit A sends data, 55 one transfer at a time and waits to send the next transfer until unit B replies that it received the data correctly.
As can be seen from the pulse diagram in lines four and five of FIG. 1C, two more interface lines are necessary for transmitting control signals. In the case of a 60 data transfer from unit A to unit B a control signal from unit A is sent to unit B, meaning new data is on the bus. The other control signal is a reply signal from unit B sent to unit A, meaning unit B read the data.
As further can be seen from lines three and eight of 65 the pulse diagram in FIG. 1C, multiple cycles are required for every data transfer. To transfer a data unit Dl from unit A to unit B almost four clock A cycles are
necessary until this data unit Dl is completely captured at unit B. When data from unit B have to be transferred asynchronously to unit A then the complete process has to be reversed.
As can be seen from the description above, both interfaces have their advantages and disadvantages. The advantage of a synchronous interface is, that one data transfer can occur every cycle. Its disadvantage, however, is that any interface delays must be adjusted to exactly align the internal clocks of both units. An asynchronous interface has the advantage, that any interface delays can exist, within the required limits of propagation delay and skew; its disadvantage, however, is that multiple cycles are required for any data transfer.
Therefore, it is the object of the present invention to avoid the disadvantages listed above of both interfaces and keep at the same time their advantages.
SUMMARY OF THE INVENTION
The invention resides in a system and method for transferring data and/or control signals between two or more data processing units. According to the invention, one or more clock signals are generated in one of the data processing units. These clock signals are used to time processing within the one unit. Then, the clock signals and data signals and/or control signals are passed from the one data processing unit to another of the data processing units. The passed data signals and/or control signals have the same frequency and phase as the clock signals. The clock signals passed to this other unit are used to derive a clock for this other unit. Then, these clock signals are returned from this other unit to the one unit, along with data signals and/or control signals from this other unit. The returned clock signals are shifted in phase relative to the clock signals when generated in the one unit. Next, the phase of the data signals and/or control signals at the one unit passed from the other unit is shifted to match the phase of the clock signals when generated in the one unit. Afterwards, these data signals and/or control signals are used in the first unit.
Thus, the invention offers the data streaming advantage of synchronous interfaces without having to pay the penalty of asynchronous interfaces. The penalty that has to be paid is an added delay in the time it takes the first message from the sender to arrive at the receiver, but not in the overall data throughput.
Furthermore, the invention allows various parallel processor system designs where various lengths of interconnecting lines or cables can be used in a highly flexible manner.
Embodiments of the invention will be described in detail below with reference to the accompanying drawings in which:
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1A to 1C is a schematic representation of known synchronous or asynchronous interfaces and their respective pulse diagrams,
FIG. 2A, B is a schematic representation of a "quasi" synchronous interface and its pulse diagram, FIG. 3A is a block diagram of an interface shown in FIG. 2A,
FIG. 3B is a block diagram of a phase alignment circuitry necessary for use in "quasi" synchronous interfaces,
FIGS. 4A to 4D are schematic representations of a phase alignment circuitry shown in FIG. 3B;