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METHOD AND APPARATUS FOR
SUPPORTING SHARED LIBRARY TEXT
REPLICATION ACROSS A FORK SYSTEM
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a data processing system. In particular, the present invention relates to supporting shared library text replication in a data processing system. Still more particularly, the present invention relates to a method and apparatus that supports shared library text replication across a fork system call.
2. Description of Related Art
Under most UNIX environments, a system call named fork is provided to replicate a process to create a new process. One of these environments is Portable Operating System Interface (POSIX). POSIX is a standard published by IEEE that describes a UNIX-based system call interface that supports multiple platforms. POSIX system call interface includes a programming model that handles multithreading. A thread is a process or task managed by the kernel or the operating system. When multiple threads are executing at the same time, each thread may execute in another thread's address space.
In POSIX system call interface, a fork system call causes a process to create an exact copy of itself. The fork system call creates a new process called a child process. The original process is called a parent process. The child process has its own process identifier and address space. Thus, using the fork system call, an application may create copies of executable program code in many different physical memory locations at the same time. The replication of executable program code is known as text replication.
Text replication may not be difficult to implement in applications that have no shared state between a parent and a child process. The child and parent processes may each have its own address space, which allows the text addresses to be different in the parent and the child. Many applications use exec system call immediately after the fork system call, which loads a new program code, instead of using the fork system call to provide an alternative mechanism for replicated text.
However, text replication may be difficult to implement in applications that require data sharing between parent and child processes. An example of these applications includes DB2 Universal Database, a product available from International Business Machines Corporation. These applications often use fork system calls to instantiate their work. The use of fork system calls requires each child and parent process to have the same effective or program addresses, while each replicated shared library may be optimized to have different physical addresses local to the shared library's affinity domain. An affinity or memory domain is a group of processors and a region of memory that is local to the group of processors and is most efficiently accessed by the group of processors.
Furthermore, the shared libraries are accessed globally by different applications and programs on the system. Therefore, it would be advantageous to have a mechanism that can transparently replicate text or shared library code for new processes created by the fork system call.
SUMMARY OF THE INVENTION
The present invention provides a method for supporting shared library text replication across a fork system call. The
5 present invention detects a fork system call by a first process with a first affinity domain and creates a second process as a replication of the first process. The present invention then selects a second affinity domain for the second process. Upon determining that a replication of the replicated shared library
10 is present in the second affinity domain, the present invention maps effective addresses of the replication of the replicated shared library to physical addresses in the second affinity domain.
15 BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further obj ectives
20 and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a pictorial representation of a data processing
25 system in which the present invention may be implemented in accordance with a preferred embodiment of the present invention;
FIG. 2 is a block diagram of a data processing system is shown in which the present invention may be implemented; 30 FIG. 3 is a diagram illustrating basic concepts of virtual and physical memory in accordance with a preferred embodiment of the present invention;
FIG. 4 is a diagram illustrating an exemplary implementation of address mapping in a POWERPC microprocessor 35 architecture in accordance with a preferred embodiment of the present invention
FIG. 5 is a diagram illustrating an exemplary implementation of a mapping mechanism that maps effective addresses to physical addresses in accordance with a preferred embodi40 ment of the present invention;
FIG. 6 is a diagram illustrating an exemplary shared library replication using the mechanism of the present invention in accordance with a preferred embodiment of the present invention; and
45 FIG. 7 is a flowchart of a process for supporting shared library text replication across a POSIX system call interface fork in accordance with a preferred embodiment of the present invention.
50 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
With reference now to the figures and in particular with reference to FIG. 1, a pictorial representation of a data pro
55 cessing system in which the present invention may be implemented is depicted in accordance with a preferred embodiment of the present invention. A computer 100 is depicted which includes system unit 102, video display terminal 104, keyboard 106, storage devices 108, which may include floppy
60 drives and other types of permanent and removable storage media, and mouse 110. Additional input devices may be included with personal computer 100, such as, for example, a joystick, touchpad, touch screen, trackball, microphone, and the like. Computer 100 can be implemented using any suit
65 able computer, such as an IBM server computer or IntelliStation computer, which are products of International Business Machines Corporation, located in Armonk, N.Y. Although the
depicted representation shows a computer, other embodiments of the present invention may be implemented in other types of data processing systems, such as a network computer. Computer 100 also preferably includes a graphical user interface (GUI) that may be implemented by means of systems 5 software residing in computer readable media in operation within computer 100.
With reference now to FIG. 2, a block diagram of a data processing system is shown in which the present invention may be implemented. Data processing system 200 is an 10 example of a computer, such as computer 100 in FIG. 1, in which code or instructions implementing the processes of the present invention may be located. Data processing system 200 employs a peripheral component interconnect (PCI) local bus architecture. Although the depicted example employs a 15 PCI bus, other bus architectures such as Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) may be used. Processor 202 and main memory 204 are connected to PCI local bus 206 through PCI bridge 208. PCI bridge 208 also may include an integrated memory controller and cache 20 memory for processor 202. Additional connections to PCI local bus 206 may be made through direct component interconnection or through add-in connectors. In the depicted example, local area network (LAN) adapter 210, small computer system interface SCSI host bus adapter 212, and expan- 25 sion bus interface 214 are connected to PCI local bus 206 by direct component connection. In contrast, audio adapter 216, graphics adapter 218, and audio/video adapter 219 are connected to PCI local bus 206 by add-in boards inserted into expansion slots. Expansion bus interface 214 provides a con- 30 nection for a keyboard and mouse adapter 220, modem 222, and additional memory 224. SCSI host bus adapter 212 provides a connection for hard disk drive 226, tape drive 228, and CD-ROM drive 230. Typical PCI local bus implementations will support three or four PCI expansion slots or add-in con- 35 nectors.
An operating system runs on processor 202 and is used to coordinate and provide control of various components within data processing system 200 in FIG. 2. The operating system may be a commercially available operating system such as 40 Windows XP, which is available from Microsoft Corporation. An object oriented programming system such as Java may run in conjunction with the operating system and provides calls to the operating system from Java programs or applications executing on data processing system 200. "Java" is a trade- 45 mark of Sun Microsystems, Inc. Instructions for the operating system, the object-oriented programming system, and applications or programs are located on storage devices, such as hard disk drive 226, and may be loaded into main memory 204 for execution by processor 202. 50
Those of ordinary skill in the art will appreciate that the hardware in FIG. 2 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash read-only memory (ROM), equivalent nonvolatile memory, or optical disk drives and the like, may be used in 55 addition to or in place of the hardware depicted in FIG. 2. Also, the processes of the present invention may be applied to a multiprocessor data processing system.
For example, data processing system 200, if optionally configured as a network computer, may not include SCSI host 60 bus adapter 212, hard disk drive 226, tape drive 228, and CD-ROM 230. In that case, the computer, to be properly called a client computer, includes some type of network communication interface, such as LAN adapter 210, modem 222, or the like. As another example, data processing system 200 65 may be a stand-alone system configured to be bootable without relying on some type of network communication inter
face, whether or not data processing system 200 comprises some type of network communication interface. As a further example, data processing system 200 may be a personal digital assistant (PDA), which is configured with ROM and/or flash ROM to provide non-volatile memory for storing operating system files and/or user-generated data.
The depicted example in FIG. 2 and above-described examples are not meant to imply architectural limitations. For example, data processing system 200 also may be a notebook computer or hand held computer in addition to taking the form of a PDA. Data processing system 200 also may be a kiosk or a Web appliance.
The processes of the present invention are performed by processor 202 using computer implemented instructions, whichmay be located in a memory such as, for example, main memory 204, memory 224, or in one or more peripheral devices 226-230.
The present invention provides a method, apparatus and computer instructions for supporting shared library text replication across a fork system call, such as a POSIX system call interface fork system call. The present invention provides a mapping mechanism that maps process or effective addresses that represent text or shared library code to multiple physical addresses for the target objects based on an affinity domain. Target objects maybe, for example, text or shared libraries.
For each shared library, the operation system maps one copy of physical pages per affinity domain. Thus, on a 32-way system with 4 affinity domain, there are up to 4 unique copies of each replicated library. Each copy of physical pages may then be mapped to virtual memory, such that unused portions of the shared library code will not require physical memory until the code is accessed.
The mapping mechanism of the present invention uniquely identifies a set of virtual mapping for a set of physical pages. The set of virtual mapping includes a range of virtual addresses that is associated with a particular affinity domain. For example, a virtual address range of0x1000 to 0x10000 is associated with affinity domain 0. The set of physical pages includes multiple physical addresses that include actual instructions and data of the processes.
When an application invokes a fork system call, the present invention determines if the parent process has mapped any of the target objects, such as text or shared libraries. This call happens when one or more threads of the parent process are executing and the child process is not yet running. If the parent has mapped one or more target objects, the child process may use the mapping mechanism provided by the present invention to map the effective addresses to the physical addresses on the target object's affinity domain. In this way, the child process's effective address is identical to the parent process, but the physical address of the child process is unique.
In addition, the present invention may also be used to migrate a process from one affinity domain to another, in order to achieve text affinity. When a process's execution involves its movement from one affinity domain to another, the operating system may detect this movement and change the effective to virtual mapping using the mapping mechanism of the present invention to allow shared library mapping to the new affinity domain. Thus, using this mapping mechanism, the program is no longer required to access virtual mapping from the previous affinity domain. Accessing local memory instead of remote memory results in superior performance.
Turning now to FIG. 3, a diagram illustrating basic concepts of virtual and physical memory is depicted in accordance with a preferred embodiment of the present invention.
As shown in FIG. 3, a data processing system, such as data processing system 200 in FIG. 2, may include a virtual memory system 300. Virtual memory system 300 creates an illusion of single-level store with access time of random access memory rather than that of a disk. Virtual memory 5 space 302 is divided into uniform virtual pages 304, each of which is identified with a virtual page number 306. Physical memory 308 is divided into unique page frames 310, each identified by a page frame number 312. Page frames 310 hold program instructions or data. Generally, a given virtual page 10 can only have one physical location. However, it is possible to have several virtual pages mapped to the same page frame.
Turning now to FIG. 4, a diagram illustrating an exemplary implementation of address mapping in POWERPC microprocessor architecture is depicted in accordance with a preferred 15 embodiment of the present invention. As illustrated in FIG. 4, POWERPC microprocessor, a product available from International Business Machines Corporation, may be implemented in processor 202 of data processing system 200 in FIG. 2. 20
In the POWERPC microprocessor architecture, a process address space may be composed of many contiguous regions of virtual memory space known as segments. In this example, there are 3 segments: segment 402, 404, and 406. Segments are typically, but not necessarily larger than pages and each 25 segment is 256 MB in size. Therefore, segment 402 has address starting from 0 to 256 MB-1. Typically, in the POWERPC microprocessor architecture, address mapping are performed in two stages.
In the first stage, effective or program addresses 401 are 30 mapped into virtual addresses 407 in the granularity of segments. The hardware may provide a register to hold the process's effective and virtual segment identifiers. The effective segment identifiers may be determined by dividing the effective address by 256 MB. The virtual segment identifiers may 35 be allocated by the operating system. Once the mapping of the first stage is complete, virtual address space now includes 3 corresponding segments of virtual addresses 407: segment 408, 410, and 412.
In the second stage, virtual addresses 407 in the virtual 40 memory space are mapped onto physical addresses 413 in the granularity of pages 414. In this example, virtual addresses 407 of segments 408, 410, and 412 are mapped to pages 414 of physical addresses 413. Pages 414 are each 4096 byte in size. Virtual segments 408,410, and 412 may be sparse, since 45 not all addresses have physical pages mapped to them.
Thus, in the POWERPC microprocessor architecture, virtual mapping can be performed easily as the architecture itself provides a mapping from effective segments to virtual segments and from virtual segments to physical pages. 50
Turning now to FIG. 5, a diagram illustrating an exemplary implementation of a mapping mechanism that maps effective addresses to physical addresses is depicted in accordance with a preferred embodiment of the present invention. As illustrated in FIG. 5, process 1 and process 2 both require 55 shared library A 502, which is replicated with the same effective address 504 of 0x1000. The present invention provides a mapping mechanism that maps virtual code addresses to physical addresses on the target affinity domain.
In this example, there are two affinity domains: affinity 60 domain 0 and affinity domain 1. Each of virtual addresses 506 in affinity domain 0 are unique. Thus, virtual addresses A and B are unique to affinity domain 0. Similarly, virtual addresses 508 in affinity domain 1 are unique. Thus, virtual addresses C and D are unique in affinity domain 1. 65
Based on this virtual mapping that is unique in each affinity domain, mapped physical address for each process also is
unique to specific affinity domain. For example, physical addresses 510 are unique in affinity domain 0 and physical addresses 512 are unique in affinity domain 1. Thus, physical addresses W and X are each unique in affinity domain 0 and physical addresses Y and Z are each unique in affinity domain 1.
Turning now to FIG. 6, a diagram illustrating an exemplary shared library replication using the mechanism of the present invention is depicted in accordance with a preferred embodiment of the present invention. As shown in FIG. 6, program a 600 may invoke a fork system call to create a child process. When the fork system call is invoked, process 2 is created as a child of process 1. When process 2 is created, an affinity domain is selected for the new process, in this example, memory domain Y 605.
Since process 1 requires a replicated shared library, in this example, shared library 601, if no replicated shared library is present in process 2, replicate shared library 602 is created for process 2. Both shared libraries 601 and 602 share the same effective address 606. The present invention then performs a mapping of effective addresses 601 and 602 to physical addresses by first mapping effective addresses 601 and 602 to virtual addresses. This mapping may be accomplished by mapping each effective address to a different virtual address that is unique to the specific memory domain.
For example, effective address 601 is mapped to virtual address 608, which is unique to memory domain X 603. Effective address 602 is mapped to virtual address 610, which is unique to memory domain Y 605. In the POWERPC microprocessor architecture, this uniqueness may be achieved by assigning unique virtual segment identifiers (VSIDS) while maintaining the same effective segment identifiers (ESID). In addition, it is inexpensive to switch mapping using the virtual addresses, since each segment is only 256 MB in size.
After the virtual addresses 608 and 610 are mapped, the present invention completes the mapping by mapping virtual addresses 608 and 610 to pages of physical addresses that are unique to the specific memory domain. In this example, virtual address 608 is mapped to pages 612, which are unique to memory domain X 603. Virtual address 610 is mapped to pages 614, which are unique to memory domain Y 605.
Once the mapping is complete, the effective addresses of both processes remain the same, while their mapped virtual and physical addresses are different.
Turning now to FIG. 7, a flowchart of a process for supporting shared library text replication across a POSIX system call interface fork system call is depicted in accordance with a preferred embodiment of the present invention. As depicted in FIG. 7, the process begins when a program executes a fork system call (step 702). The operating system then executes the call (step 704) to create a new child process. When the child process is created, the operating system selects a memory or affinity domain for the child process (step 706).
Next, the program loader runs to determine what programs to run (step 708). These programs may include text and shared libraries. A determination is then made by the operating system as to whether the required shared library is a replicated shared library in the parent process (step 710). A replicated shared library is a shared library that may be shared by both parent and child processes, or more generally all of the processes in the system. When the child process is first created, it inherits the same effective address that points to the shared library, even though the child process has its own address space. The operating system may choose to replicate selected libraries or all libraries. The criteria for replication may be