An improved carpeting gate array having a plurality of basic cells (9) each comprising an N channel MOS transistor (8) and a P channel MOS transistor (7) continuously arranged in row and column directions comprises a logic cell region (20) comprising a plurality of basic cells (9) continuously formed...http://www.google.com.tw/patents/US4999698?utm_source=gb-gplus-share專利 US4999698 - Interconnection arrangement for a gate array
