CA1123948A - System arrangement for distribution of television games and the like - Google Patents

Abstract

F.8229 IMPROVED SYSTEM ARRANGEMENT
FOR DISTRIBUTION OF
TELEVISION GAMES AND THE LIKE

ABSTRACT

An ensemble of video game controlling programs are multiplexed (e.g., on a time division, word-interleaved basis) and distributed over a common communications link, e.g., a CATV
cable. Each authorized user station connected to the cable has an adapter with a read/write (RAM) memory disposed between a stored program controlled video game player and the cable.
A particular game specified at an input device of the user station selects the corresponding game program listing for reception and loading into the adapter RAM. Once loaded, the RAM causes the microprocessor controlled player to execute the selected game in a per se conventional fashion. When a new game is desired, the input device setting is changed to appropriately replace the adapter RAM contents with the instruction set for the new game.

Description

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Il DISCLOSURE OF THE INVhNTION
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This invention relates to electroni.c video games and, more specifically, to a communications system and terminal equipment permittiny subscribers at diverse receiving stations to select, xeceive/load and execute a desired one of an ensemble of video I games or the like~
Electronic video games are now a matter of common exper-ience. One class of such games involves "hitting" and i'hit"
~I spots traversing across the face of a television cathode ray ¦I tube in accordance with a set of rules to simulate contests ¦I such as ping pong, tennis, hockey and so forth. As used herein, - 1l "video games" i5 used generically for all such sports - as well ¦l as informational displays and other presentations of interest, ¦
I ~ dynamic and/or static, which may be developed on a user's television set.
. Such video games typica~lly have user controls for at least a portion of the display (e.g., to control paddle/racket ~osition . ' for ping pong/tennis), game controlling electronics, television master synchronizing signal generatin~ circuitry, and a modulator . to generate an output signal spectrum corresponding to a VHE' television channel to permit receptlon and display by a standard television receiver.
The "game" rule implementation is of two general forms.
First in time was the declicated, special. purpose "haraware"
approach, pursuant to which special purpose circuitry was built : 25 to perform one or, at best, a fixed and limited repertory of games. The other, "software" approach utilizes a microprocessor --. . .

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plaver which is controlled by a read only memory ~ROMl having stored therein a program containing the rules of one (or several) j games. In this software approach, games can be changed by simply replacing a ROM of a player with another RO~ loaded with i different microprocessor-controlling programming to implement ¦ the rules and constraints of a different game.
I It is an object of the present invention to provide improved -1¦ video game program distribution/user terminal eauipment apparatus.
i, More specifically, it is an o~ject of the present invention I to permit each subscriber station connected to a common commun-I ications medium te.g., a community antenna television (CATV) coaxial cable network~ to load a desired one of an ensemble of game-controlling program listings; and to thereafter execute ¦ the "game" of the selected program.
, The above and other objects of the present invention are l~realized in a specific, illustrative system arrangement wherein , . I
an ensemble of video game controlling programs are multiplexed (e.g., on a time division, word-interleaved basis) and distributed iover a common communications link, e.g., a CATV ca~le. ~ach I authorized user station connected to the cable has an adapter with a read/write ~RAM) memory disposed between a stored progxam controlled video game player and the cable.
A particular game speci~ied at an input device of the user station selects the corresponding game program listing for reception and loading into the adapter RAM. Once loaded, the R~ causes the microprocessor controlled pla~er to execute the selected game in a per se conventional fashion~ l~hen a new game is desired, the input device setting is changed to appropriately ; ~
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i replace the adapter RAM contents with the program listing for the new game.
¦ The above and other features and advantages of the present ¦ invention will become more clear from the following detailed ¦ description of a specific embodiment thereof, presented herein-¦ below in conjunction with -the accompanying drawing, in which:
Figure 1 is a block diagram depictin~ specific te'le~ision game program distribution, reception and utilization apparatus of the present invention; and 10 ! Figure 2 is a flow chart characterizing operation of a program controlled central processing unit 32 included in the Figure 1 embodiment. ' Referring now to Figure 1, there is schematically shown an improved system arrangement for distributing an ensemble of I television signals which includes as a part thereof, program j listings for implementing a plurality of television games. Again as stated hereinabove, the expression "television games" is used i generically and includes all simulated sports con-tests infor- !
1~ mational displays, and any passive or interactive pre~entation ' of interest. In overview, a system head end or co~mon station 10 ' is employed to generate and disseminate an ensemble of radio frequency signals, typically including a plurality of television programs (at VHF and/or mid, su~ or super band). There is further included one frequency band including a program instruc-tion carrier modulated with digital information correspondingto the program instruction set;s for a plurality of stored program microprocessor controlled video games~ Any communica-tions link may be employed. Thus, for example, the head end 10 may be , i , "

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connec-ted to an array of subscriber stations 12 (a representative one being shown in detail) via a common coaxial cable ll, e.g., a community antenna television (CATV~ or master antenna tele- i i vision (MATV) cable.
~ The program instruction set-s may be modulated and multi-¦ plexed onto the cable ll in any of numerous ways per se well known to those skilled in the art. For concreteness, it will be I assumed for specificity and not limitation, that the instruction ¦ sets for the ensemble o~ games modulate the program carrier i~
; ~ a *ime division interleaved fashion, with the words of successive~i game instruction sets serially following one another. That is, the plural bits forming one digital instruction (or one byte I thereof) for one program serially modulate the carrier, followed , ¦I by the next-in-order instruction from the next program listing 1' ana so forth. This repetitively continues until all instructions of all program sets have been transmitted, whereupon ~the entire .
" transmission cycle repeats. By way of further illustrative ~ I
particular formatting for the game program information transmitted at t~e beginning of an instruction cycle the head end lO-sends , a sequence of binary zero words (e.g., arbitrarily, fifteen in 1, number), followed in turn by a digital word specifyin~ the number of program instruction sets to be transmitted; any other desirable adm:inistrative header irformation; ~inally and principally followed by the time division multiplexed interleaved instruction sets themselves and any desired message terminating ords. It is assumed that the transmitted binar~ information includes a modulating process wi~h an embedded clock, i.e., where bit (digit) timing may be recovered from the received .

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' digital wave itself. Em~e~ded clock modulated schemes are se well known to those skilled in the art, e.g., including a ¦ transition each bit-time. Any other manner of obtaining bit synchronization between head end and each receiver location, per se well known, may alternatively be employed. Still in overview each subscriber station 12 connected via cable 11 to the head end 10, e~g., the illustrative station 12 shown in detail, includes adapter or interface apparatus connected to a per se known microprocessor (or other stored program i computing element) controlled video game player 30. More specifically, the adapter 12 apparatus includes a read/write I (RAM) memory 59 which stores the video game program instruction set desired for the subject station as signalled by a user via an input source 42r e.g., a keyboard, thumb wheel switch or 1' the like. A read only memory (ROM) 57 contains the fixed executive program for controlling RAM loading.
In general terms, the adapter apparatus 1~ receives the incoming video game program listing information under central processing unit (CPU) 3~ control. Of the ensemble of consecutive , interleaved instructionsj only those belonging to the desired game program listing are selected and stored in RA~ 59. Since I I
these are spaced apart by a number of intervening words of no present interest (corresponding to the nu~ber of other game programs multiplexed on the cable game channel), the composite Fig. 1 station data processing eauipment need operate relatively slowly vis-a-vis the word transmission rate obtaining where consecutively transmitted words are part of the same game controlling program.

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¦ ~hen all the program instructions for a desired game repose ¦ in RAM 59, the video game player 30 performs the game ~exeeutes ¦ -the program) in a ~ se conventional manner for sueh players I under control of the executive p~ogram in an internal ROP~ 39.
I To this end, a game/standard television ~rogram seleetor switch ¦ 65 is connected to its lo~er position to eonnect a s-tandard ¦ television reeeiver 67 to player 30. The player 30 generates ¦l television base band video and synehronizing siqnals under CPU
. 32 eontrol, employing ROM 39 for an executive program, RA~ 59 for speeifie qame eontrolling instruetions, player actuated input deviees (part of input.source 42) for spot display loeation . ¦ or other interae~ive response eontrol, and a RAM 41 for seratch :~ I pad memory. A modulator 44 and video carrier source 45 raise ~by a conventional hetrodyne process) the frequency of I the base band video modulation, eOg., to that of a standard television ehannel. . .
. 1 Again, player 30 operation is ~ se standard. Also, the ¦¦ reeeiver 67 may view regular television ~either directly or via 1 a converter) by placing switeh 65 in its upper position.
1 Accordingly, the remaining technieal discussion pertains to the manner in which a desired program set of the ensemble modulating i . the program carrier is received and loaded into RA~I 59.
The CPU 32 controls the various ane.illary elements conneetecl thereto via a eommon control bus 35 and, external to the player i 25 30, a command decocler 50. The command decoder 50 may ~simply comprise per se well known combinatorial coincidence gates (which also may distributed and located at the various controlled .~: elements~ for providing appropriate enabling, a.ddress, count and like signals. Thus the decoder 50 generates gate 22 (ROl) and 30 '-, 27 (RO2), ROM 57 (RO3) and address register (AR) enabling, RAM

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~ 59 read(R)/write(W), and a counter 25 plesettiny PRESET eommand j, signals responsive to CPU impressed cornmand words on the bus 35.
¦ Thus, particular ROM 57 and R~ 59 adaresses for reading or I writing are stored by eonditioning register 55 for loading I (aetive AR), and an address to be loaded sent by the CPU 32 on address/data bus 33. Similarly, eounter 25 is preset to a desired initial eount by a PRESET signal, and a particular count impressed by the CPU on data bus 33. Memory (57, 59~, latch 19 Il and eounter 25 CPU reading via bus 33 merely require eorresponding ¦¦ eontrol signalling.
Turning now to partieular operation for the illus~rative subscriber station 12 shown in detail in ~ig. 1 to depict RAM
59 proyram loading, demodulator 13 tunes and demodulates the data ~program instruetion) modulation on the program earrier.
The embedded cloek in the demodulated data digital wave is ¦, recovered at a eloek reeovery cireuit 16 (e.g~, an oseillator snychronized or -triggered by a bit-transition sensing di~feren-Il tiator). The demodulator 12 data output is delayed (elemen-t 14 !' to permit clock reeovery), and then cloeked into a shift register 20 l, 18. .
', It will be assumed that a digital "l" is transmitted for control purposes at the beginning of each data word, i~e., at ,; !
the beginning of each initialization and header word and each following instruction word. ~?hen this "l" initial bit of each word progresses to the last stage in the shift register 18, the Eull program instruction (or data of other significance) is eontained in register 18. Accordingly, a one-shot (monostable) circuit 21 is tric3gered to en-ter the incoming digital word in a word-preserving latch l9, thereafter clearinc3 register 18 via de-lay 24. At an appropriate time (see below) under central

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processing unit 32 control, the incoming latch l9-stored ~lord , passes through gate 22 and onto a data/address bus 33 for I delivery to the CPU 32 and RAM 59. (It is assumed that RAM
loading is via the CPU, although direct memory access may be , utilized.~
¦ The incoming received digital words, each signalled by an ¦ output pulse from one-shot circuit 21, are counted by a selec-tively preset counter 25, with the counter 25 contents being passed by a gate 27 to the CPU 32 on bus 33 under CPU control.
~, The counter 25 is preset by the CPV 32 to an initial number (more fully described below) such that it will reach a predetermined state (e.g., empty or all "ois"? when the I next word of the program set desired for reception resides in ; ¦~ latch 19 ready for transmittal to the CPU 32 and RAM 59. Thus, ¦~ the CPV 32 examines counter 25 via gate 27, and accepts infor-mation from latch 19 only when the counter 25 reposes in the predetermined (e~g., all "~") state. This conveniently discards all instructions of game controlling programs not presently desired for the RAM S9.
¦I Loading of instructions for the desired game into RAM 59 proceeds under stored (ROM 57) program controll and is typified ~i by the control program flow chart of Fig. 2. As a first matter, while the composite receiver is looking for the beginning of a composite interleAved message field, each incoming word stored ' in -the latch 19 is passed by the CPU 32 via gate 22 onto the data bus 33 for delivery to the CPU. Each incoming word may be signalled by any means per se~well known to those skilled in the art, eOg., by connec-ting the ou-tput of the one-shot circuit 21 to an interrupt port of the CPU 32; or by simply enabling , ~L~LZ3~3i4~
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, ga-te 27 sufficiently rapidly to note any change in the state of the coun-ter 25, such a state chanye correspondiny to receipt of a new incominy word. In the flow chart terms of Pig. 2 this is reported by the "READ W~RD" instruction 80. The CPU examines the incoming word to determine whether or not it is an initial one of the sequence of zeroes (branching test 82). If ik is not, control passes back to progra~ state 80 to again examine the incominy word for the initial "0" data. Correspondinyly, if the incoming word is a zero ("YES" branch from test 82) ! a computa-I tional storage variable "ZER0S" accumulating the number of"O's" is incremented by one (instruction 34) and the ZER~S
variable then tested to determine whether the requisite fifteen ¦ initialization words have been accumula-ted~ If they have I not, control returns to the program state 80 to look for the ~ next initialization word.
After the requisite fiEteen zeroes have been received ("YES"
I output from branching sta-te 85), the next following header ¦ information is read into appropriate storage cells. This ! includes at least data yielding the number of interleaved game 20 ¦I controlling programs modulating the program carrier which is stored in a RAM 41 variable location (NP), followed by any other ¦
desired administrative type header information, if indeed any is present.
Following completion of messaye synchronization (the fifteen "ZER0" words) and administrative type variable loadings, the CPU 32 presets the counter 25 to a value PRESET
such that the counter will he~at the predetermined state (assumed above to be all "O's") when a number of incoming words have passed and the firs-t instruction for the desired program --10-- ' I, I

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specified by the user at the input source 42 is then contained in the latch 19. The specific number to be initially preset j is given by the modulus (M0D) of the counter 25, i.e., its full I count state minus the sum of the fixed, known number of header i words and the number o the program desired for viewing (PN0) as determined by CPU 32. Thus, beginning from the PRESET state, the counter 25 will reach the predetermined cleared, or ¦ all zero state when the first instruction for the particular , desired program specified by the user via input source 42 is , contained in latch 19. Following counter 25 presetting (program function 89) and entry of header information (if any), the CPU
32 is released to do other work (if any) since the next following¦
sequence of words are first instructions for game contro].ling i programs other than that desired by the particular user at the , Fig. 1 adapter station.
The CPU 32 periodically examines the state of the counter 25 by issuing a gate 27 enabling R02 command via control bus 45 and command decoder 50. So long as the counter 25 is not at the ¦~ all zero predetermined state ("N0" output of branching test ~1 instruction g2), Fig. 2 control passes to the READ C0UNTER state I
1 90. This occurs until the counter 25 is in fact at the all zeroes predetermined state ("YES" output from test 92), thus indicating that the first instruction for the desired program is contained in latch 19. CPU inputs the contents of latch 19 via gate 22 (enabled by an active R01 signal at this time) and bus 33 (READ
W0RD state 93). Following this, the incom.ing instruction word is processed (if appropriate for storage format or other pur~
poses) and -the first instruction stored either as received or as modified during processing in the game controlling program R~M 59. The availability of new information in the latch 19 may ~L~123~

alternatively be signalled ~o CPU 32 by connec-ting the counter 25 overflow to a CPU 32 interrupt port.
The CPU next asks whether or not the subject incoming program listing is fully loaded in RP~ 59. For the assumed ¦ initial traverse through in the lower iterative program loop 32 i of Fig. 2, the program has of course not. been fully loaded in -the ("D0NE" test fails "NO" branch). The program tes-t 95 may be implemented in any manner ~_ se known -to those skilled in the art, e.g~, by terminating each program with a special .
I program completion code during head end 10 transmission.
Assuming the progr~m is not fully loaded in R~M 59 ("NO"
branch from test 95), the counter 25 is now preset by CPU 32 to a state equal to its modulus (M~D) minus the number of inter~
leaved programs (NP), thus assuring that the counter 25 will clear to the predetermined zero state when the next in-terleaved instruction for the desired game controlling program is 1 contained in latch 19. Following this counter 25 presetting ¦~ operation of flow chart state 96, the CPU 32 is again released . ¦ for other work if desired.
I ~s before, the CPU 32 reads the counter 25 (instruction state 98) looking for the data signalling all zero state ~test 99).
I' When new data is in hand, i.e , the next following instruction I for the interleaved program desired is ln latch 19, test 99 returns program instruction control -to state 93 to input the instruction whereupon it is processed if desired and stored in i RL~1 59 (flow chart block 9fi).
This lower loop of ~ig. 2 iteratively repeats until the desired game controll.i.ng program is fully contained in RA~1 59 ("YES" outpu-t of test 95). The composite ~ig. 1 arrangement 30is then in a condition to execute the desired television game with a complste program in RA~ 59, and ploqram control passes - 1 ` !
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with the game controlling program fully contained in RAM 59, Il the television game player 30 simply uses the RAM 59 as a pro-; gram memory and permits a user to execute the television I game via switch 65, the standard ~elevision receiver 67, and the input source 42 as long as desired.
When a new program is desired, the user simply changes the desired program ntDnber (thereby changing the computational i variable PN0) by changing his thumb wheel switch setting or the ¦l like, forming a part of data input source 42. This causes the new desired program to replace that previously reposing ini RAM
' 59 as above discussed. ~gain, the CPU may sense the desire for a new program in any way per se known to those skilled in the art. This may be done under sotware control simply comparing i the present setting of the program identifier in input source i . 42 with the previous setting available either directly as a ¦ storage variable or via the contents of the storage location P~lj0,, ¦l and switching to state 80 responsive to any change. Alternative-¦~ ly, as just one further example among many, a separate l' "change" button switch or the like may be included in input i source 42 to direc-tly signal CPU 32 as via a flag bit, interrupt ' I or the like that a new program is desired.
The above-descrlbed arrangement has thus been shown to readily permit plural suhscribers connected to a signal distri-bution medium such as a CATV cable or the like to implement adesired one of an ensemble head end of transmitted vldeo games by simply interposing adapter equipment 12 between a cable and a program controlled conventional game player 30.
The above-described arrangement is merely illustrative of the principles of the present invention. Modifications and I'' I
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, 1, 1 A r l:!LZ3948 adaptations thereo~ will be readily apparent to those s~illed ¦ in the art without departing ~rom the spirit and scope of the I present invention.

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Claims (9)

WHAT IS CLAIMED IS:

1. In combination in terminal means for recovering and utilizing a digital television game controlling program instruc-tion set serially transmitted on a common transmission medium;
program controlled television game playing means including a microprocessor, and a modulator coupled to said microprocessor for frequency converting an output of said microprocessor to the television radio frequency spectrum; a data bus and a further bus connected to said microprocessor; a program demodulator for recovering the transmitted digital program instruction set information; a plural stage shift register having an input connected to said demodulator for receiving, storing and shifting said recovered program information; means selectively connecting the outputs of said shift register stages with said data bus; and read and write memory means connected to said data bus and to said further bus and controlled by said micro-processor for storing the program instruction set recovered by said demodulator in said read and write memory.

2. A combination as in claim 1 wherein said terminal means includes selection means for recovering a desired one of plural time division multiplexed transmitted game program instruction sets, said selection means including input means for entering the designation of a particular one of said plural program instruction sets, and means actuated at spaced time intervals for loading successive instructions of the desired program instruction set in said read and write memory.

3. A combination as in claim 2 further comprising a coaxial signal distribution cable having said terminal means connected thereto, and head end means for impressing on said coaxial distribution cable a program carrier modulated with said plural time division multiplexed, interleaved digital television game controlling program instruction sets.

4. A combination as in claim 3 wherein said program instruction sets are modulated onto said carrier with an embedded clock, and further comprising clock recovery means connecting the output of said program demodulator and a clock input of said plural stage shift register.

5. A combination as in claim 2 further comprising a first read only memory included in said television game playing means and connected to said data and said further buses for storing television game program utilization instructions, and second read only memory means connected to said data and further buses for containing read and write memory means loading program instructions.

6. A combination as in claim 2 further comprising additional read and write memory means included in said tele-vision game playing means and connected to said data bus and said further buses, said additional read and write memory means being in part employed by said microprocessor as scratch pad memory during utilization of a digital television game.

7. A combination as in claim 2 further comprising counter means selectively changing its count responsive to complete incoming program instruction words being contained in said plural stage shift register, and means for connecting the output of said additional counter means with said data bus.

8. A combination as in claim 7 further comprising means for presetting said additional counter means to a count state dependent upon the number of time division multiplexed game programs received by said terminal means.

9. A combination as in claim 3 further comprising a standard television receiver, and means for connecting the input of said receiver to one of said television game playing means or to said cable.