CA1233259A

CA1233259A - High performance memory utilizing pipelining techniques

Info

Publication number: CA1233259A
Application number: CA000491265A
Authority: CA
Inventors: Robert A. Iannucci
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1985-04-15
Filing date: 1985-09-20
Publication date: 1988-02-23
Also published as: EP0199134A3; DE3686436T2; EP0199134B1; JPS61237289A; US4685088A; DE3686436D1; EP0199134A2; JPH0368476B2

Abstract

ABSTRACT OF THE DISCLOSURE

A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer. Consequently, as a result of the use of these latch circuits in a memory system, pipelining techniques are utilized in the memory system for the improvement of the performance of the memory system.

Description

}SIGH PERFORMANCE MEMORY SYSTEM

Field of the Invention 7 .. . .
The present invention relates to memory systems, and 9 more particularly, to a system and apparatus for 10 improving the performance of a memory system. 11 Description of the Prior Art 14 An examination of a traditional, prior art memory 16 system reveals a serious shortcoming: at any point 17 in a memory cycle, only a small fraction of the 18 total circuitry in the traditional memory system is 19 active. As a result, the address and data buses of 20 the memory chips in the traditional memory system 21 are unnecessarily idle for a substantial period of 22 time. Traditional solutions to this problem are 23 typically expensive and are based on the use of time 24 multiplexing across disjoint banks of memory chips. 25 In the time multiplexing scheme, the individual 26 memory chips are under-utilized, the memory chip 27 addressing logic is complex, and the interleaving 28 techniques performed by this time multiplexing 29 scheme are highly sensitive to addressing patterns 30 in order to achieve efficient use of the buses. 31 .
In the traditional memory system, the following READ 33 cycle is typical: A memory cell in a memory array 34 is selected by presenting a row address. The row 35 address is decoded into a l-of-n signal by a row 36 decoder, and is then repoured by driver circuits. 37 The red riven signals select the correct row in the 38 of : memory array. The selected row in the memory array 39 .
if .

~2332~9 is read by sense amplifiers. The column address is decoded by a multiplexer to select the appropriate 2 bit(s) from the row In a write cycle, the column 3 information is used to demultiplex the input data 4 which, in turn, modifies the selected row. 5 With regard to the READ cycle in the traditional 7 memory system, the locus of control flows through 8 the memory chip leaving circuits idle in its wake. 9 For example, while the memory array is being 10 accessed, the row decoder sets idle. It is only 11 after the end of a complete cycle that the circuits 12 may be reused. 13 Accordingly, it is a primary object of the present 18 invention to provide a memory system wherein the lo components of the memory system may be continually 20 and repeatedly utilized during a complete cycle of 21 operation thereby achieving maximum utilization of 22 the components which comprise the memory system. 23 .
It is another object of the present invention to 25 provide a memory system which utilizes pipe lining 26 techniques in lieu of interleaving techniques during 27 a READ from or WRITE to said memory system, the 28 pipe lining techniques achieving maximum utilization 29 of the components which comprise the memory system. 30 :
It is yet a third object of the present invention to 32 utilize said pipe lining techniques to achieve a net 33 increase in the number of memory references which 34 may be acco~nodated in a unit of time by a 35 particular memory system over non-pipelined 36 alternatives. 37 :~:

12~3~9 These and other objects of the present invention are accomplished by designing a memory system which 2 functions in accordance with a pipe lining technique. 3 In the memory system of the present invention, a 4 plurality of latch circuits are placed at strategic 5 locations within the memory system. For example, a 6 latch circuit is placed between a row decoder and a 7 driver circuit, between the driver circuit and a 8 memory array, between the memory array and a 9 plurality of sense amplifiers, and between the sense 10 amplifiers and a multiplexer. A plurality of other 11 latch circuits are placed at other locations within 12 the memory system for the purpose of implementing 13 the pipe lining technique within the memory system of 14 the present invention. The latch circuits store 15 data values which are propagating through the memory 16 system thereby permitting more frequent use of the 17 memory system. As a result, all of the components 18 of the subject memory system are continually and 19 repeatedly utilized during a complete cycle of 20 operation. 21 Further scope of applicability of the present 23 invention will become apparent from the detailed 24 description presented hereinafter. It should be 25 understood, however, that the detailed description 26 and the specific examples, while representing a 27 preferred embodiment of the invention, are given by 28 way of illustration only, since various changes and 29 modifications within the spirit and scope of the 30 invention will become obvious to one skilled in the 31 art from a reading of the following detailed 32 description. - 33 .

ENNUI - 3 _ ~23~2~9 BRIEF DESCRIPTION OX THE DRAWINGS

A full understanding of the present invention will 3 be obtained from the detailed description of the 4 preferred embodiment presented hereinbelow, and the 5 accompanying drawings, which are given by way of 6 illustration only and are not intended to be 7 limitative of the present invention, and wherein: 8 Figure 1 illustrates a circuit which exhibits the 10 property of a delay in time between the energization 11 of the circuit by an input signal and the generation 12 of a corresponding output signal from the circuit; 13 Figure 2 illustrates another circuit which exhibits 15 the property of the delay in time, this circuit 16 including a plurality of latch circuits thereby 17 illustrating the concept of pipe lining; 18 Figure 3 illustrates a typical memory system; 20 Figure 4 illustrates the clock signals which drive 22 the memory system of figure 3; 23 Figure 5 illustrates a memory system in accordance 25 with the present.. invention which utilizes the 26 concept of pipe lining illustrated in figure 2; and 27 Figure 6 illustrates the clock signals which drive 29 the latch circuits of figure 5. 30 ,. .
.

Referring to figure l, a circuit is illustrated 35 which exhibits-the physical property of a time 36 delay, that is, input signals are reflected as 37 output signals only after a period of time has 38 elapsed. In figure 1, a first input signal is 39 ENNUI _ g _ ''' .

~233Z~9 propagated from input terminal lo to output terminal 20 by way of circuit (1) 12 (abbreviated CUT (l)), 2 circuit (2) 14 (abbreviated CUT (2)), and circuit 3 (3) 16 (abbreviated CUT (3)). second input signal 4 may not begin its propagation through the circuit of 5 figure 1 until the first input signal appears at 6 output terminal 20. Unnecessary idle time is 7 experienced with respect to the components of the 8 circuit of figure 1. For example, CUT (1) 12 9 remains idle while the first input signal propagates 10 through CUT (2) 14 and CUT (3) 16. 11 Referring to figure 2, another circuit is 13 illustrated exhibiting the same physical property of 14 a time delay as mentioned with reference to figure 15 1, this circuit utilizing the concept of pipe lining. 16 ....
In figure 2, CUT (1) 12 is connected at its output, 17 and CUT (2) 14 is connected at its input to latch 18 circuit 13. Similarly, CUT (2) 14 is connected at 19 its output and CUT (3) 16 is connected at its input 20 to latch circuit 15. In operation, when the first 21 input signal propagates from input terminal 10, the 22 first input signal becomes latched in latch circuit 23 13 in response to the clock signal "ILK". When the 24 first input signal is latched in latch circuit 13, 25 the second input signal at input terminal 10 may 26 begin its propagation through CUT (1) 12 of figure 27

2. When the first input signal is latched in latch 28 15, and the second input sign]. is latched in latch 29 13, a third input signal may begin its propagation 30 through the CUT (1) 12 of figure 2. Therefore, the 31 individual circuits, CUT 12, CUT 14, and 32 CUT 16, of figure 2. are more frequently utilized 33 relative to the CUT 12, CUT 14, and CUT 16 34 of figure 1. Furthermore, with respect to the 35 I circuit of figure 2, when the first input signal 36 arrives at output 20, a fourth input signal begins 37 its propagation through the CUT I 12; however, 38 with respect to figure 1, when the first input 39 ' ~233~59 signal arrives at output 20, the second input signal begins its propagation through the CUT (1) 12. 2 Therefore, the circuit of figure 2 is more efficient 3 than the circuit of figure 1. Moreover, the rate at 4 which subsequent inputs may be applied to the 5 circuit of figure 1 is inversely proportional to the 6 sum of the delays of CUT (1), CUT (2), and CUT (3) 7 whereas the rate at which subsequent inputs may be 8 applied to the circuit of figure 2 is inversely 9 proportional to the maximum of either CUT (1), CUT 10 (2), or CUT (3). Thus, assuming that CUT (1), CUT 11 (2), and Cut (3) are realizable, physical devices 12 whose time delay is strictly greater than zero, the 13 circuit of figure 2 must necessarily be able to 14 accept input values at a faster rate than the 15 circuit of figure 1. 16 Referring to figure 3, a typical memory system 30 is 18 illustrated. In figure 3, the memory system 30 19 , includes a memory array aye including a plurality of 20 ', rows and a plurality of intersecting columns, the 21 intersection of a single row and a single column 2 defining the location of a single memory cell. A 23 row decoder 30b is connected to each of the rows of 24 the memory array aye by way of a driver circuit 30c. 25 A row address is received by the row decoder 30b 26 from bus 30d by way of a row address register eye. 27 Each of the columns of memory array aye are 28 connected to corresponding inputs of multiplexer 30f 29 by way of a plurality of corresponding sense/refresh 30 amplifiers 30g. The functioning of the component 31 elements in the memory system 30 of figure 3 is 32 controlled by a timing and control circuit 30h. 33 ,~:
i In operation, referring to figure 3, a row address 35 on bus 30d is stored in row address register eye and 36 is decoded by row decoder 30b. The row decoder 30b 37 , develops one output signal energizing driver circuit 38 30c. The driver circuit 30c develops a corresponding 39 ~2332S9 output signal energizing and selecting the corresponding row of the memory array aye. The data 2 stored in each cell of the corresponding row is read 3 from the corresponding row of the memory array aye, 4 the data being represented by a plurality of output 5 signals developed from the memory array aye and 6 energizing the multiplexer 30f by way of the 7 sense/refresh amplifiers 30g. Since the bus is time 8 multiplexed with respect to the row and column 9 addresses, following the appearance of the row 10 address on bus 30d, a column address appears on bus 11 30d. The column address, on bus 30d, energizes the 12 multiplexer 30f thereby selecting one of the 13 plurality of output signals energizing the 14 multiplexer 30f. Therefore, data stored in one cell 15 of the corresponding row is read from memory array 16 aye and selected by multiplexer 30f in accordance 17 with the column address on bus 30d. 18 Referring to figure 4, a timing diagram is 20 illustrated associated with the memory system 30 of 21 figure 3. In figure 4, a Row Address Select (RAY) 22 clock signal is shown, this clock signal energizing 23 the row address register eye. A Column Address 24 Select (CAY) clock signal is shown, this clock 25 signal energizing column circuitry (not shown) of 26 the memory system 30 of figure 3. In figure 4, the 27 signal labeled "ADDRESS" comprises row and column 28 address signals, the row and column address signals 29 appearing on the bus 30d in a time multiplexed- 30 manner. Since the bus 30d is time multiplexed, a row 31 and column address will not appear on bus 30d 32 simultaneously. For example, when a row address 33 (Al) appears on bus 30d, a column address (C1) will 34 not appear on the bus. The RAY clock signal for 35 each access operation comprises a single pulse. As 36 shown in figure 4, the pulse RAY is associated 37 with the first access, and pulse RAY is 38 associated with the subsequent access. This is 39 !

i23~ 9 similarly true with respect to the CAY clock signal.
As drawn, both the RAY and CAY signals are logically 2 significant when low. Inn pulse RAY of the RAY 3 clock signal energizes the row address register eye, 4 a row address (Al), on buy 30d, is stored in the row 5 address resister eye. When an output signal is 6 generated from multiplexer 30f in response to the 7 row address stored in row address register eye, 8 pulse RUSS) of the RAY clock signal energizes the 9 row address register eye thereby storing another row 10 address (R2) in row address register eye. In figure 11 4, notice the cycle time between generation of pulse 12 RAY and pulse RAY of the RAY clock signal. 13 However, with respect to the memory system of figure 15

3, following the interrogation of the memory system 16 30 with a first row and column address, it is 17 necessary to wait for the generation of an output 18 signal from multiplexer 30f, representing a first 19 piece of data read from memory array aye, before a 20 second row and column address on bus aye may be 21 utilized for the interrogation of the memory system 22 30. Therefore, the individual element of figure 3 23 remain idle a large portion of the elapsed time 24 during the reading of the first piece of data from 25 array aye. Furthermore, the cycle time strictly 26 limits the rate at which new addresses may be 27 presented to the memory. 28 Referring to figure 5, a memory system 40 in 30 accordance with the present invention is 31 illustrated. The individual elements of the memory 32 system of figure 5-are utilized more frequently 33 during the reading of a single piece of data from 34 array aye relative to the elements of the memory 35 system of figure 3. Moreover, the cycle time is 36 dramatically reduced. Therefore, the memory system 37 of figure 5 is more efficient than the memory system 38 of figure 3. 39 ~Z3:3Z~;9 In figure 5, the memory system 40 comprises the memory array aye including a plurality of rows and a 2 plurality ox intersecting columns, the intersection 3 of a single row and a single column defining the 4 location of a single memory cell, similar to the 5 figure 3 memory array. The memory array aye of 6 figure 5 includes a separate column termed "locks" 7 Allah. The locks column Allah includes a plurality of 8 bits stored in column fashion therein. Therefore, 9 each row of the memory array aye of figure 5 10 includes a lock bit stored as part of the locks 11 column Allah. The function of the lock bit will be 12 described in the following paragraphs as a part of 13 the functional description of the present invention. 14 A row decoder 30b is connected to each of the rows ; 15 of the memory array aye by way of a driver circuit 16 30c. A row address is received by the row decoder 17 30b from bus 30d by way of a row address register 18 eye. however, a first group of latch circuits aye 19 are connected between the row decoder 30b and the 20 driver circuit 30c. A second group of latch 21 circuits 40b are connected between the driver 22 circuit 30c and the memory array aye. 23 Each of the columns of memory array aye are 25 connected to corresponding inputs of multiplexer 30f 26 by way of a plurality of corresponding sense refresh 27 amplifiers 30g. The functioning of the component 28 elements in the memory system 40 of figure 5 is 29 controlled by a timing and control circuit 30h. 30 However, a third group of latch circuits 40c are 31 connected between the sense amplifiers 30g and the 32 memory array aye. A fourth group of latch circuits 33 40d-~are~connected between multiplexer 30f and the 34 sense amplifiers 30g. the column address portion of 35 besides connected to multiplexer 30f by way of 36 four latch circuits latch circuits eye, 40f, 40g, 37 Andy, the four latch circuits being connected in 38 series fashion. The output of multiplexer 30f is 39 ~23~ 9 connected to a de-multiple~er 40i by way of three further latch circuits, latch circuits 40j, 40k, and 2 40L. The column address portion of bus 30d is 3 further connected to de-multiplexer 40i by way of 4 another latch circuit 40M. Another group of latch 5 circuits 40N is connected between the de-multiplexer 6 40i and the memory array aye. 7 Referring to figure 6, a plurality of waveforms 9 associated with the memory system I of figure 5 is 10 illustrated. In figure 5, a Row Address Select 11 (RAY) clock signal is illustrated, the RAY clock 12 signal being comprised of a RAY pulse, a RAY 13 pulse, and a RAY pulse. A Column Address Select 14 (CAY) clock signal is illustrated, the CAY clock 15 signal being comprised of a CAY pulse, a CAY 16 pulse, and a CAY pulse. The RAY and CAY clock 17 signals set the various latch circuits present in 18 the memory system 40 of figure 5. A signal termed lo ADDRESS comprises the various row and column 20 addresses (R1, Of, R2, C2, eta) present on bus 30d 21 in a time multiplexed manner shown in figure 5. In a 22 fashion identical to that of the circuit of figure 23 3, a row and a column address will not appear on bus 24 30d simultaneously. For example, when a row address 25 (R1) appears on bus 30d, a column address (C1) will 26 not appear on the bus. In figure 6, note that the 27 leading edge of the RAY pulse of the RAY clock 28 signal corresponds to the row address R1, the 29 leading edge of the CAY pulse of the CAY clock 30 corresponds to the column address Cal, etc. 31 The circuit of figure 6 observes the traditional 33 discipline of pipeline circuits controlled by a two 34 phase clock. These two clock phases are exactly the 35 signals RAY and CAST It is always the case that 36 each latch in the circuit is connected to either RAY 37 or CAST but never both. Furthermore, all latches 38 connected to RAY will operate on every RAY pulse, 39 ~233~59 In a similar fashion, all latches connected to CAY
will operate on every CAY pulse. Correct operation 2 requires that a latch set by a RAY pulse will 3 provide its output only to a latch set by a CAY 4 pulse; and a latch set by a CAY pulse will provide 5 its output only to a latch set by a RAY pulse. 6 Referring to figure 6, latch circuits eye, 40b, 40d, 8 40f, 40h, 40k, and 40n are all connected to the RAY 9 signal and are set in synchronism with one another. 10 The remaining latch circuits aye, 40c, eye, 40g, 11 40j, 401, and 40m are connected to the CAY signal 12 and are set in synchronism with one another. 13 The functional operation of the memory system 40 in 15 accordance with the present invention will be 16 presented in the following paragraphs with reference 17 to figure 5 of the drawings. 18 In figure 5, a first row address R1 and a first 20 column address Of appears on bus 30d in a time 21 multiplexed manner, the first row address Al 22 energizing row address register eye and being stored 23 therein in response to pulse RAY of the RAY 24 pulse. - 25 The first row address R1 is decoded by row decoder 27 30b, the row decoder generating output signals 28 representing the decoded first row address, the 29 decoded first row address being stored in latch 30 circuit aye in response to pulse CAY of the CAY 31 clock signal. When the CAY pulse is generated 32 storing the decoded first row address in latch 33 circuit aye, the first column address C1 is stored 34 in latch eye in response to pulse CAST 35 The decoded first row address energizes driver 37 circuit 30c, the driver circuit retransmitting a 38 signal representing the decoded first row address, 39 lZ33ZS9 the decoded first row address being stored in latch circuit 40b in response to pulse RAY (2) of the RAY 2 clock signal. In the meantime, the first column 3 address C1 is restored in latch 40f in response to 4 pulse RAY (2) of the US clock. signal. As a result, 5 latch circuits aye and eye are free for storage 6 therein of other row and column addresses. 7 Consequently, a second row address R2 energizes row 8 decoder 30b (aria row address register eye) and latch 9 circuit eye in a time multiplexed manner. 10 Therefore, at this point in time, the decoded first 11 row address is stored in latch circuit 40b in 12 response to pulse RAY of the RAY clock signal and 13 the first column address Of is stored in latch 14 circuit 40f in response to pulse RAY of the RAY 15 clock signal. A second row address is stored in row 16 address register eye. 17 A second column address C2 energizes row decoder 30b 19 (via row address register eye) and latch circuit eye 20 in a time multiplexed manner. A decoded second row 21 address is stored in latch circuit aye in response 22 to pulse CAY of the CAY clock signal and a second 23 column address C2 is stored in latch circuit eye in 24 response to pulse CAY of the CAY clock signal. 25 ; The decoded first row address, in latch 40b, 26 energizes memory array aye. The data stored in a 27 rough memory array aye, corresponding to the 28 decoded first row address, is read therefrom and 29 stored yin latch circuit 40c in response to pulse 30 CAY of the CAY clock signal. In the meantime, the 31 first column address is restored in latch circuit 32 Gwen response to pulse CAY of the CAY clock 33 signal. 34 The decoded second row address, in latch aye, is 36 restored in latch 40b in response to pulse RAY 37 of the RAY clock signal. The second column address, 38 unlatch 40~, is restored in latch 40f in response 39 :;

,: .

12332~;9 to pulse RAY of the RAY clock signal. Therefore, latch aye and eye are free, for storage therein, of 2 a third decoded row address and a third column 3 address, respectively. sup 30d supplies the third 4 row address R3, stored in row address register eye 5 during WAS. The data, corresponding to the first 6 decoded row address, stored in latch 40c, is sensed, 7 read from latch 40c, and stored in latch circuits 8 40d in response to pulse RAY of the RAY clock 9 signal. The first column address C1, in latch 40~, 10 is restored in latch 40h in response to pulse 11 RAY of the RAY clock signal. 12 Bus 30d supplies the third column address C3 in a 14 time multiplexed manner, a third decoded row address 15 being stored in latch aye in response to pulse 16 - CAY of the CAY clock signal, the third column 17 address C3 being subsequently stored in latch eye in 18 response to pulse CAY of the CAY clock signal. 19 Data stored in a row of memory array aye, 20 corresponding to the second decoded row address, in 21 latch 40b, is read and stored in latch circuits 40c 22 in response to pulse CAY of the CAY clock signal. 23 The second column address C2, in latch 40f, is 24 restored in latch 40g in response to pulse CAY 25 of the CAY clock signal. Bus 30d supplies the 26 fourth row address. The data stored in latch 27 circuits 40d, corresponding to the first decoded row 28 address, comprise a plurality of data elements 29 corresponding to the plurality of columns in the 30 memory array aye. One of the data elements, in 31 latch circuits 40d, is selected by multiplexer 30f 32 in accordance with the first column address C1, in 33 latch circuit 40h, energizing the multiplexer 30f. 34 Thin data element is stored in latch circuit 40j 35 in~respon5e to pulse CAY of the CAY clock signal. 36 At~thls point, the one data element, corresponding 37 to the first decoded row address and the first 38 I column address Of, is stored in latch 40j~ The data 39 '.

123~ 59 element is available for use at the output during the CAY I pulse. 2 The third decoded row address, in latch aye, is 4 restored in latch circuits 40b in response to pulse 5 WAS of the RAY clock signal. The third column 6 address C3, in latch eye, is restored in latch 40f 7 in response to pulse RAY of the RAY clock signal. 8 Therefore, latch aye and eye are free, for storage 9 therein, of a fourth decoded row address and a 10 fourth column address, respectively. Bus 30d 11 supplies a fourth row address R4, stored in the row 12 address register eye during RAY (4). The data, 13 corresponding to the second decoded row address, 14 stored in latch 40c, is sensed, read from latch 40c, 15 and stored in latch circuits 40d in response to 16 pulse RAY of the RAY clock signal. The second 17 column address C2, in latch 40g, is restored in 18 latch 40h in response to pulse RAY of the RAY 19 clock signal. 20 Note that the events which occur during the 22 generation of pulse RUSS) are identical to the 23 events which occur during the generation of pulse 24 RUSS). Similarly, the events which occur during 25 the generation of pulse CASEY) are identical to the 26 events which occur during the generation of pulse 27 CAST etc. Therefore, at this point, the memory 28 system of figure 5 has reached steady state 29 operation. 30 A write operation is fundamentally similar to the 32 read operation described above. Such a write 33 operation is described in the following paragraphs: 34 Referring to figure 5, a first row address R1 is 36 presented on bus 30d in a time multiplexed manner, 37 the first row address R1 energizing row address 38 register eye and being stored therein in response to 39 pulse RAY of the RAY pulse. Simultaneously, the datum to be written is applied to the "DATA AND LOCK 2 STATUS LINE" 40P thereby energizing latch 40k and 3 hying stored therein in response to the pulse 4 RAY (1) . The first row address Al is decoded by row 5 decoder 30b, the decoded first row address hying 6 stored in latch circuit aye in response to pulse 7 CAST simultaneously storing the column address C1 8 in latch Tom and the datum to be written in latch 9 40L. The decoded first row address energizes driver 10 circuit 30c, the driver circuit retransmitting a 11 signal representing the decoded first row address, 12 the decoded first row address being stored in latch 13 circuit 40b in response to pulse RASP In the 14 meantime, the first column address C1 is used to 15 properly route the datum to be written through the 16 demultiplexer circuit 40i, the demultiplexed output 17 being stored in latch circuit 40n in response to 18 pulse RASP The decoded first row address, in 19 latch 40b, energizes memory array aye. The data 20 stored in latch 40n is written to a row of memory 21 array aye corresponding to the decoded row and 22 column addresses. 23 As a result, due to the presence of the latch 25 I' circuits aye through 40N, the individual elements of 26 the memory array 40 of figure 5 are utilized more 27 Jo frequently, during either the reading or the writing 28 of a single piece of data from the memory array aye, 29 than are the individual elements of the memory array 30 30 of figure 3. As a result, the memory system of 31 figure 5 is more efficient and can support a shorter 32 - cycle time the memory system of figure 3. For these 33 Jo reasons, the memory system of figure 5 is superior 34 to the memory system of figure 3. 35 The functional operation of the memory system 40 of 37 the present invention in conjunction with the lock 38 bits stored in the locks column Allah of the memory 39 I

I, ::
I:, array aye of figure S will be presented in the following paragraphs with reference to figure 5 of 2 the drawing. 3 The pipeline memory system 40 of figure 5 may be 5 accessed my a plurality of independent but 6 communicating processes being carried out by one or 7 more possibly pipeline processors. For example, 8 during time if, process 1 may be accessing a 9 location in memory system 40, and during time to > 10 if, process 2 may be accessing the same location in 11 memory system 40. During time to > to, process 1 may 12 rickshaws the location in memory system 40, and 13 during time to > to, process 2 may rickshaws the 14 location in memory system 40. Assume that process 1 15 and process 2 are both performing read-modify-write 16 cycles. Since process 1 is performing a 17 read-modify-write cycle and data is read from memory 18 system 40 during time if, process 1 may not be 19 capable of writing new data to memory system 40 20 until time to. however, during this time frame, 21 process 2 is accessing the memory system 40, reading 22 data during time to. Process 2 should not be 23 allowed to read data from the location in question - 24 in memory system 40 until process 1 has completed 25 writing its new data to the same location in memory 26 system 40. 27 In order to prevent process 2 from reading data from 29 the location in question in memory 40 prior to the 30 completion of the writing of new data to the same 31 location in memory 40 by process 1, the lock bits of 32 the lock column Allah are utilized. When process 1 33 reads data from memory 40 during time if, the lock 34 bit associated with a row from which the data is 35 read is set, for example, to one (1). When processor 36 2 reads data from the same row during time to, it 37 reads a "one" lock bit. Therefore, process 2 cannot 38 read data from that row because the lock bit, which 39 lZ332S9 it read from that row, was set to one. When process 1 writes its new data to the row, the lock bit is 2 reset to Nero (0). If process 2 subsequently 3 retreads data from that row, since the lock bit 4 associated with that row is now a zero, process 2 5 can subsequently proceed to read the new data and 6 subsequently write newer data. 7 The invention being thus described, it will be 9 obvious that the same may be varied in many ways. 10 Such variations are not to be regarded as a 11 departure from the spirit and scope of the 12 invention, and all such modifications as would be 13 obvious to one skilled in the art are intended to be 14 included within the scope of the following claims. 15 .

EN98500l - 17 -:'

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a memory system for storing data, said data being written to and read from said memory system, the improvement comprising:

means disposed within said memory system for pipelining said data during the write of said data to said memory system or during the read of said data from said memory system.

2. A memory system, comprising:

memory means for storing data therein;

first circuit means for developing first accessing information, said first accessing information accessing said memory means for the purpose of retrieving data from said memory means;

second circuit means for receiving said data retrieved from said memory means in response to the accessing performed by said first circuit means utilizing said first accessing information;

first latch circuit means interconnected between said first circuit means and said memory means for latching said first accessing information therein;

second latch circuit means interconnected between said second circuit means and said memory means for latching said data therein corresponding to said first accessing information, said first latch circuit means latching second accessing information received from said first circuit means when said second latch circuit means latches said data therein corresponding to said first accessing information.

3. The memory system of claim 2, wherein said first circuit means comprises:

decoder circuit means for receiving information related to said first accessing information, decoding said information, and temporarily storing decoded information therein;

driver circuit means connected at its output to said first latch circuit means for receiving said decoded information and retransmitting said first accessing information in response thereto;
and third latch circuit means interconnected between said decoder circuit means and said driver circuit means for receiving said decoded information from said decoder circuit means and latching said decoded information therein, said decoded information subsequently causing said driver circuit means to retransmit said first accessing information, said first accessing information being latched in said first latch circuit means.

4. The memory system of claim 3, wherein said second circuit means comprises:

sensing means connected to an output of said second latch circuit means for sensing the existence of the data retrieved from said memory means via said second latch circuit means in response to the accessing performed my said first circuit means;

multiplexer means for selecting one element of the data sensed by said sensing means; and fourth latch circuit means interconnected between said sensing means and said multiplexer means for latching and temporarily storing the sensed data sensed by said sensing means.

5. The memory system of claim 4, further comprising:

a plurality of further latch circuit means serially connected to an input of said multiplexer means for developing an output signal, said multiplexer means selecting said one element of the sensed data in accordance with said output signal, said plurality of further latch circuit means corresponding in number to the number of latch circuit means functionally involved with the accessing of said memory means and with the receipt of the data retrieved from said memory means in response to said accessing.

6. In a memory system including a memory array, input circuitry connected to an input of said memory array for addressing said memory array with address information, output circuitry connected to an output of said memory array for receiving data retrieved from said memory array in response to the addressing of the memory array, and multiplexer means having an input connected to an output of said output circuitry for selecting one element of said data, the improvement comprising:

at least one first latch circuit means connected within said input circuitry for successively storing a plurality of address information, said plurality of address information successively addressing said memory array;

at least one second latch circuit means connected within said output circuitry for successively storing a plurality of data, said plurality of data being successively retrieved from said memory array in response to the corresponding plurality of address information successively addressing said memory array; and a plurality of further latch circuit means serially connected to another input of said multiplexer means for storing a plurality of selection information, the plurality of selection information successively selecting a corresponding plurality of the one elements of said data.