CA2121446C - Video signal encrypting apparatus - Google Patents
Video signal encrypting apparatus Download PDFInfo
- Publication number
- CA2121446C CA2121446C CA002121446A CA2121446A CA2121446C CA 2121446 C CA2121446 C CA 2121446C CA 002121446 A CA002121446 A CA 002121446A CA 2121446 A CA2121446 A CA 2121446A CA 2121446 C CA2121446 C CA 2121446C
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- Prior art keywords
- video signal
- memory
- address
- horizontal scanning
- generator
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
- H04N7/169—Systems operating in the time domain of the television signal
- H04N7/1696—Systems operating in the time domain of the television signal by changing or reversing the order of active picture signal portions
Abstract
A common circuit is used for scrambling and descrambling video signals. A memory stores key data. During scrambling the output of the memory is transmitted to a read address counter through an address generating circuit. Scrambling is effected by executing line rotation from a cut point. Descrambling is effected by the reverse of the aforementioned process.
Description
HF'f2-1J--1N~4 1;.~13 f-;i0P1 Rdtn~r 8 I=rest id ICI Fet.herstonhdugh P.04 VIpEO SIGNAL ENCRYPTING APPARATUS
i FIELD OLD THE INVPNTION ' a The present invention relates to a v~,deo signal encrypting apparatus for'processing signals ao that data contained in the signals may be maintained secret even if the.signals are stored on s storage device or transmitted i by saate111te, wireless communication, or wired communication or recorded by a video oamexa, v~,deo tape recordex, or optical dir~k. ~
. ~
BACKGROUND OF THE INVENTION
s 10 Recently, ass a result of advancements in various communication media such as communication satellites and recor8ing media, it has become posasiblQ to transmit and communicate information aver a wide area at high rates of speed. However, ae a consequence, it has df-4T ~ nnt~3033~eor~pstl . , i HI 'h--l=l-1~':r<1 1~~:id I-hIJYI liat.ner i~ lerestia IU I-etherstonhaugH~
i'.IdS
'- 2 -bes'come easier to access the information and more difficult to keep transmitted information secret.
Por example, information such as company communications which are transmitted by communication satellite anti internal experimental data are often transmitted on a recording media such as video tape (VT>
or optical disk.
The information transmitted in this manner is often in the form of pictures and sound which usually are confidential. This information is often protected by using a scramble encoder having a scrambling function. A
conventional scrambling encoder, however, usually requires a large encrypting system and encoder. In addition, the encrypting pracese ie complicated. ds a Z5 result, an apparatus for recording and reproducing secret information which is encoded in, for example, a VTR is large and expensive.
Fig. 11 is a block d~.agram of a conventional scrambling encoder. The conventional scrambling enaader includes a computer 101 (CPU1 for controlling the Scrambling encoder. A variety of computers such as a per~onal computer or a general-purpose Computer mzxy be r used for the CPU. In the conventional scrambling i encoder, video signals arid audio signals are applied to a i Z5 viddct sorambler 102 and an audio scrambler 103, i respectively. A key Signal which is~synchronized with the vid~o signal is formed by a key signal forming ci>~cuft 104. The key signal is superimposed by a superimposing circuit 105 on the video signal scrambled by the video scrambler lOZ. The audio signal .is frequency-modulated in an FM circuit 106 and mixed with the output of the I~uperimpoaing circuit 105 in mixing circuit 10'7 to produce a scrambled composite video and audio signal.
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The operation of the conventional scrambling encoder is described below. The video scrambler lOZ uses line rotation processing for randomly exchanging the scanning lines of video signals to perform scrambling.
The line processing uses a disconnection point of rotation for line rotation which ie determined by CPU
101. For example, if the disconnection point is value x, the disconnection point X would be encoded by a key signal (kj). Then, the encoded value X would be formed into a binary signal within the vertical blanking period ' by the key signal forming Circuit. Then, the audio signal is A/D Converted and a pseudo-random number sequence pulse signal (PN signal) is added to encode and scramble the audio signal. The initial value of the PN
signal is superimposed an the audio signal.
The scrambled signals are descrambled by a scrambling decoder. Far example, to descramble the scrambled sound signal, the initial PN signal value is provided to the PN generating circuit. Then, a PN ei.gnal series for descrambling is generated, and the scrambled signal is demodulated using the PN signal series. The video signal is descrambled by using the PN signal initial value in every field or specific period to determine the read start position of video signal in the horizontal i~canning period. The secrecy of the video and audio signal is maintained by not disclosing the algoritkun for encoding the sfgnale.
This conventional scrambling encoder and its Corresponding decoder are large and exgensive, and difficult to assefnble into a television receiver, video .
Gape recorder or video camera.
M'IS-R4-l~j=!4 lc~1~ i-h;Uli hat.ner aS I-'restia IU I-etY,erstonhaugh F'.!~'I
SUI~ARY OF THE INVENTION , The present invention relates to an encrypting apparatus which is suited for home use by downsizing and integrating the scrambling enCOder and its decoder.
~ The present invention further relates to a video signal encrypting apparatus for scrambling and descrambling video signals of a television signal. The apparatus includes a memory for holding key data for encrypting a pair of line memories which alternatively write horizontal scanning lines of an input video signal.
A hN generator is also provided for setting the key data in the memory as an initial value for producing mutually i different pseudo-random pulse signals for every horizontal scanning line. Rn address setting circuit is provided for setting a.value corresponding to the output of the PN generator as an initial value when scrambling. I
arid for setting a value as the output of the PN generator to be subtracted from the maximum address value of the ~
line memory to determine an initial value when deacrambling. Also included i» an address counter for generating an address which is the next subsequent address to the address set by the address setting circuit, and for applying addreel9 signals alternately to the pair of line memories.
, . The present invention further relates to a I
video signal encrypting apparatus for scrambling and .
deecrambling a video signal of a television signal. The apparatus includes a first nonvolatile memory fox storing key data for encrypting and a second nonvolatile memory for storing a reloadable code number Which includes a plurality of digitp. A Logic circuit is also provided ' for applying the outputs of the first and second nonvolatile memories. An input means is provided for entering tl-.e code number into the second memory. A pair of line memories are provided for writing the input video I
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rir rc- W mj'?-1 1.~~ lt. I-r~l_iln i~atner ri V'rescia IU Hr.th,rrstonhaugh, N.~~EI
. ~.3_ n,~~, i t: i i signals alternately for every horizontal scanning line.
A PN generator urea the output of the logic circuit to I set an initial value for producing mutually different pseudo-random pulr~e signals far every horizontal scanning line. Also included is an address setting circuit far setting a value corresponding to the output of the 8N
f generator as an initial value when scrambling, and for setting a value as the output of the PN generator to be subtracted from the maximum address value of the line memory to determine an initial value when descrambling.
Also included is an address counter far generating an address which is the next subsequent address to the 'I
address set by the address setting circuit and for .
applying address signals alternately to the pair of line i 15 memories.
The present invention further relates to a video signal encrypting apparatus further including an address setting circuit fax setting a value equal to the output of the PN generator which ie subtracted air output of the PN generator from the maximum address value of the line memory to set an initial value when scrambling, and ae a value corresponding to the output of the PN
generator which is used as an initial value to perform degcrambling. i I
I 25 . , Accordingly, an apparatus relating to the present invention uses one scrambling codes to ~ICramble ' and deecramble. When scrambling, the PN generator issues mutually different pseudo-random pulse signals for every horizontal scanning line. The signal corresponding to the output of the PN generator ie set ae an initial address value in the address counter by the address setting circuit. The address counter is incremented up to a maximum address from the set address, and then from a minimum address up to one before the set address. The address counter then applies the address signals rai K-L:J ij_~-l i~~.lt~ I-hlil~l IW tner is. f-'restva 10 I etherst.onhaugh N.V~:J
i FIELD OLD THE INVPNTION ' a The present invention relates to a v~,deo signal encrypting apparatus for'processing signals ao that data contained in the signals may be maintained secret even if the.signals are stored on s storage device or transmitted i by saate111te, wireless communication, or wired communication or recorded by a video oamexa, v~,deo tape recordex, or optical dir~k. ~
. ~
BACKGROUND OF THE INVENTION
s 10 Recently, ass a result of advancements in various communication media such as communication satellites and recor8ing media, it has become posasiblQ to transmit and communicate information aver a wide area at high rates of speed. However, ae a consequence, it has df-4T ~ nnt~3033~eor~pstl . , i HI 'h--l=l-1~':r<1 1~~:id I-hIJYI liat.ner i~ lerestia IU I-etherstonhaugH~
i'.IdS
'- 2 -bes'come easier to access the information and more difficult to keep transmitted information secret.
Por example, information such as company communications which are transmitted by communication satellite anti internal experimental data are often transmitted on a recording media such as video tape (VT>
or optical disk.
The information transmitted in this manner is often in the form of pictures and sound which usually are confidential. This information is often protected by using a scramble encoder having a scrambling function. A
conventional scrambling encoder, however, usually requires a large encrypting system and encoder. In addition, the encrypting pracese ie complicated. ds a Z5 result, an apparatus for recording and reproducing secret information which is encoded in, for example, a VTR is large and expensive.
Fig. 11 is a block d~.agram of a conventional scrambling encoder. The conventional scrambling enaader includes a computer 101 (CPU1 for controlling the Scrambling encoder. A variety of computers such as a per~onal computer or a general-purpose Computer mzxy be r used for the CPU. In the conventional scrambling i encoder, video signals arid audio signals are applied to a i Z5 viddct sorambler 102 and an audio scrambler 103, i respectively. A key Signal which is~synchronized with the vid~o signal is formed by a key signal forming ci>~cuft 104. The key signal is superimposed by a superimposing circuit 105 on the video signal scrambled by the video scrambler lOZ. The audio signal .is frequency-modulated in an FM circuit 106 and mixed with the output of the I~uperimpoaing circuit 105 in mixing circuit 10'7 to produce a scrambled composite video and audio signal.
r-.i K-.m m~'_,_J 1~~ l-l i~~.Ul~i i:ar,ner b 1'nrast.rtx IU I-~tIW
rstonh~euglv I'.db v N ~
The operation of the conventional scrambling encoder is described below. The video scrambler lOZ uses line rotation processing for randomly exchanging the scanning lines of video signals to perform scrambling.
The line processing uses a disconnection point of rotation for line rotation which ie determined by CPU
101. For example, if the disconnection point is value x, the disconnection point X would be encoded by a key signal (kj). Then, the encoded value X would be formed into a binary signal within the vertical blanking period ' by the key signal forming Circuit. Then, the audio signal is A/D Converted and a pseudo-random number sequence pulse signal (PN signal) is added to encode and scramble the audio signal. The initial value of the PN
signal is superimposed an the audio signal.
The scrambled signals are descrambled by a scrambling decoder. Far example, to descramble the scrambled sound signal, the initial PN signal value is provided to the PN generating circuit. Then, a PN ei.gnal series for descrambling is generated, and the scrambled signal is demodulated using the PN signal series. The video signal is descrambled by using the PN signal initial value in every field or specific period to determine the read start position of video signal in the horizontal i~canning period. The secrecy of the video and audio signal is maintained by not disclosing the algoritkun for encoding the sfgnale.
This conventional scrambling encoder and its Corresponding decoder are large and exgensive, and difficult to assefnble into a television receiver, video .
Gape recorder or video camera.
M'IS-R4-l~j=!4 lc~1~ i-h;Uli hat.ner aS I-'restia IU I-etY,erstonhaugh F'.!~'I
SUI~ARY OF THE INVENTION , The present invention relates to an encrypting apparatus which is suited for home use by downsizing and integrating the scrambling enCOder and its decoder.
~ The present invention further relates to a video signal encrypting apparatus for scrambling and descrambling video signals of a television signal. The apparatus includes a memory for holding key data for encrypting a pair of line memories which alternatively write horizontal scanning lines of an input video signal.
A hN generator is also provided for setting the key data in the memory as an initial value for producing mutually i different pseudo-random pulse signals for every horizontal scanning line. Rn address setting circuit is provided for setting a.value corresponding to the output of the PN generator as an initial value when scrambling. I
arid for setting a value as the output of the PN generator to be subtracted from the maximum address value of the ~
line memory to determine an initial value when deacrambling. Also included i» an address counter for generating an address which is the next subsequent address to the address set by the address setting circuit, and for applying addreel9 signals alternately to the pair of line memories.
, . The present invention further relates to a I
video signal encrypting apparatus for scrambling and .
deecrambling a video signal of a television signal. The apparatus includes a first nonvolatile memory fox storing key data for encrypting and a second nonvolatile memory for storing a reloadable code number Which includes a plurality of digitp. A Logic circuit is also provided ' for applying the outputs of the first and second nonvolatile memories. An input means is provided for entering tl-.e code number into the second memory. A pair of line memories are provided for writing the input video I
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rir rc- W mj'?-1 1.~~ lt. I-r~l_iln i~atner ri V'rescia IU Hr.th,rrstonhaugh, N.~~EI
. ~.3_ n,~~, i t: i i signals alternately for every horizontal scanning line.
A PN generator urea the output of the logic circuit to I set an initial value for producing mutually different pseudo-random pulr~e signals far every horizontal scanning line. Also included is an address setting circuit far setting a value corresponding to the output of the 8N
f generator as an initial value when scrambling, and for setting a value as the output of the PN generator to be subtracted from the maximum address value of the line memory to determine an initial value when descrambling.
Also included is an address counter far generating an address which is the next subsequent address to the 'I
address set by the address setting circuit and for .
applying address signals alternately to the pair of line i 15 memories.
The present invention further relates to a video signal encrypting apparatus further including an address setting circuit fax setting a value equal to the output of the PN generator which ie subtracted air output of the PN generator from the maximum address value of the line memory to set an initial value when scrambling, and ae a value corresponding to the output of the PN
generator which is used as an initial value to perform degcrambling. i I
I 25 . , Accordingly, an apparatus relating to the present invention uses one scrambling codes to ~ICramble ' and deecramble. When scrambling, the PN generator issues mutually different pseudo-random pulse signals for every horizontal scanning line. The signal corresponding to the output of the PN generator ie set ae an initial address value in the address counter by the address setting circuit. The address counter is incremented up to a maximum address from the set address, and then from a minimum address up to one before the set address. The address counter then applies the address signals rai K-L:J ij_~-l i~~.lt~ I-hlil~l IW tner is. f-'restva 10 I etherst.onhaugh N.V~:J
2~.~~~~~~ I
alternately to a pair of line memories to read the video signals alternately written in the pair of line memories.
Accordingly, line rotation is performed. The video signal is scrambled by reading the horizontal scanning lines from the line memories by using a different etarting~position.
When desarambling, while the video signals are written alternately into the pair of line memories, a value corre»ponding to the output of r_he PN generator is Subtracted from the maximum address value of the line memory Set by the address setting circuit as an initial value for each horizontal Scanning line. The address saunter is incremented up Go a maximum address from the seC address, and then from a minimum address up to one i before the set address. The address counter also applies i the address signal alternately to the pair of line memories. The address counter also reads the video ' Signal from the line memories to reproduce the original oignal. Thus, 'scrambling and deSCrambling can be performed using the same apparatus.
The present invention further relates to storing the key data in the first memory and for storing ' the adds number in the second memory. The code number is input by an input unit. Then a logic circuit produces from the data in the first and second memories a signal which is set as an initial value in the PN generator.
Thus, a more advancerd encrypting process fs realized.
The present invention further relates to setting the address of the address Setting circuit by subtracting the value of the output of the FN generator ' from the maximum address value of the line memory to set an initial value when scrambling. A value corresponding to the output of the pN generator is Set as the initial ' ~ralue when deacrambling.
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i HRIEF DESCRIPTION OF 'rHE DRAWINGS
Fig. 1 is a perspective view r3howing the appearance of a video signal encrypting apparatus in i accordance with a first exemplary embodiment of the present invention.
Fig. 2 is a block diagram showing the construction of video aigndl encrypting apparatus in accordance with a first exemplary embodiment of. the present invention.
1.0 Fig. 3 is a block diagram showing the construction of portions for acran871ing and descrambling I
of the video signal encrypting apparatus in a first' ' exemplary embodiment of the present invention.
Fig. 4 is a timing chart showing the operation of the first exemplary embodiment of the present invention.
Fig. 5 is a diagram showing an example of the signal configuration change of the horizontal scanning lines according to a first exemplary method of the ~
I present invention far scrambling and descrambling.
Fig. 6 is a diagram showing an example of signal configuration change of the horizontal scanning lines according to a second exemplary method of the preeent~invention for scrambling and deacrambling.
Fig. 7 is a block diagx'am showing the Construction of a video signal encrypting apparatus in t aCCOrdance With a second exemplary embodiment of the present invention.
Figs. 8a and eb are block diagrams showing two I 30 different examples of nonlinear shift registers of the second exemplary embodiment.
I
Fig. 9 is a block.diagram showing a third exemplary embodiment of the present invention.
Hf-'R-14-l9yA 12~1H FRllt°i Re~tner !4 Prestie 10 f=etherstonheugh f'.11 2~.21~~'~~
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Fig. 10 is a block diagram showing a Fourth exemplary embodimenC of tha present invention, Fig. 11 is a block diagram showing tha Construction of a conventional scrambling apparatus.
, i~ESCRIPTI0ri1 OF THfi PREFERRED EL~iEODIMENTB
OF THB INVEPtTTON
Fig. 1 is a perspective outline view of a video signal encrypting apparatus in accordance with an ' exemplary embodiment of the present invention. An input terminal 12 and an output terminal 13 are provided on a j Caging 11. The casing 11 also has a socket for attaching and detaching a read-only memory as-discussed below. The socket is covered by lid 14. The casing 11 also includes operation switches 18 cansisting of encoding start switch 15, decoding r3tart switch 16, and stop gwitCh 17.
Fig. 2 and Fig. 3 are block diagrams showing f tha internal construction of the video signal encrypting apparatus according to the first exemplary embodiment of the present invention. In Fig. 2, an input terminal 12 is connected to a clack pulse forming circuit 21, and A/D
Converter 22, and a 20H detector 23. The clock pulse forming circuit 21 forms a signal 4 fsc by reproducing a Color subcarrier (fsc) using the horizontal sync signal H
and vertical eyrtc signal V of the signal input at input terminal 12. The clock pulse forming circuit also feeds a clock t~ignal arid a gate pulse to other parts of the t apparatus as needed. The 20H detector 23 detects the .
video signal of the 20th horizontal scanning line (hereinafter called 20H), and i~ the brightness level of the 20H i5~ entirely white level, then the 20H detector provides a detection signal to CPU 24.
CYU 24 is used for controlling the operation of the different units which compris~ the video signal encrypting apparatus. Operation switches 18 are i t ~ , ,1 t 'y; '' , v Eu ;~ -1~1 mi'~~ l~:lLi 1 t<UI I tiatner r: I-'r~stia fU f-etherstonhaugh F', 1~
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connected to CPU 24. CPU 24 provides a trigger signal to an A/D converter 22 when scrambling is started as well as providing necessary r_ontrol signals to other unite in the video signal encrypting apparatus. Also provided is a nonvolatile memory 26 Which is connected through a read address generating circuit 25 to CPU 24. The nonvolatile memory 26 uses a read-only memory (ROM). The nonvolatile memory 26 is for storing key data which is desirably 64 or more bite, and for storing a read signal which is eventually provided to a PN generator 27.
The PN generator 27 includes a feedback shift register for generating a pseudo-random number sequence pulse signal (PN signal) of 16 bits. A predetermined B !
! bits among the 16 bit outgut ie provided to an MS8 ' inverting Circuit 28.
The output signal.pxovided to PN generator 27 ! i8 used to determine a cut point of the horizontal ~
scanning line. Tf there are 186 cut points in the one horizontal scanning line, the MSB exceeding 186 is 2o inverted. This is accomplished by MSH inverting circuit 28 which inverts the MSB of the output signal of the PN
generator 27. The output signal n, where Osns185, of the MSH inverting circuit is provided to address setting circuit 29. The address setting circuit 29 uses different methods to set an address. The first method is i to calculate and set the initial value o! a reading address for every horizontal scanning line. Accordingly, the initial value is 4n when scrambling. The initial !
! value for descrambling is 744-4n. This assumes that the maximum value of the reading address is 744 or four times the number of cut points of 186. Alternatively, a srecond method sets the initial value equal to ?44-4n when scrambling and 4n when descrambling.
Fig, 3 is a block diagram showing another part of the video signal encrypting apparatus. A clock signal 4 fsc is provided to a write address count~r 31 and a ;, .
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Hl~tl-l~l-1~~=!~7 1<:::1'~ I-I~UU1 I~:~tner & f-'restia fl) I-etherstonhnugh f'.1.3 read addrese~ counter 32 by the clock pulse foritting circuit 21 shown in Fig. 2. Address counters 31, 32 are counters used for counting input clocks. Address counters 31, 32 provide parallel output to selectors 33 and 34, respectively. An A/D converter 22 converts the stignals ~to digital Signals and provides the digital signals to line memories 35, 36. The changeover signals (H) are provided by clock pulse foxining circuit 21 to selector 33 and through inverter 37 to selector 34. Th~
1o changeover signals provided to the selectors 33, 34 are mutually inverted. Tn this process. the write address counter 31 and the read address counter 32 are alternated. Changeover signals which are synchronized with the horizontal sync signal H, are provided to selectors 33 dnd 34. Subsequently, the changeover signals are provided to line memories 35 and 36. Line j memories 35 and 36 are used for storing the video signals i corresponding to one scanning line having 744 dots, in 8 bite. Data corresponding to one horizontal scan line ie written into each line memories 35,36 at an address which is provided by write address counter 31 and selected by selectors 33, 34. The scan lines are alternately read out of the line memorise 35,36 using the read address i from the read a.ddresa counter 32 which is selected by ~electors 33, 34. Selector 38 selects the read signal !
Erom~the line memories 35 and 36. Selector 38 is '.
synchronized with seleetars 33, 34. The output of the j selector 38 is provided to D/A converter 39. D/A
converter 39 cortverte the selected signal into an analog signal. The output of D/A converter 39 is connected to output terminal 13.
. Memory 26, in Fig. 2, is an EPROM formed in pacnage 40 so that it is detachable.
The operation of the exemplary embodiment is described below with reference to the timing chart shown in Fig. 4. As an example, a VTR ie discussed below.
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- il First, to ecramt~le the video signal entering the input i terminal 12, the encoding start switch ~.5 is manipulated.
As a result, the encoding instruction (ciphering) is terminated at time tii and a signal is sent to CPU 29.
Then, CPU 24 sends a control signal to A/D converter 22, and generates a scramble trigger pulse. The A/1~
Converter 22 performs A/D conversion in accordance with i the clock pulse of_ the clock pulse forming circuit Z1.
At this time, the brightness level of the whole 20th horizontal scanning line is set to a white level axed is used as a scramble trigger pulse. F'or example, if a scramble trigger signal is generated at time tzl aftex' ' the start video signal t30, then enGOding of the video signal starts at t3z about 2 frames later than t21, at t32. This delay occurs because time is required to prepare the decoding process for the encoded signal.
Zf the video signal is not scrsmriled, the Video .
' signal is converted into an e-bit digital value in the A/b converter 22, and alternately written iota one of the line memories 35 and 36 for every horizontal scanning line. The converted Video signal is alternatively read out from the other line memory. In this Case, 7.ater than one line, the signal is issued to the D/A converter 39 i through the selector 39. In other words, an input signal ~
of one H line is written in the memory, and the written I
one H Nine signal is read out from the memory and outputted to the D/A converter 39 so that the output signal delays one H line from the input signal.
The scrambling of the video signal by line rotation ie explained below, mhe operation is started by adjusting the read address of the line memory to the cut point of the video signal. The cut point is the changeover.positiort for line rotation which is also the changeover signals of the scanning line. The 8-bit output from the PN generator 27 is used as the cut point.
The cut point is defined within the maximum of the t , , ~u N...1,J l'~~_~.J 1~':~~1 I lc~lll ;~a~nrr k FY-est~a ILI hetlverstonhaugh I-'.1~
I
~ 12 -maximum address 186 of the line memory as mentioned ax>ove. The MSS of the out point is inverted by the M9H
I inverting circuit 28 if the cut point exceeds 186. The output of the M5H inverting circuit 28 is an 8-bit signal having an address value of 0 to 185. Tha value is different for every line.
For example, set the value equal to n. In the address getting circuit 29, 4n is preset until the end of the Z2nd horizontal scanning line of the video signal supplied to the input terminal 12 (c:orrespanding to the 21st horizontal scanning lime in the output o~ D/A
converter 39). This is when 4 x n scrambling is performed. Thus, from the beginning of the 23rd horizontal scanning line, the 22nd horizontal scanning .
line provided by the D/A converter 39, of the video signal is~ fed into input terminal 12. The read address counter 32 counts 4n, 4n+1, 4n+2, ..., 744, 0, 1, 2, 3, i ..., 4n-1. Accordingly, as shown in the "original signal t23H) ~0" in Fig. 5, the data a0 to a9 of one horizontal scanning line is written in line memory 35 and read out of line memory 35 as a4, a5, ..., ag, a0, al, a2, a3.
Thus, a scrambling signal such as shown as ~1 in Fig.
may be obtained. The 24th horizontal scanning line read i during this period ie directly written into the line memory 36. When the 24th horizontal scanning line is to be read from line memory 35 after ac~ambling of the 23rd horizontal scanning line, the read ata~rt address set in i i the read address counter 32 is shifted by a specified I
f number of bits, and changed from n to k. The number of bits by which the shift register is shifted often far scrambling the horizontal scanning line is preliminarily determined at the time of system design.
While the 25th horizontal scanning line is I being fed into the line meiaory 35 through input terminal 12, the data of Line memory 36 correaponding,to the 24th horizontal scanning line is read out. nt this time, the I I
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output of the read address counter 32 counts up from 4k to 4k*1 as shown in fig. 5. This process is ales performed when reading the 23rd horizontal scanning l~.rie ~
from line memory 35. Therefore, line rotation is applied with 4k as the cut point. Thua, video signals Pram scanning line 23H to scanning line 236H of the field starting at t32 in Fig. 4 are scrambled by rotation processing for each horizontal scanning line unit.
Accordingly, a user records and reproduces scrambled video signals, therefore protecting the encoded video I signals from others. By using a detachable memory 26 for storing the key data it is possible to prevent the original picture from being reproduced unless the same .
memory 26 for a duplicate thereof? as the one used at the ! 15 time of recording is inserted into the apparatus. I
The second method ig described below with ' ~
I r reference to Big. 6_ When the 22nd horizontal scanning I
line is supplied to input terminal s2 (corresponding to the 21st horizdrital scanning line output of the D/A
converter 39), the read address counter 32 is preset at ! 744-4n. The read address counter 32 counts up, 744-4ri+i, 744-4n+2, ..., 744-4n+4n, 0, 1, 2, 3, ..., 744-4n-1. Ag a result, ag shown in "original signal 23(h1 X10" in Fig.
6, data a0 to a9 of the 23rd horizontal scanning line o!
23H is written in the line memory 35 and read from line i memory ~35 as a4, a5, ..., a~, a0, ai, a2. a3, as shown on line X11 of Fig, 6.
When the signal corresponding to the 24th ' horizontal scanning line is entered in this reading period it is written into line memory 36 ag shown on line X13 in Fig 6. When the 24th horizontal scanning l~.ne is to be read out, the r~ad start address, set in the read address counter 32, is changed to a value k lrom the value n. Accordingly, the bits will be shifted by 744-4k. Therefore, the output of the read address counter 32 counts up from 744-4k. 744-4k+1, .., as shown in Fig. 6.
ra'ic W I ~'.,~l L:_~ct t nlinl i.eatme~n c; IY estma lu I etlnerstonhnugln I'.1'I
In this way, Ghe 24th Scanning line ie read out as bg, I
b9, b0, ..., b7 from the line memory 36 in a manner similar to the reading of the 23rd horizontal spanning line. The cut paint for rotation applied is 744-4k.
In addition, the CPU 24 seta ox changes the value of the read address generat~.ng circuit 25, for example, once in every field or once in every horizontal scanning line. This procedure ie pxedetermined.
As mentioned before, scramble trigger signaa.
lU (white level 2oH) is generated once after key input of Switch 15. That ie, white level ZUH, which is also used far the trigger of descramble, exists only at the , beginning of the scrambled signal. If the scrambled signal is reproduced from the middle portion of ttte scrambled signal, white level ZUH does not appear, thus making descrambling impossible.
Accordingly, it is desired to generate a . scramble trfgger signal at a specified pariad interval to superimpose the scrambled signal on the video signal, Far example, scramble trigger signal may be generated in every minut~, gimiiarly to the repetitive time interval of the pseudo-random signal. Descramble can start by the scramble trigger signal.
It is important that the H bit output of the PN
x5 generator Z7 are ul~ed as the cut point for scrambling in the line rotation method. It is also important that the cut paint is defined within the maximum of the maximum address, which is 185, of the line memory. Accordingly, j the relationship between n and k for determining the cut point during one horizontal line scanning period of the i video signal is nonlinear, and therefore cannot be predicted. specifically, the read start address sat by the read address counter 32 ie shifted by specified bfts iri every horizontal scanning line, and changed to another I
num9ral k instead of n. The number of bit~ used to shift the shift register in a horizontal line scanning period i .. h: t~v 1_~ ~-. l..~._-'~_ i IW ~,~, IW ~W ~~~r ~;. Inestie. IU I
etlnerstonivauc~ln I-'.lU
A
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is determined preliminarily at the time of system design.
'Thus, even is n if known, k may not be know». Therefore, by ciphering the cut point of rotation, ,secret processing of a video signal may be realized.
Next, the operation of reading the scrambled signal and deacrambled signal according to the first method far a VTR or video disk is described below.
First, the reproduced scrambled video signal is fed into input terminal 12. As a result, a pAriod of the 20th j 10 scanning line is detected by the 20H detector 23 when the video signal is all white level. The detected period is transmitted to CPU 24. CPU 24 Bets the address setting circuit 29 to a deserambling state when the period is detected.
In order to retur» "~1 after scrambling" into "Qr2 after descrambling" as shown in Fig. 5, it is necessary to set the read address counter 32 to an initial state oI (744-4n) according to the output of FN
generator 27 which is n. Accordingly, the address . 20 setting circuit 29 operates 744-4n when descrambling.
The addreBS setting circuit 29 presets 744-4n in the read address counter 32 ae a read address. As a result, as in.
line ~0 shown in Fig. 5, the 23rd horizontal scanning line starts from a0, that is, a0. ...~ a3, a4, ..., a9, aid is sequentially read out to produce data a8 shown in ' line.ø~0, In this period, the rotated 24th horizontal scanning line signal ie recorded in line memory 36 by ' sequentially reading from b0 to bl, .., while using 744-4k ae the initial starting point to read. Accordingly, it is paaBible to deacramble the video signal. During this process, the write address counter 31 is set to write the input directly into line memory 35 or 36 far every horizontal scanning line. Therefore, special processing is not necessary far descrambling. ' When the second method ie uged, it is desirable to stet the read address counter 32 initially to 4n ' , i r,l n; i~a 1 W n l._~_a I I.Lllv ne.tnm- r, f-'ncstms IU f etlrerstonheugln I~'.l:l .a ~) j , , A ~1 - ~, 6 ..
I because n is output by PN generator 27. This is done to return line ~lZ after scrambling into Vila after deacrambling as shown in Fig. 5. The address setting circuit 29 presets 4n into the r~ad address counter 32 when descrambling. As a result, ag shown on line "~12 after descrambling" in Fig. 6, the 23rd horizontal scanning line ie Sequentially read out in a state which is similar to that shown in X10. In this period, since the rotated 24th horizontal scanning line is recorded in line memory 36, it i~r possible to deacramble by reading out from 4K sequentially to produce b0, bl, ... when starting to read the 24th horizontal scanning line.
j The video signal having each horizontal ' scanning line read using this process is selected by selector 38 and provided to D/A converter 39, where it is I converted into an analog video signal. Thus, a deacrambled video signal is produced from the output tezminal 13.
As specifically described above, most of the circuits shown in Figs. 2 and 3 are digital signal groceseing circuits, which can be easily formed on a LSI
chip. The number o~ gates, except switched 18 (~.5 to 17), clock pulse forming circuit 21, A/D converter 22, and D/A converter 39, are approximately 20,000 to 30,000 get~s. These gates may be integrated on one chip. The clock pulps forming circuit 21 and 2UH detecting circuit 23 may be Constructed by altering circuits which have a similar function and which are used in a character broadcast receiver.
' 30 Below, a second exemplary embodiment of the pre~9erit invention is described. Fig. 7 is a block diagram showing the second exemplary embodiment which .
includes units which corre>gpond to those shown in Fig. 2 of the first exemplary embodiment. The corresponding units to the previous Figures are identical and hence, I
I
explanatians of their functions are omitted. In the ~
I
v:.;
Ht 'ft--14-1'-)nA la.'::_'3 f-FiLll~l fiatner fi hrest>a 1L7 Fetherstonhaugh f'.cFJ
second embodiment, as shown in Fig. 7, a nonlinear I
fieedback shift register 41 id used instead of the PN
generator 27. The nonlinear feedback shift register is I
contained in a package unit 42 Cogether with memory 26 for storing the key data. An example of the linear I feedback shift xegister is shown in Fig. e. It is known that there axe at least ten different methods of implementing a 16-stage linear M series wiring system ~a I
shown iri "Latest Spectrum Diffusion Communication System, pp. 88-90, JATECH, 1978" which is incorporated herein by reference. Fig. 8 is a circuit diagram showing two different examples of the linear feedback shift register. ~
I
Herein, the shift register shown in Fig. 8 is Comppsed of a field programmable gate array. The shift registers differ in the number of stages by one stage each. 8ach I package can be set very easily when manufacturing. 8y selecting (1) the number of stages of the shift from 49 types which range from 16 to 64, and t2) the feedback , Ioope, it ig possible to obtain shift register, and I
feedback loop combinations of about 500 types. Further, if the combinations of the 64-bit key data of the memory 26 are taken into account, it would be very difficult to copy package 42 unless package 42 is obtained and disassembled. Thus, the safety against tapping and illegal deciphering is heightened a9 compared to the lirat~exemplary embodiment, The scrambling and descrambling operation of the second exemplary embodiment is the same as the fixat exemplary embodiment.
A third exemplary embodiment is described I below. Fig. 9 shows the principal parts of the third exemplary embodiment. Instead of using switches 15 to 17 as in the first embodiment, a keyboard 51 is used.
Keyboard 51 is connected to GPU 24. The keyboard I
comprises *, )k keys and numeric keys For example, the key is used as an input to start ciphering and and i r v-mn-m -m~ua m:~n ma~n~ i:Rtr,~r- ~ i r-rst ~a nu ePtr~~r-stm,r~augn I f~.ai -, . .-. . . , ., - lg - , deciphering. The # key is used to start Qeciphering and end ciphering at the same time. Keyboard 51 ia, fox example, used for entering a four-digit node number.
The input coda number could, for example, be displayed on j display,unit 52. The input code number would also be provided to PN generator 27 through memory 53. Memory j may be a random access memory (RAM), or an erasable programmable ROM (EPROM). Suppose. far example, the four-digit code number entered from numeric keypad of the keyboard 51 is a Binary Coded hecimal (BCD) code which is I a numeric string of 0 to 1 of 16 bits. The code is used as the key data in this embodiment. This data is used as I the initial value of the PN generator 27. The remaining portions of the third exemplary embodiment operate in a similar manner as the first embodiment, The code number is written once into the memory 53. When memory 53 is a~
RAM, a battery may be used to back up the KAM. It could j be possible td enter the code number every time the ;
apparatus is used even if there is no battery backup.
Alternatively, the RAM may ba detachable and located in , package 59. However, the data of code number would be lost when disconnected from the main bady if the r detachable package did not have a battery backup. ;
In this embodiment, since the code number comprises four digits which are rt~ndam inputs of four-digit numerals, it would be po~riible to decipher the code by using of approximately 10,000 ct~mbiriationa. To I
prevent this, as iri the pecond embodiment, the PN
generator 27 is selected from 500 types of nonlinear feedback shift registers, which help prevent illegal deciphering.
A fourth exemplary embodiment is described while reference to Fig. 10. In this embodiment, the units which are different from those shown fn the first exemplary embodiment are explained. In this embodiment, instead of using switches Z8 t15 to 17), a keyboard 51 to I
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L i . 1~
provided so that a four,-digit code number may be entered in CPU 24 through keyboard 5~.. CPU hold; the four-digit code number as a 16-bit binary signal in, for example, a second memory 55 composed of an EFROM. AS in ttZe first exemplary embodiment, a read address generating circuit 25 ig provided. and key data i» read out from the 64-bit first memory (ROM) 26 through the read address ganer&ting circuix. In this case, the data ie read out in a I
prescribed procedure so that four bite of the memory 26 may be arraigned for one bit of the memory 55. The outputs of the memories 26 and 55 are grovided to an gOR circuit 56. The FOR circuit 56 i9 a logic circuit which , calculates an exclusive OR of the input signal, and which j applies 16-bit data to the PN generator 27. Tn this i embodiment. memories 2&, 55 and BOR circuit 56 are contained in one package 57 which i:~ detachable from casting 11. In thisr case. as compared with the first 1 I
embodiment, the prevention of illegal deciphering may be enhanced. The logic circuit is not limited to an SOR ~
circuit. Circuits such as an RND circuit and a NOR
circuit may be used.
In the foregoing embodiments, video signals for horizontal scanning lines are alternately written into I the line memories 35, 36 directly. The reading start position of each line memory ig read out from a different postition in each line by the addre~5a setting circuit 29 , and read address counter 32 ao as to perform an I encrypting process. However, it ie ales possible to write from the address set in the address setting circuit when writing, and readout continuously from 0 to 744 bits in the read address counter. This is accomplished by exahanying the write address counter 31 and read address ' counter 32. I
By employing the encrypting proceasting apparatus of the invention ae described in the exemplary . embodiments herein, scrambling and descrambling of video w'h-14-1~~~4 1~~2t~ Ehfin I~atner r, f'restia TO I~etherstonhaugh P.23 i i ~~
I signal may be realized by the crams apparatus, The circuit construction is relatively simple, and an expensive video signal encrypting apparatus is realized.
By using a key data memory, for example, a key data K1 of S ug to 64 bits, the probability of realizing the same key is 1 out of 18,490,000,000 billion. Thus, the probability of producing the same key is very small.
Although illustrated and described herein with reference to certain specific embodiments, the present i0 invention is nevertheles~r not intended to be limited to the details shown, Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing frc~n the -;
i spirit of the invention.
alternately to a pair of line memories to read the video signals alternately written in the pair of line memories.
Accordingly, line rotation is performed. The video signal is scrambled by reading the horizontal scanning lines from the line memories by using a different etarting~position.
When desarambling, while the video signals are written alternately into the pair of line memories, a value corre»ponding to the output of r_he PN generator is Subtracted from the maximum address value of the line memory Set by the address setting circuit as an initial value for each horizontal Scanning line. The address saunter is incremented up Go a maximum address from the seC address, and then from a minimum address up to one i before the set address. The address counter also applies i the address signal alternately to the pair of line memories. The address counter also reads the video ' Signal from the line memories to reproduce the original oignal. Thus, 'scrambling and deSCrambling can be performed using the same apparatus.
The present invention further relates to storing the key data in the first memory and for storing ' the adds number in the second memory. The code number is input by an input unit. Then a logic circuit produces from the data in the first and second memories a signal which is set as an initial value in the PN generator.
Thus, a more advancerd encrypting process fs realized.
The present invention further relates to setting the address of the address Setting circuit by subtracting the value of the output of the FN generator ' from the maximum address value of the line memory to set an initial value when scrambling. A value corresponding to the output of the pN generator is Set as the initial ' ~ralue when deacrambling.
i HF'h'-14--19x4 1~~1'i FiiUhi h'ntner & Frestin fD Fetherstonhaugh P.10 ~ ~ ~ ~ ~ ~ i~ ~;a v . ~~ . .. .': 'v -. 7 - ' I
i HRIEF DESCRIPTION OF 'rHE DRAWINGS
Fig. 1 is a perspective view r3howing the appearance of a video signal encrypting apparatus in i accordance with a first exemplary embodiment of the present invention.
Fig. 2 is a block diagram showing the construction of video aigndl encrypting apparatus in accordance with a first exemplary embodiment of. the present invention.
1.0 Fig. 3 is a block diagram showing the construction of portions for acran871ing and descrambling I
of the video signal encrypting apparatus in a first' ' exemplary embodiment of the present invention.
Fig. 4 is a timing chart showing the operation of the first exemplary embodiment of the present invention.
Fig. 5 is a diagram showing an example of the signal configuration change of the horizontal scanning lines according to a first exemplary method of the ~
I present invention far scrambling and descrambling.
Fig. 6 is a diagram showing an example of signal configuration change of the horizontal scanning lines according to a second exemplary method of the preeent~invention for scrambling and deacrambling.
Fig. 7 is a block diagx'am showing the Construction of a video signal encrypting apparatus in t aCCOrdance With a second exemplary embodiment of the present invention.
Figs. 8a and eb are block diagrams showing two I 30 different examples of nonlinear shift registers of the second exemplary embodiment.
I
Fig. 9 is a block.diagram showing a third exemplary embodiment of the present invention.
Hf-'R-14-l9yA 12~1H FRllt°i Re~tner !4 Prestie 10 f=etherstonheugh f'.11 2~.21~~'~~
_A.
Fig. 10 is a block diagram showing a Fourth exemplary embodimenC of tha present invention, Fig. 11 is a block diagram showing tha Construction of a conventional scrambling apparatus.
, i~ESCRIPTI0ri1 OF THfi PREFERRED EL~iEODIMENTB
OF THB INVEPtTTON
Fig. 1 is a perspective outline view of a video signal encrypting apparatus in accordance with an ' exemplary embodiment of the present invention. An input terminal 12 and an output terminal 13 are provided on a j Caging 11. The casing 11 also has a socket for attaching and detaching a read-only memory as-discussed below. The socket is covered by lid 14. The casing 11 also includes operation switches 18 cansisting of encoding start switch 15, decoding r3tart switch 16, and stop gwitCh 17.
Fig. 2 and Fig. 3 are block diagrams showing f tha internal construction of the video signal encrypting apparatus according to the first exemplary embodiment of the present invention. In Fig. 2, an input terminal 12 is connected to a clack pulse forming circuit 21, and A/D
Converter 22, and a 20H detector 23. The clock pulse forming circuit 21 forms a signal 4 fsc by reproducing a Color subcarrier (fsc) using the horizontal sync signal H
and vertical eyrtc signal V of the signal input at input terminal 12. The clock pulse forming circuit also feeds a clock t~ignal arid a gate pulse to other parts of the t apparatus as needed. The 20H detector 23 detects the .
video signal of the 20th horizontal scanning line (hereinafter called 20H), and i~ the brightness level of the 20H i5~ entirely white level, then the 20H detector provides a detection signal to CPU 24.
CYU 24 is used for controlling the operation of the different units which compris~ the video signal encrypting apparatus. Operation switches 18 are i t ~ , ,1 t 'y; '' , v Eu ;~ -1~1 mi'~~ l~:lLi 1 t<UI I tiatner r: I-'r~stia fU f-etherstonhaugh F', 1~
2~~_~~~~
. g _ .
connected to CPU 24. CPU 24 provides a trigger signal to an A/D converter 22 when scrambling is started as well as providing necessary r_ontrol signals to other unite in the video signal encrypting apparatus. Also provided is a nonvolatile memory 26 Which is connected through a read address generating circuit 25 to CPU 24. The nonvolatile memory 26 uses a read-only memory (ROM). The nonvolatile memory 26 is for storing key data which is desirably 64 or more bite, and for storing a read signal which is eventually provided to a PN generator 27.
The PN generator 27 includes a feedback shift register for generating a pseudo-random number sequence pulse signal (PN signal) of 16 bits. A predetermined B !
! bits among the 16 bit outgut ie provided to an MS8 ' inverting Circuit 28.
The output signal.pxovided to PN generator 27 ! i8 used to determine a cut point of the horizontal ~
scanning line. Tf there are 186 cut points in the one horizontal scanning line, the MSB exceeding 186 is 2o inverted. This is accomplished by MSH inverting circuit 28 which inverts the MSB of the output signal of the PN
generator 27. The output signal n, where Osns185, of the MSH inverting circuit is provided to address setting circuit 29. The address setting circuit 29 uses different methods to set an address. The first method is i to calculate and set the initial value o! a reading address for every horizontal scanning line. Accordingly, the initial value is 4n when scrambling. The initial !
! value for descrambling is 744-4n. This assumes that the maximum value of the reading address is 744 or four times the number of cut points of 186. Alternatively, a srecond method sets the initial value equal to ?44-4n when scrambling and 4n when descrambling.
Fig, 3 is a block diagram showing another part of the video signal encrypting apparatus. A clock signal 4 fsc is provided to a write address count~r 31 and a ;, .
, " ,, ~ , : , ;
~b. .
.
;
;~ 4 , , ,.
;
,.
;
: ; . -.
Hl~tl-l~l-1~~=!~7 1<:::1'~ I-I~UU1 I~:~tner & f-'restia fl) I-etherstonhnugh f'.1.3 read addrese~ counter 32 by the clock pulse foritting circuit 21 shown in Fig. 2. Address counters 31, 32 are counters used for counting input clocks. Address counters 31, 32 provide parallel output to selectors 33 and 34, respectively. An A/D converter 22 converts the stignals ~to digital Signals and provides the digital signals to line memories 35, 36. The changeover signals (H) are provided by clock pulse foxining circuit 21 to selector 33 and through inverter 37 to selector 34. Th~
1o changeover signals provided to the selectors 33, 34 are mutually inverted. Tn this process. the write address counter 31 and the read address counter 32 are alternated. Changeover signals which are synchronized with the horizontal sync signal H, are provided to selectors 33 dnd 34. Subsequently, the changeover signals are provided to line memories 35 and 36. Line j memories 35 and 36 are used for storing the video signals i corresponding to one scanning line having 744 dots, in 8 bite. Data corresponding to one horizontal scan line ie written into each line memories 35,36 at an address which is provided by write address counter 31 and selected by selectors 33, 34. The scan lines are alternately read out of the line memorise 35,36 using the read address i from the read a.ddresa counter 32 which is selected by ~electors 33, 34. Selector 38 selects the read signal !
Erom~the line memories 35 and 36. Selector 38 is '.
synchronized with seleetars 33, 34. The output of the j selector 38 is provided to D/A converter 39. D/A
converter 39 cortverte the selected signal into an analog signal. The output of D/A converter 39 is connected to output terminal 13.
. Memory 26, in Fig. 2, is an EPROM formed in pacnage 40 so that it is detachable.
The operation of the exemplary embodiment is described below with reference to the timing chart shown in Fig. 4. As an example, a VTR ie discussed below.
r-a n ,N ml..~-t I~'~~.'FJ 1-istJi~ I«t.i,er c, in est.le IU
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- il First, to ecramt~le the video signal entering the input i terminal 12, the encoding start switch ~.5 is manipulated.
As a result, the encoding instruction (ciphering) is terminated at time tii and a signal is sent to CPU 29.
Then, CPU 24 sends a control signal to A/D converter 22, and generates a scramble trigger pulse. The A/1~
Converter 22 performs A/D conversion in accordance with i the clock pulse of_ the clock pulse forming circuit Z1.
At this time, the brightness level of the whole 20th horizontal scanning line is set to a white level axed is used as a scramble trigger pulse. F'or example, if a scramble trigger signal is generated at time tzl aftex' ' the start video signal t30, then enGOding of the video signal starts at t3z about 2 frames later than t21, at t32. This delay occurs because time is required to prepare the decoding process for the encoded signal.
Zf the video signal is not scrsmriled, the Video .
' signal is converted into an e-bit digital value in the A/b converter 22, and alternately written iota one of the line memories 35 and 36 for every horizontal scanning line. The converted Video signal is alternatively read out from the other line memory. In this Case, 7.ater than one line, the signal is issued to the D/A converter 39 i through the selector 39. In other words, an input signal ~
of one H line is written in the memory, and the written I
one H Nine signal is read out from the memory and outputted to the D/A converter 39 so that the output signal delays one H line from the input signal.
The scrambling of the video signal by line rotation ie explained below, mhe operation is started by adjusting the read address of the line memory to the cut point of the video signal. The cut point is the changeover.positiort for line rotation which is also the changeover signals of the scanning line. The 8-bit output from the PN generator 27 is used as the cut point.
The cut point is defined within the maximum of the t , , ~u N...1,J l'~~_~.J 1~':~~1 I lc~lll ;~a~nrr k FY-est~a ILI hetlverstonhaugh I-'.1~
I
~ 12 -maximum address 186 of the line memory as mentioned ax>ove. The MSS of the out point is inverted by the M9H
I inverting circuit 28 if the cut point exceeds 186. The output of the M5H inverting circuit 28 is an 8-bit signal having an address value of 0 to 185. Tha value is different for every line.
For example, set the value equal to n. In the address getting circuit 29, 4n is preset until the end of the Z2nd horizontal scanning line of the video signal supplied to the input terminal 12 (c:orrespanding to the 21st horizontal scanning lime in the output o~ D/A
converter 39). This is when 4 x n scrambling is performed. Thus, from the beginning of the 23rd horizontal scanning line, the 22nd horizontal scanning .
line provided by the D/A converter 39, of the video signal is~ fed into input terminal 12. The read address counter 32 counts 4n, 4n+1, 4n+2, ..., 744, 0, 1, 2, 3, i ..., 4n-1. Accordingly, as shown in the "original signal t23H) ~0" in Fig. 5, the data a0 to a9 of one horizontal scanning line is written in line memory 35 and read out of line memory 35 as a4, a5, ..., ag, a0, al, a2, a3.
Thus, a scrambling signal such as shown as ~1 in Fig.
may be obtained. The 24th horizontal scanning line read i during this period ie directly written into the line memory 36. When the 24th horizontal scanning line is to be read from line memory 35 after ac~ambling of the 23rd horizontal scanning line, the read ata~rt address set in i i the read address counter 32 is shifted by a specified I
f number of bits, and changed from n to k. The number of bits by which the shift register is shifted often far scrambling the horizontal scanning line is preliminarily determined at the time of system design.
While the 25th horizontal scanning line is I being fed into the line meiaory 35 through input terminal 12, the data of Line memory 36 correaponding,to the 24th horizontal scanning line is read out. nt this time, the I I
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output of the read address counter 32 counts up from 4k to 4k*1 as shown in fig. 5. This process is ales performed when reading the 23rd horizontal scanning l~.rie ~
from line memory 35. Therefore, line rotation is applied with 4k as the cut point. Thua, video signals Pram scanning line 23H to scanning line 236H of the field starting at t32 in Fig. 4 are scrambled by rotation processing for each horizontal scanning line unit.
Accordingly, a user records and reproduces scrambled video signals, therefore protecting the encoded video I signals from others. By using a detachable memory 26 for storing the key data it is possible to prevent the original picture from being reproduced unless the same .
memory 26 for a duplicate thereof? as the one used at the ! 15 time of recording is inserted into the apparatus. I
The second method ig described below with ' ~
I r reference to Big. 6_ When the 22nd horizontal scanning I
line is supplied to input terminal s2 (corresponding to the 21st horizdrital scanning line output of the D/A
converter 39), the read address counter 32 is preset at ! 744-4n. The read address counter 32 counts up, 744-4ri+i, 744-4n+2, ..., 744-4n+4n, 0, 1, 2, 3, ..., 744-4n-1. Ag a result, ag shown in "original signal 23(h1 X10" in Fig.
6, data a0 to a9 of the 23rd horizontal scanning line o!
23H is written in the line memory 35 and read from line i memory ~35 as a4, a5, ..., a~, a0, ai, a2. a3, as shown on line X11 of Fig, 6.
When the signal corresponding to the 24th ' horizontal scanning line is entered in this reading period it is written into line memory 36 ag shown on line X13 in Fig 6. When the 24th horizontal scanning l~.ne is to be read out, the r~ad start address, set in the read address counter 32, is changed to a value k lrom the value n. Accordingly, the bits will be shifted by 744-4k. Therefore, the output of the read address counter 32 counts up from 744-4k. 744-4k+1, .., as shown in Fig. 6.
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In this way, Ghe 24th Scanning line ie read out as bg, I
b9, b0, ..., b7 from the line memory 36 in a manner similar to the reading of the 23rd horizontal spanning line. The cut paint for rotation applied is 744-4k.
In addition, the CPU 24 seta ox changes the value of the read address generat~.ng circuit 25, for example, once in every field or once in every horizontal scanning line. This procedure ie pxedetermined.
As mentioned before, scramble trigger signaa.
lU (white level 2oH) is generated once after key input of Switch 15. That ie, white level ZUH, which is also used far the trigger of descramble, exists only at the , beginning of the scrambled signal. If the scrambled signal is reproduced from the middle portion of ttte scrambled signal, white level ZUH does not appear, thus making descrambling impossible.
Accordingly, it is desired to generate a . scramble trfgger signal at a specified pariad interval to superimpose the scrambled signal on the video signal, Far example, scramble trigger signal may be generated in every minut~, gimiiarly to the repetitive time interval of the pseudo-random signal. Descramble can start by the scramble trigger signal.
It is important that the H bit output of the PN
x5 generator Z7 are ul~ed as the cut point for scrambling in the line rotation method. It is also important that the cut paint is defined within the maximum of the maximum address, which is 185, of the line memory. Accordingly, j the relationship between n and k for determining the cut point during one horizontal line scanning period of the i video signal is nonlinear, and therefore cannot be predicted. specifically, the read start address sat by the read address counter 32 ie shifted by specified bfts iri every horizontal scanning line, and changed to another I
num9ral k instead of n. The number of bit~ used to shift the shift register in a horizontal line scanning period i .. h: t~v 1_~ ~-. l..~._-'~_ i IW ~,~, IW ~W ~~~r ~;. Inestie. IU I
etlnerstonivauc~ln I-'.lU
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2~~:!.~'~y i . ~~ .
is determined preliminarily at the time of system design.
'Thus, even is n if known, k may not be know». Therefore, by ciphering the cut point of rotation, ,secret processing of a video signal may be realized.
Next, the operation of reading the scrambled signal and deacrambled signal according to the first method far a VTR or video disk is described below.
First, the reproduced scrambled video signal is fed into input terminal 12. As a result, a pAriod of the 20th j 10 scanning line is detected by the 20H detector 23 when the video signal is all white level. The detected period is transmitted to CPU 24. CPU 24 Bets the address setting circuit 29 to a deserambling state when the period is detected.
In order to retur» "~1 after scrambling" into "Qr2 after descrambling" as shown in Fig. 5, it is necessary to set the read address counter 32 to an initial state oI (744-4n) according to the output of FN
generator 27 which is n. Accordingly, the address . 20 setting circuit 29 operates 744-4n when descrambling.
The addreBS setting circuit 29 presets 744-4n in the read address counter 32 ae a read address. As a result, as in.
line ~0 shown in Fig. 5, the 23rd horizontal scanning line starts from a0, that is, a0. ...~ a3, a4, ..., a9, aid is sequentially read out to produce data a8 shown in ' line.ø~0, In this period, the rotated 24th horizontal scanning line signal ie recorded in line memory 36 by ' sequentially reading from b0 to bl, .., while using 744-4k ae the initial starting point to read. Accordingly, it is paaBible to deacramble the video signal. During this process, the write address counter 31 is set to write the input directly into line memory 35 or 36 far every horizontal scanning line. Therefore, special processing is not necessary far descrambling. ' When the second method ie uged, it is desirable to stet the read address counter 32 initially to 4n ' , i r,l n; i~a 1 W n l._~_a I I.Lllv ne.tnm- r, f-'ncstms IU f etlrerstonheugln I~'.l:l .a ~) j , , A ~1 - ~, 6 ..
I because n is output by PN generator 27. This is done to return line ~lZ after scrambling into Vila after deacrambling as shown in Fig. 5. The address setting circuit 29 presets 4n into the r~ad address counter 32 when descrambling. As a result, ag shown on line "~12 after descrambling" in Fig. 6, the 23rd horizontal scanning line ie Sequentially read out in a state which is similar to that shown in X10. In this period, since the rotated 24th horizontal scanning line is recorded in line memory 36, it i~r possible to deacramble by reading out from 4K sequentially to produce b0, bl, ... when starting to read the 24th horizontal scanning line.
j The video signal having each horizontal ' scanning line read using this process is selected by selector 38 and provided to D/A converter 39, where it is I converted into an analog video signal. Thus, a deacrambled video signal is produced from the output tezminal 13.
As specifically described above, most of the circuits shown in Figs. 2 and 3 are digital signal groceseing circuits, which can be easily formed on a LSI
chip. The number o~ gates, except switched 18 (~.5 to 17), clock pulse forming circuit 21, A/D converter 22, and D/A converter 39, are approximately 20,000 to 30,000 get~s. These gates may be integrated on one chip. The clock pulps forming circuit 21 and 2UH detecting circuit 23 may be Constructed by altering circuits which have a similar function and which are used in a character broadcast receiver.
' 30 Below, a second exemplary embodiment of the pre~9erit invention is described. Fig. 7 is a block diagram showing the second exemplary embodiment which .
includes units which corre>gpond to those shown in Fig. 2 of the first exemplary embodiment. The corresponding units to the previous Figures are identical and hence, I
I
explanatians of their functions are omitted. In the ~
I
v:.;
Ht 'ft--14-1'-)nA la.'::_'3 f-FiLll~l fiatner fi hrest>a 1L7 Fetherstonhaugh f'.cFJ
second embodiment, as shown in Fig. 7, a nonlinear I
fieedback shift register 41 id used instead of the PN
generator 27. The nonlinear feedback shift register is I
contained in a package unit 42 Cogether with memory 26 for storing the key data. An example of the linear I feedback shift xegister is shown in Fig. e. It is known that there axe at least ten different methods of implementing a 16-stage linear M series wiring system ~a I
shown iri "Latest Spectrum Diffusion Communication System, pp. 88-90, JATECH, 1978" which is incorporated herein by reference. Fig. 8 is a circuit diagram showing two different examples of the linear feedback shift register. ~
I
Herein, the shift register shown in Fig. 8 is Comppsed of a field programmable gate array. The shift registers differ in the number of stages by one stage each. 8ach I package can be set very easily when manufacturing. 8y selecting (1) the number of stages of the shift from 49 types which range from 16 to 64, and t2) the feedback , Ioope, it ig possible to obtain shift register, and I
feedback loop combinations of about 500 types. Further, if the combinations of the 64-bit key data of the memory 26 are taken into account, it would be very difficult to copy package 42 unless package 42 is obtained and disassembled. Thus, the safety against tapping and illegal deciphering is heightened a9 compared to the lirat~exemplary embodiment, The scrambling and descrambling operation of the second exemplary embodiment is the same as the fixat exemplary embodiment.
A third exemplary embodiment is described I below. Fig. 9 shows the principal parts of the third exemplary embodiment. Instead of using switches 15 to 17 as in the first embodiment, a keyboard 51 is used.
Keyboard 51 is connected to GPU 24. The keyboard I
comprises *, )k keys and numeric keys For example, the key is used as an input to start ciphering and and i r v-mn-m -m~ua m:~n ma~n~ i:Rtr,~r- ~ i r-rst ~a nu ePtr~~r-stm,r~augn I f~.ai -, . .-. . . , ., - lg - , deciphering. The # key is used to start Qeciphering and end ciphering at the same time. Keyboard 51 ia, fox example, used for entering a four-digit node number.
The input coda number could, for example, be displayed on j display,unit 52. The input code number would also be provided to PN generator 27 through memory 53. Memory j may be a random access memory (RAM), or an erasable programmable ROM (EPROM). Suppose. far example, the four-digit code number entered from numeric keypad of the keyboard 51 is a Binary Coded hecimal (BCD) code which is I a numeric string of 0 to 1 of 16 bits. The code is used as the key data in this embodiment. This data is used as I the initial value of the PN generator 27. The remaining portions of the third exemplary embodiment operate in a similar manner as the first embodiment, The code number is written once into the memory 53. When memory 53 is a~
RAM, a battery may be used to back up the KAM. It could j be possible td enter the code number every time the ;
apparatus is used even if there is no battery backup.
Alternatively, the RAM may ba detachable and located in , package 59. However, the data of code number would be lost when disconnected from the main bady if the r detachable package did not have a battery backup. ;
In this embodiment, since the code number comprises four digits which are rt~ndam inputs of four-digit numerals, it would be po~riible to decipher the code by using of approximately 10,000 ct~mbiriationa. To I
prevent this, as iri the pecond embodiment, the PN
generator 27 is selected from 500 types of nonlinear feedback shift registers, which help prevent illegal deciphering.
A fourth exemplary embodiment is described while reference to Fig. 10. In this embodiment, the units which are different from those shown fn the first exemplary embodiment are explained. In this embodiment, instead of using switches Z8 t15 to 17), a keyboard 51 to I
ririi lJ-1_i_rd L~~:~S FIi~Ai lar"e,- a I-'rest.rn fll I-etlnrrstonhaugh F'.
L i . 1~
provided so that a four,-digit code number may be entered in CPU 24 through keyboard 5~.. CPU hold; the four-digit code number as a 16-bit binary signal in, for example, a second memory 55 composed of an EFROM. AS in ttZe first exemplary embodiment, a read address generating circuit 25 ig provided. and key data i» read out from the 64-bit first memory (ROM) 26 through the read address ganer&ting circuix. In this case, the data ie read out in a I
prescribed procedure so that four bite of the memory 26 may be arraigned for one bit of the memory 55. The outputs of the memories 26 and 55 are grovided to an gOR circuit 56. The FOR circuit 56 i9 a logic circuit which , calculates an exclusive OR of the input signal, and which j applies 16-bit data to the PN generator 27. Tn this i embodiment. memories 2&, 55 and BOR circuit 56 are contained in one package 57 which i:~ detachable from casting 11. In thisr case. as compared with the first 1 I
embodiment, the prevention of illegal deciphering may be enhanced. The logic circuit is not limited to an SOR ~
circuit. Circuits such as an RND circuit and a NOR
circuit may be used.
In the foregoing embodiments, video signals for horizontal scanning lines are alternately written into I the line memories 35, 36 directly. The reading start position of each line memory ig read out from a different postition in each line by the addre~5a setting circuit 29 , and read address counter 32 ao as to perform an I encrypting process. However, it ie ales possible to write from the address set in the address setting circuit when writing, and readout continuously from 0 to 744 bits in the read address counter. This is accomplished by exahanying the write address counter 31 and read address ' counter 32. I
By employing the encrypting proceasting apparatus of the invention ae described in the exemplary . embodiments herein, scrambling and descrambling of video w'h-14-1~~~4 1~~2t~ Ehfin I~atner r, f'restia TO I~etherstonhaugh P.23 i i ~~
I signal may be realized by the crams apparatus, The circuit construction is relatively simple, and an expensive video signal encrypting apparatus is realized.
By using a key data memory, for example, a key data K1 of S ug to 64 bits, the probability of realizing the same key is 1 out of 18,490,000,000 billion. Thus, the probability of producing the same key is very small.
Although illustrated and described herein with reference to certain specific embodiments, the present i0 invention is nevertheles~r not intended to be limited to the details shown, Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing frc~n the -;
i spirit of the invention.
Claims (22)
1. A video signal encrypting apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising:
memory means for storing key data, plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means, set to an initial value correspondingly to an output of the PN generator for scrambling, and, set to a further initial value correspondingly to a maximum address value of the plurality line memories minus a further output of the PN
generator far descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value. and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
memory means for storing key data, plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means, set to an initial value correspondingly to an output of the PN generator for scrambling, and, set to a further initial value correspondingly to a maximum address value of the plurality line memories minus a further output of the PN
generator far descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value. and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
2. A video signal encrypting apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising:
memory means for storing key data for encrypting, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means for generating a respective pseudo-random pulse signal for each one of said plurality horizontal scanning lines, address setting means, set to an initial value correspondingly to a maximum address value of the plurality of line memories minus an output of the PN
generator for scrambling, and set to further initial value correspondingly to a further output of the PN
generator for descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each o~
said plurality of line memories for each horizontal scanning line,
memory means for storing key data for encrypting, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means for generating a respective pseudo-random pulse signal for each one of said plurality horizontal scanning lines, address setting means, set to an initial value correspondingly to a maximum address value of the plurality of line memories minus an output of the PN
generator for scrambling, and set to further initial value correspondingly to a further output of the PN
generator for descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each o~
said plurality of line memories for each horizontal scanning line,
3. A video signal encrypting apparatus according to claim 1, wherein the memory means includes a nonvolatile memory.
4. A video signal encrypting apparatus according to claim 2, wherein the memory means includes a nonvolatile memory.
5. A video signal encrypting apparatus according to claim 1, wherein the memory means includes a reloadable memory, and said memory means further includes input means for entering key data.
6. A video signal encrypting apparatus according to claim 2, wherein the memory means includes a reloadable memory, and said memory means further includes input means for entering key data.
7. A video signal encrypting apparatus according to claim 1, wherein the memory means includes a detachable memory device.
8. A video signal encrypting apparatus according to claim 2, wherein the memory means includes a detachable memory device.
9. A video signal encrypting apparatus according to claim 3, wherein the memory means includes a detachable memory device.
i0. A video signal encrypting apparatus according to claim 4, wherein the memory means includes a detachable memory device.
11. A video signal encrypting apparatus according to claim 1, wherein the PN generator includes one of a linear feedback shift register and a nonlinear feedback shift register.
12. A video signal encrypting apparatus according to claim 2, wherein the PN generator includes one of a linear feedback shift register and a nonlinear feedback shift register.
13. A video signal encrypting apparatus according to claim 12, wherein said one of said linear feedback shift register and said nonlinear feedback shift register is a field programmable register.
14. A video signal encrypting apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising:
a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit set to an initial value correspondingly to an output of the PN generator when scrambling, and sat to a further initial value correspondingly to a maximum address value of the plurality line memories minus a further output of the PN
generator when descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit set to an initial value correspondingly to an output of the PN generator when scrambling, and sat to a further initial value correspondingly to a maximum address value of the plurality line memories minus a further output of the PN
generator when descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
15. A video Signal encrypting apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising:
a first memory for storing key data, a second memory for storing a reloadable wade number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN
generator when scrambling, and set to a further initial value correspondingly to a further output of the PN
generator when descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
a first memory for storing key data, a second memory for storing a reloadable wade number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN
generator when scrambling, and set to a further initial value correspondingly to a further output of the PN
generator when descrambling, and an address counter for generating a plurality of address values consecutively to one of said initial value and said further initial value, and for applying said plurality of address values respectively to each of said plurality of line memories for each horizontal scanning line.
16. A video signal encrypting apparatus according to Claim 14, wherein the first memory and the second memory are included in a single detachable package.
17. A video signal encrypting apparatus according to claim 15, wherein the first memory and the second memory are included in a single detachable package.
18. A video signal encrypting apparatus according to claim 14, wherein the PN generator includes one of linear feedback shift register and nonlinear feedback shift register.
19. A video signal encrypting apparatus according to claims 15, wherein the PN generator includes one of linear feedback shift register and nonlinear feedback shift register.
20. A video signal encrypting apparatus according to claim 19, wherein said one of said linear feedback shift register and said nonlinear feedback shift register is a field programmable register.
21. A video signal encrypting apparatus according to any one of claims 1 to 20 further comprising:
scramble trigger writing means for writing a scramble trigger signal in a horizontal scanning period corresponding to a selected one of said plurality of horizontal scanning lines when scrambling, and control means for setting said initial value in the address setting circuit when the scramble trigger signal is detected during descrambling.
scramble trigger writing means for writing a scramble trigger signal in a horizontal scanning period corresponding to a selected one of said plurality of horizontal scanning lines when scrambling, and control means for setting said initial value in the address setting circuit when the scramble trigger signal is detected during descrambling.
22. A video signal encrypting apparatus of any one of claims 1 to 20, wherein the address counter is a read address counter which generates a read address consecutively from the address set by the address setting circuit, and which applies respective read address signals to the plurality of line memories corresponding to said plurality of horizontal scanning lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5113804A JPH06133314A (en) | 1992-09-03 | 1993-04-15 | Video signal secreting processor |
| JP5-113804 | 1993-04-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2121446A1 CA2121446A1 (en) | 1994-10-16 |
| CA2121446C true CA2121446C (en) | 2001-07-10 |
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ID=14621491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002121446A Expired - Fee Related CA2121446C (en) | 1993-04-15 | 1994-04-15 | Video signal encrypting apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5488658A (en) |
| EP (1) | EP0620690B1 (en) |
| AU (1) | AU676265B2 (en) |
| CA (1) | CA2121446C (en) |
| DE (1) | DE69416183T2 (en) |
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|---|---|---|---|---|
| US5903704A (en) * | 1994-08-26 | 1999-05-11 | Hitachi, Ltd. | Apparatus for selectively recording and reproducing received analog and digital signals |
| JP3294739B2 (en) * | 1995-03-30 | 2002-06-24 | 三洋電機株式会社 | Method for scrambling or descrambling FM multiplex broadcasting |
| CA2248909A1 (en) | 1996-03-15 | 1997-09-25 | Zapa Digital Arts Ltd. | System for producing an animation sequence according to character behaviour characteristics |
| JPH1056361A (en) * | 1996-08-07 | 1998-02-24 | Matsushita Electric Ind Co Ltd | Dummy noise generator |
| JP3639424B2 (en) * | 1998-01-30 | 2005-04-20 | 三洋電機株式会社 | Address generation circuit |
| WO2008010689A1 (en) * | 2006-07-20 | 2008-01-24 | Electronics And Telecommunications Research Institute | Method for generating the counter block value |
| US20080152142A1 (en) * | 2006-12-20 | 2008-06-26 | Mark Buer | Memory scrambler unit (msu) |
| JP4528846B2 (en) * | 2008-04-21 | 2010-08-25 | シャープ株式会社 | Image compression method, image compression apparatus, image processing apparatus, image forming apparatus, computer program, and recording medium |
| US8584167B2 (en) | 2011-05-31 | 2013-11-12 | Echostar Technologies L.L.C. | Electronic programming guides combining stored content information and content provider schedule information |
| US9185331B2 (en) | 2011-08-23 | 2015-11-10 | Echostar Technologies L.L.C. | Storing multiple instances of content |
| US9357159B2 (en) | 2011-08-23 | 2016-05-31 | Echostar Technologies L.L.C. | Grouping and presenting content |
| US8763027B2 (en) | 2011-08-23 | 2014-06-24 | Echostar Technologies L.L.C. | Recording additional channels of a shared multi-channel transmitter |
| US8660412B2 (en) | 2011-08-23 | 2014-02-25 | Echostar Technologies L.L.C. | System and method for dynamically adjusting recording parameters |
| US8959566B2 (en) | 2011-08-23 | 2015-02-17 | Echostar Technologies L.L.C. | Storing and reading multiplexed content |
| US8437622B2 (en) | 2011-08-23 | 2013-05-07 | Echostar Technologies L.L.C. | Altering presentation of received content based on use of closed captioning elements as reference locations |
| US8627349B2 (en) | 2011-08-23 | 2014-01-07 | Echostar Technologies L.L.C. | User interface |
| US8850476B2 (en) | 2011-08-23 | 2014-09-30 | Echostar Technologies L.L.C. | Backwards guide |
| US8447170B2 (en) | 2011-08-23 | 2013-05-21 | Echostar Technologies L.L.C. | Automatically recording supplemental content |
| US9621946B2 (en) | 2011-08-23 | 2017-04-11 | Echostar Technologies L.L.C. | Frequency content sort |
| US9489981B2 (en) | 2012-03-15 | 2016-11-08 | Echostar Technologies L.L.C. | Successive initialization of television channel recording |
| US8959544B2 (en) | 2012-03-15 | 2015-02-17 | Echostar Technologies L.L.C. | Descrambling of multiple television channels |
| US8819722B2 (en) | 2012-03-15 | 2014-08-26 | Echostar Technologies L.L.C. | Smartcard encryption cycling |
| US8989562B2 (en) | 2012-03-15 | 2015-03-24 | Echostar Technologies L.L.C. | Facilitating concurrent recording of multiple television channels |
| CN104685543B (en) * | 2012-09-27 | 2017-04-12 | 三菱电机株式会社 | Graphics rendering device |
| US8793724B2 (en) | 2012-11-08 | 2014-07-29 | Eldon Technology Limited | Image domain compliance |
| US9628838B2 (en) | 2013-10-01 | 2017-04-18 | Echostar Technologies L.L.C. | Satellite-based content targeting |
| US9756378B2 (en) | 2015-01-07 | 2017-09-05 | Echostar Technologies L.L.C. | Single file PVR per service ID |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4547802A (en) * | 1983-04-29 | 1985-10-15 | Westinghouse Electric Corp. | TV Scrambler/descrambler using serial memories |
| FR2642597A1 (en) * | 1989-01-27 | 1990-08-03 | Labo Electronique Physique | TRANSMISSION STAGE FOR EXTENDED DEFINITION TELEVISION IMAGE TRANSMISSION SYSTEM, TRANSMISSION SYSTEM INCLUDING SUCH STAGE, AND RECEPTION STAGE FOR SUCH A SYSTEM |
| DE3927338A1 (en) * | 1989-08-18 | 1991-02-21 | Ind Technik Ips Gmbh | TV image fading by image signal coding - converts image signals into digital image point data, stored in lines at addresses |
| DE69125756T2 (en) * | 1990-06-29 | 1997-12-18 | Digital Equipment Corp | Method and device for decrypting an information package with a modifiable format |
| EP0560345B1 (en) * | 1992-03-13 | 1997-06-18 | Matsushita Electric Industrial Co., Ltd. | A scramble codec and a television receiver incorporating the same |
| US5455860A (en) * | 1992-04-17 | 1995-10-03 | Matsushita Electric Industrial Co., Ltd. | Scramble codec |
-
1994
- 1994-04-13 EP EP94302618A patent/EP0620690B1/en not_active Expired - Lifetime
- 1994-04-13 DE DE69416183T patent/DE69416183T2/en not_active Expired - Fee Related
- 1994-04-15 US US08/228,220 patent/US5488658A/en not_active Expired - Lifetime
- 1994-04-15 AU AU59455/94A patent/AU676265B2/en not_active Ceased
- 1994-04-15 CA CA002121446A patent/CA2121446C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| EP0620690A1 (en) | 1994-10-19 |
| AU676265B2 (en) | 1997-03-06 |
| CA2121446A1 (en) | 1994-10-16 |
| DE69416183T2 (en) | 1999-06-10 |
| US5488658A (en) | 1996-01-30 |
| AU5945594A (en) | 1994-10-20 |
| DE69416183D1 (en) | 1999-03-11 |
| EP0620690B1 (en) | 1999-01-27 |
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