CA2669690A1 - Hybrid solid-state memory system having volatile and non-volatile memory - Google Patents

Hybrid solid-state memory system having volatile and non-volatile memory Download PDF

Info

Publication number
CA2669690A1
CA2669690A1 CA002669690A CA2669690A CA2669690A1 CA 2669690 A1 CA2669690 A1 CA 2669690A1 CA 002669690 A CA002669690 A CA 002669690A CA 2669690 A CA2669690 A CA 2669690A CA 2669690 A1 CA2669690 A1 CA 2669690A1
Authority
CA
Canada
Prior art keywords
memory
volatile
solid
volatile memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002669690A
Other languages
French (fr)
Inventor
Jin-Ki Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Incorporated
Jin-Ki Kim
Conversant Intellectual Property Management Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Incorporated, Jin-Ki Kim, Conversant Intellectual Property Management Inc. filed Critical Mosaid Technologies Incorporated
Publication of CA2669690A1 publication Critical patent/CA2669690A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

Description

HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE
MEMORY
[0001] The present invention relates generally to a solid-state memory system, and specifically to a hybrid solid-state memory system that comprises both volatile and non-volatile memory.

BACKGROUND
[0002] The most common mass storage system in computer systems today is a hard disk drive (HDD) that uses one or more rotating disks and records data magnetically.
Although HDDs are capable of storing a large amount of information, they have disadvantages compared to solid-state memories. Specifically, HDDs have a slower read/write speed, higher power consumption, larger system size, and lower tolerance to mechanical shock.
[0003] Solid-state memories are data storage devices that use memory chips to store data. Non-volatile solid-state memories, such as flash memory for example, are becoming increasingly popular as their memory density increases. It is envisioned that eventually solid-state memories will replace HDDs in mobile computers, such as notebook computers, because of their advantages, as discussed above.
[0004] However, there are known problems associated with the use of flash memory. One known problem is flash memory cells have a limited number of rewrite cycles.
For example, typical maximum number of rewrite cycles range between 100,000 and 1,000,000 cycles.
Further, in order to meet memory density and low cost requirements, multilevel cell (MLC) technology will likely be employed. However, MLC typically reduces the maximum number of rewrite cycles per flash memory cell by two orders of magnitude, for example from 1,000,000 cycles to 10,000 cycles.
[0005] Another issue with flash memory is a size mismatch between read/program and erase operations. Specifically, in flash memory, read and program operations are executed on a page basis, while erase operations are executed on a block basis. Therefore the minimum erasable size is typically 16 to 64 times larger than the read/program size. Since memory cells in flash memory devices must be erased before being programmed with new data, an entire block has to be erased in order to write a new page. This further exacerbates the problem of having a limited number of rewrite cycles.
[0006] Accordingly, a number of solutions have been proposed to address these issues. Many of these attempted solutions are described in U.S. Patent No. 6,763,424 issued to Conley.
However, while these solutions provide certain improvements, they still require a significant number of pages to be rewritten.
[0007] Accordingly it can be seen that there is a need for a memory system that further reduces the number of read/write operations performed by the flash memory, thereby extending a life expectancy of the memory system.

SUMMARY
[0008] It is an object of the present invention to obviate or mitigate at least some of the above-mentioned disadvantages. Accordingly, a solid-state memory storage system is provided that combines both volatile memories, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), and non-volatile memories, such as flash memory.
The memories are combined in a manner that takes advantage of the benefits of each type of memory to improve the overall system performance and improve the life expectancy of the storage device.
[0009] In accordance with an aspect of the present invention, there is provided a solid-state memory system comprising: a volatile solid state memory; a non-volatile solid-state memory; a memory controller configured to store write data in the volatile memory, the memory controller being further configured to transfer data from the volatile memory to the non-volatile memory in response to a data transfer request.
[0010] In accordance with a further aspect of the present invention, there is provided a method for storing data in a solid-state memory system comprising a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller, the method comprising the steps of receiving a command to store write data; storing the write data in the volatile memory in response; and transferring data from the volatile memory to the non-volatile memory in response to a data transfer request.

BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Embodiments of the present invention will now be described with reference to the following drawings in which:

Figure 1 is a block diagram illustrating a solid-state memory system;
Figure 2a is a block diagram illustrating a memory cell array structure having a plurality of blocks;
Figure 2b is a block diagram illustrating a block structure having a plurality of pages;
Figure 2c is a block diagram illustrating a page structure;
Figures 3a and 3b are memory space maps of a volatile and non-volatile memory, respectively;
Figures 4 and 5 are flow diagrams illustrating a process implemented by the solid-state memory system;
Figure 6 is a block diagram of a solid-state memory system using a common bus to communicate with a plurality of memory devices;
Figure 7 is a block diagram of a solid-state memory system using a plurality of common buses to communicate with a plurality of memory devices;
Figure 8 is a block diagram of a solid-state memory system using a plurality of common buses to communicate with a plurality of memory devices, each bus communicating with one type of memory device;
Figure 9 is a block diagram of a solid-state memory system using a daisy chain structure to communicate with a plurality of memory devices;
Figure 10 is a block diagram of a solid-state memory system using a plurality of chains to communicate with a plurality of memory devices; and Figure 11 is a block diagram of a solid-state memory system using a plurality of chains to communicate with a plurality of memory devices, each chain communicating with one type of memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] For convenience, like numerals in the specification refer to like structures in the drawings. Referring to Figure 1 a block diagram of solid-state memory system is illustrated generally by numeral 100. The solid-state memory system 100 comprises a memory controller 102 and a solid-state memory 104. External devices 106 communicate with the solid-state memory 104 via the memory controller 102.
[0013] In the present embodiment, the memory controller 102 includes a virtual mapping system 108 (or simply mapping system 108). The mapping system 108 is used to map a logical address associated with the request to a physical address associated with the solid-state memory 104.
[0014] The solid-state memory 104 includes volatile memory 104a and non-volatile memory 104b. As will be appreciated, both the volatile memory 104a and the non-volatile memory 104b can include one or more memory devices.
[0015] In the present embodiment, the volatile memory 104a comprises DRAM
memory and the non-volatile memory 104b comprises NAND flash memory. However it will be appreciated that other types of both volatile and non-volatile memory 104a and 104b may be used.
[0016] Since the solid-state memory system 100 includes volatile memory, it may also incorporate an internal battery (not shown) to retain data. If power to the solid-state memory system 100 is lost, the battery would maintain sufficient power to copy data from the volatile memory 104a to the non-volatile memory 104b. More commonly, however, battery power will be provided as part of an external system.
[0017] Referring to Figure 2a, a block diagram illustrating a memory cell array structure is shown generally by numeral 200. The cell array 200 comprises n erasable blocks 202, labelled from Block 0 to Block n-1.
[0018] Referring to Figure 2b, a block diagram illustrating a cell array block 202 in more detail is shown. Each block 202 comprises m programmable pages 252, labelled from Page 0 to Page m-1.
[0019] Referring to Figure 2c, a block diagram illustrating a programmable page 252 in more detail is shown. Each page 252 comprises a data field 262 for storing data and a spare field 264 for storing additional information related to the data, such as error management functions. The data field comprisesj bytes (B) and the spare field 264 comprises k bytes (B).
[0020] Accordingly, it can be seen that each page 252 comprises (j + k) bytes (B). Each block 202 comprises m pages 252 and, thus, one block 202 is (j + k) * m bytes (B).
Further, a total memory size for the cell array 200 of n blocks 202 is (j + k) * m n bytes (B).
For convenience, the following abbreviations are used: 1B = 8 bits; 1K = 1024; 1M = 1024K; and 1G = 1024M.
[0021] Referring to Figures 3a and 3b, block diagrams illustrating volatile 104a and non-volatile 104b memory, respectively, in accordance with the present embodiment are shown. The following description provides exemplary sizes for pages, blocks and cells.
However, it will be appreciated that these size can vary greatly for different implementations and will continue to change as technology advances. Further, it will be appreciated that volatile memory 104a, such as DRAM for example, does not necessarily have a block and page structure.
Accordingly, any data temporarily stored in the volatile memory 104a may also include a corresponding block address and/or a page address. The block address and/or page address is referred to when the data is transferred into the non-volatile memory 104b. Therefore as long as the data in the volatile memory 104a is block and page addressable, the volatile memory 104a itself need not be physically mapped onto the non-volatile memory 104b.
[0022] In the present embodiment, the size of the page 252 is the same for both the volatile 104a and non-volatile 104b memory. Specifically, the page 252 comprises 2112B;
2048B for the data field 262; and 64B for spare field 264.
[0023] Further, the size of the block 202 is the same for both the volatile 104a and non-volatile 104b memory. Specifically, since each block 202 includes 64 pages 252, each block 202 comprises 132KB; 128KB for the data field 262; and 4KB for spare field 264.
[0024] In accordance with the present embodiment, the number of blocks 202 in the volatile memory 104a is fewer than the number of blocks 202 in the non-volatile memory 104b.
Specifically, the volatile memory 104a comprises 8K blocks and the non-volatile memory 104b comprises 256K blocks. Therefore, the volatile memory 104a comprises 1,056MB;
1GB for the data field 262; and 32MB for the spare field 264. The non-volatile memory 104b comprises 33GB; 32GB for the data field 262; and 1GB for spare field 264.
[0025] For clarity, general operation of NAND flash devices is described as follows. Read and program operations are executed on a page basis while erase operations are executed on a block basis.
[0026] For a read operation, a READ command followed by a logical address is sent to the solid-state memory system 100. The mapping system determines a physical address corresponding with the logical address. Data corresponding to the physical address is read from the volatile memory 104a, or non-volatile memory 104b if the physical address does not exist in the volatile memory 104a.
[0027] In the case where data is read from the non-volatile memory 104b, the read data may be programmed in the volatile memory 104a. Details thereon are described with reference to Figures 4 and 5.
[0028] For a program operation, a PROGRAM command followed by an address and input data is issued to the solid-state memory system 100. The data is initially programmed in the volatile memory 104a. If the address referenced by the PROGRAM command is already programmed in the volatile memory 104a, the data is overwritten at that address. If the address referenced by the PROGRAM command is not yet programmed in the volatile memory 104a, space for the address is established in the volatile memory 104a.
[0029] For a block erase operation, a BLOCK ERASE command followed by block addresses is issued to the solid-state memory system 100. The 128K bytes of data in a block are erased in less than a predefined block erase time tBERS. Referring to Figure 4, a flow diagram illustrating a process implemented by the solid-state memory system 100 in accordance with one embodiment is shown generally by numeral 400. In step 402, the memory controller 102 receives an operation request. The operation request typically includes a command. Types of commands include, for example, read, program and erase. Depending on the command, other information may be included as part of the operation request. For example, both a read and a write command will include a logical address. Further, a write command will also include data to be written.
[0030] At step 404, the memory controller 102 processes the request and the requested operation is determined. In step 406 it is determined whether or not the request includes an operation that involves a transfer of data from the volatile memory 104a to the non-volatile memory 104b. A
number of situations exist for which the data would have to be transferred.
For example, system restart, system power down or memory maintenance operations may create a data transfer request. Therefore, if a request to transfer data is received at the memory controller 102, the process continues at step 408. Otherwise, the process continues at step 414.
[0031] At step 408, the data stored in the volatile memory 104a is transferred to the non-volatile memory 104b and the mapping system 108 is updated accordingly. The transfer can be done in accordance with any state-of-the-art method for updating data in a non-volatile memory 104b.
At step 409, the mapping system 108 is updated with the physical address of the transferred data, which is in the non-volatile memory 104b. At step 410 it is determined whether or not the transfer of data was in response to a power down operation. If the data transfer was performed in response to a power down operation, then at step 412 the solid-state memory system 100 powers down. If the data transfer was performed in response to another operation, the process returns to step 402.
[0032] At step 414, it is determined whether the requested operation is a read operation or a write operation. If it is determined that the operation is a read operation the process continues at step 416. Otherwise, the process continues at step 420.
[0033] At step 416, the memory controller 102 translates the received logical address of the data to be read into a physical address using the mapping system 108. At step 418, the data is read from the non-volatile memory 104b as is standard in the art and the process returns to step 402.
[0034] At step 420 the memory controller 102 translates the received logical address of the data to be written into a physical address using the mapping system 108. In step 422, mapping system 108 determines whether the physical address matches a non-volatile memory address or a volatile memory address.
[0035] If the physical address corresponds to a volatile memory address, the process continues at step 424. At step 424, the data accompanying the write operation is written to the physical address in the volatile memory, overwriting the pre-existing data. Writing data to a volatile memory 104a, such as DRAM, does not require that the memory be erased prior to the write operation. Further, volatile memory 104a does not suffer from the rewrite cycle limitation associated with non-volatile memory 104b, such as flash memory. Once the data is written to the volatile memory 104a, the process continues to step 434. At step 434, the mapping system 108 is updated with the physical address of the write data and the process returns to step 402 in order to execute a next operation, if one is pending.
[0036] If the physical address corresponds to a non-volatile memory address, the process continues at step 426. At step 426, the memory controller determines the amount of space available in the volatile memory 104a. At step 428, it is determined whether or not the amount of available space is greater than an amount of space required for the data to be written. If there is insufficient space, the process continues at step 430. Otherwise, the process continues at step 432.
[0037] At step 430, at least a portion of data stored in the volatile memory 104a is transferred to the non-volatile memory 104b. In the present embodiment, a predefined number of blocks are transferred from the volatile memory 104a to the non-volatile memory 104b.
Further, in the present embodiment, the blocks selected for transfer are the most "stale".
That is, the blocks that are transferred have had not been accessed for the longest period of time. As described with reference to step 408, the pages can be written to the non-volatile memory 104b in accordance with one of a number of state-of-the-art methods. At step 431, the mapping system 108 is updated to reflect the change in physical address for the transferred data and the process returns to step 428.
[0038] At step 432, the data is written to the volatile memory 104a. The method used to write the data to the volatile memory 104a can be any state-of-the-art method, as will be appreciated by a person of ordinary skill in the art. At step 434, the mapping system 108 is updated with the physical address of the write data and the process returns to step 402 in order to execute a next operation, if one is pending.
[0039] Accordingly, it can be seen that the present embodiment uses a combination of both volatile and non-volatile memories to improve overall performance of a solid-state memory system. Specifically, relatively inexpensive non-volatile memory is used to provide persistent storage of data. Volatile memory is used to improve limitations related with the use of non-volatile memory. For example, the use of volatile memory as described above improves overall time-performance of the solid-state memory system. Further, since fewer write operations are performed to the non-volatile memory, the effective life expectancy of the non-volatile memory is improved.

[0040] Further, in the present embodiment, a read operation is implemented by simply reading the data from the non-volatile memory 104b and outputting it to a requesting device or processor.
However, it will be appreciated that in some instances it may be preferable to load the read data into the volatile memory 104a as well.
[0041] Accordingly, referring to Figure 5, a flow diagram illustrating a process implemented by the solid-state memory system 100 in accordance with an alternate embodiment is shown generally by numeral 500. In the present embodiment, data transfer and write operations are handled in the same way as described with reference to Figure 4. Accordingly, Figure 5 illustrates an alternate process for a read operation and the description begins at step 414.
[0042] At step 414, it is determined that the operation request is for a read operation and the process continues at step 502. At step 502 the memory controller 102 translates the received logical address of the data to be read into a physical address using the mapping system 108. In step 504, the mapping system 108 determines whether the physical address matches a non-volatile memory address or a volatile memory address.
[0043] If the physical address corresponds to a volatile memory address, the process continues at step 506. At step 506, the data reads the physical address in the volatile memory associated with the read operation. It will be appreciated that the data can be read using state-of-the art methods.
Once the data is read from the volatile memory 104a, the process returns to step 402.
[0044] If the physical address corresponds to a non-volatile memory address, the process continues at step 508. At step 508, the requested data is read from the physical address in the non-volatile memory 104b associated with the read operation. As described at step 506, the data can be read using state-of-the art methods. At step 510, the data read from the non-volatile memory 104b is made available to the requesting device 106.
[0045] At step 552, the memory controller 102 determines the amount of space available in the volatile memory 104a and whether or not the amount of available space is greater than an amount of space required for the data to be written to the volatile memory 104a. If there is insufficient space, the process continues at step 554. Otherwise, the process continues at step 512.
[0046] At step 554, at least a portion of data stored in the volatile memory 104a is transferred to the non-volatile memory 104b. In the present embodiment, a predefined number of blocks are transferred from the volatile memory 104a to the non-volatile memory 104b.
Further, in the present embodiment, the blocks selected for transfer are the most "stale". As described with reference to steps 408 and 430, the pages can be written to the non-volatile memory 104b in accordance with one of a number of state-of-the-art methods. In step 555, the mapping system 108 is updated to reflect the change in physical address for the transferred data and the process returns to step 552. At step 512, the data read from the non-volatile memory 104b is written to the volatile memory 104a. At step 514, the mapping system 108 is updated with the new physical address for the read data and the process returns to step 402 in order to execute a next operation, if one is pending.
[0047] Accordingly, it can be seen that in the embodiments described with reference to Figures 4 and 5, data is loaded into the volatile memory 104a for read operations as well as write operation. This may improve the solid-state memory system performance if the same data is accessed before it is transferred back to the non-volatile memory due to the improved access speed of volatile memory.
[0048] In the previous embodiment, data may be written to the volatile memory 104a in response to a read or a write operation. In a further embodiment, a tag is provided for each page of data written to the volatile memory 104a to identify the data as being the result of either a read operation or a write operation. The tag may be maintained in either the spare field 264 of the page 252 or in the mapping system 108.
[0049] The tag can then be used for other steps in the process. For example, when data is transferred from the volatile memory 104a to the non-volatile memory 104b, only pages with a write tag are transferred. Pages with a read tag may be able to be deleted from the volatile memory 104a since the data is still stored at an associated non-volatile memory address.
Accordingly, the mapping system 108 would need to be updated.
[0050] Further, the previous embodiment describes freeing space from the volatile memory 104a in accordance with the most stale data. However, the process of determining which blocks to erase may also contemplate whether or not a page includes a read or write tag.
For example, in some cases it may be preferable to delete newer pages comprising read tags than an older page comprising write tags. It will be appreciated that different algorithms can be implemented on a using one or more of these or other considerations.
[0051] Referring to Figure 6, a block diagram of a solid-state memory system in accordance with an alternate embodiment is illustrated by numeral 600. The solid-state memory system 600 comprises a memory controller 102 and a solid-state memory 104. In the present embodiment, the solid-state memory 104 comprises a plurality of volatile memory devices 104a and a plurality of non-volatile memory devices 104b. The volatile memory devices 104a and the non-volatile memory devices 104b are coupled with the memory controller 104 via a common bus 602.
[0052] For exemplary purposes only, the volatile memory devices 104a are DRAM
devices and the non-volatile memory devices 104b are flash memory devices. Further, although the diagram illustrates two DRAM devices and four flash memory devices, the number of devices may vary depending on the implementation.
[0053] In order to access one of the solid-state memory devices 104a or 104b, the common bus 602 includes a device enable signal for enabling only one of the plurality of volatile memory devices 104a or one of a plurality of the non-volatile memory devices 104b at a time. Methods of using an enable signal for activating one of a plurality of memory devices on a common bus are well known in the art and need not be described in detail.
[0054] Referring to Figure 7, a block diagram of a solid-state memory system in accordance with an yet an alternate embodiment is illustrated by numeral 700. The solid-state memory system 700 comprises a memory controller 102 and a solid-state memory 104. In the present embodiment, the solid-state memory 104 comprises a plurality of volatile memory devices 104a and a plurality of non-volatile memory devices 104b. The volatile memory devices 104a and the non-volatile memory devices 104b are coupled with the memory controller 104 via a common bus 602. However, unlike the previous embodiment, the memory controller 104 controls a plurality of buses, referred as channels.
[0055] In order to access one of the solid-state memory devices 104a or 104b, each channel 602 includes a device enable signal for enabling only one of the memory devices at a time. If the requested operation is a read operation, the enabled memory device outputs the data onto the channel 602. If the requested operation is a write operation, the enabled memory device writes the data from the channel 602.
[0056] Each channel 602 works independently. Further, multiple channels 602 can be active at the same time. Using this scheme, the system performance increases along with the number of channels 602 implemented, since the channels 602 operate in parallel.
[0057] Referring to Figure 8, a block diagram of a solid-state memory system in accordance with an alternate embodiment is illustrated by numeral 800. The present embodiment is similar to the previous embodiment and comprises a plurality of channels 602. However, in the present embodiment, each channel is assigned a specific type of solid-state memory device. That is, for an n-channel solid-state memory system 800, m channels are coupled exclusively to volatile memory devices 104a and n-m channels are coupled exclusively to non-volatile memory devices 104b.
[0058] Referring to Figure 9, a block diagram of a solid-state memory system in accordance with yet an alternate embodiment is illustrated by numeral 900. The solid-state memory system 900 comprises a memory controller 102 and a solid-state memory 104. In the present embodiment, the solid-state memory 104 comprises a plurality of volatile memory devices 104a and a plurality of non-volatile memory devices 104b. The volatile memory devices 104a and the non-volatile memory devices 104b are coupled with the memory controller 102 in a daisy chain configuration. That is, the memory controller 102 is coupled to a first one 902 of the memory devices 104a or 104b. The remaining memory devices 104a and 104b are serially coupled and a last serially coupled 904 memory device 104a or 104b is coupled back to the memory controller 102.
[0059] In order to access one of the solid-state memory devices 104a or 104b, the memory controller 102 outputs a request to the first memory device 902. The request is passed through the memory devices 104a and 104b until it reaches a target device. The target device performs the requested operation and the results, if any, continue to pass through the chain of memory devices until it reaches the last device 904, which returns the result to the memory controller 102.
Methods of using a daisy chain for activating one of a plurality of memory devices are well known in the art and need not be described in detail.
[0060] Referring to Figure 10, a block diagram of a solid-state memory system in accordance with yet an alternate embodiment is illustrated by numeral 1000. The solid-state memory system 1000 comprises a memory controller 102 and a solid-state memory 104. In the present embodiment, the solid-state memory 104 comprises a plurality of volatile memory devices 104a and a plurality of non-volatile memory devices 104b. The volatile memory devices 104a and the non-volatile memory devices 104b are coupled with the memory controller 104 in a daisy chain configuration. However, unlike the previous embodiment, the memory controller 104 controls a plurality of chains.
[0061] Each chain works independently. Further, multiple chains can be active at the same time.
Using this scheme, the system performance increases along with the number of chain implemented, since the chains operate in parallel.
[0062] Referring to Figure 11, a block diagram of a solid-state memory system in accordance with yet an alternate embodiment is illustrated by numeral 1100. The present embodiment is similar to the previous embodiment and comprises a plurality of chains.
However, in the present embodiment, each chain is assigned a specific type of solid-state memory device. That is, for an n-chain solid-state memory system 1100, m chains are coupled exclusively to volatile memory devices 104a and n-m chains are coupled exclusively to non-volatile memory devices 104b.
[0063] All of the previous embodiments described various ways of implementing an solid-state memory device comprising both volatile and non-volatile memory devices. The devices are combined in such a way as to improve the performance and effective life expectancy of the solid-state memory device.
[0064] Although the previous embodiments describe the volatile memory 104a as having fewer blocks 202 than the non-volatile memory 104b, this need not be the case. This arrangement will be the most likely embodiment due to volatile memory 104a limitations with regard to cost, size and persistence. However, there may be situations where the number of blocks for each of the volatile memory 104a and the non-volatile memory 104b are the same. Further, there may be situations where the number of blocks in the volatile memory 104a exceeds the number of blocks in the non-volatile memory 104b.
[0065] Lastly, although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (23)

1. A solid-state memory system comprising:
a volatile solid-state memory;
a non-volatile solid-state memory;
a memory controller configured to store write data in the volatile memory, the memory controller being further configured to transfer data from the volatile memory to the non-volatile memory in response to a data transfer request.
2. The solid-state memory system of claim 1, further comprising a mapping system configured to correlate a logical address of stored data with a physical address of stored data, the mapping system further configured to update the physical address of the write data when the write data is transferred to the non-volatile memory.
3. The solid-state memory system of claim 2, wherein the memory controller is further configured to transfer read data from the non-volatile memory to the volatile memory in response to a read command.
4. The solid-state memory system of claim 3 wherein the mapping system is further configured to update the physical address of the read data when the read data is transferred to the non-volatile memory.
5. The solid-state memory system of claim 1, wherein the non-volatile solid-state memory comprises a plurality of non-volatile solid-state devices.
6. The solid-state memory system of claim 5, wherein the volatile solid-state memory comprises a plurality of volatile solid-state devices.
7. The solid-state memory system of claim 6, wherein the plurality of volatile and non-volatile solid-state devices are coupled to the memory controller via a common bus.
8. The solid-state memory system of claim 6, wherein the plurality of volatile and non-volatile solid-state devices are coupled to the memory controller via plurality of buses, the buses capable of being accessed simultaneously.
9. The solid-state memory system of claim 8, wherein the each of the plurality of buses is coupled with either a plurality of volatile memory devices or a plurality of non-volatile memory devices.
10. The solid-state memory system of claim 6, wherein the plurality of volatile and non-volatile solid-state devices are coupled to the memory controller in a daisy chain.
11. The solid-state memory system of claim 6, wherein the plurality of volatile and non-volatile solid-state devices are coupled to the memory controller in a plurality of daisy chains, the daisy chains capable of being accessed simultaneously.
12. The solid-state memory system of claim 11, wherein the each of the plurality of daisy chains comprises either a plurality of volatile memory devices or a plurality of non-volatile memory devices.
13. The solid-state memory system of claim 3, wherein data written to the volatile memory further comprises a tag identifying whether the data is written in response to a read command or a write command.
14. A method for storing data in a solid-state memory system comprising a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller, the method comprising the steps of:
receiving a write command;

storing write data in the volatile memory in response to the write command;
and transferring data from the volatile memory to the non-volatile memory in response to a data transfer request.
15. The method of claim 14, further comprising the step of updating a mapping system when transferring data from the volatile memory to the non-volatile memory.
16. The method of claim 14, wherein the data transfer request is in response to a command requesting transfer of all data from the volatile memory to the non-volatile memory.
17. The method of claim 16, wherein the command requesting transfer of all data is a power down command.
18. The method of claim 14, wherein the data transfer request is in response to a lack of available space in the volatile memory.
19. The method of claim 18, wherein the data transfer request occurs when the available space in the volatile memory falls below a predefined threshold.
20. The method of claim 18, wherein the data transfer request occurs there is insufficient available space in the volatile memory to perform a requested command.
21. The method of claim 14, further comprising the step of transferring data from the non-volatile memory to the volatile memory in response to a read command.
22. The method of claim 21, further comprising the step of updating a mapping system when transferring data from the non-volatile memory to the volatile memory.
23. The method of claim 21, wherein the data transfer request occurs there is insufficient available space in the volatile memory to perform a requested command.
CA002669690A 2006-12-20 2007-12-18 Hybrid solid-state memory system having volatile and non-volatile memory Abandoned CA2669690A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/613,325 2006-12-20
US11/613,325 US7554855B2 (en) 2006-12-20 2006-12-20 Hybrid solid-state memory system having volatile and non-volatile memory
PCT/CA2007/002304 WO2008074140A1 (en) 2006-12-20 2007-12-18 Hybrid solid-state memory system having volatile and non-volatile memory

Publications (1)

Publication Number Publication Date
CA2669690A1 true CA2669690A1 (en) 2008-06-26

Family

ID=39535937

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002669690A Abandoned CA2669690A1 (en) 2006-12-20 2007-12-18 Hybrid solid-state memory system having volatile and non-volatile memory

Country Status (8)

Country Link
US (4) US7554855B2 (en)
EP (1) EP2100306A4 (en)
JP (4) JP5619423B2 (en)
KR (2) KR101495975B1 (en)
CN (2) CN101563729B (en)
CA (1) CA2669690A1 (en)
TW (2) TWI476780B (en)
WO (1) WO2008074140A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109741777A (en) * 2018-12-28 2019-05-10 上海新储集成电路有限公司 A kind of memory for improving speed and keeping data time

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554855B2 (en) * 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
EP3279798B1 (en) * 2007-03-30 2020-07-29 Rambus Inc. System including hierarchical memory modules having different types of integrated circuit memory devices
US8874831B2 (en) * 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
US7855916B2 (en) * 2007-10-24 2010-12-21 Rao G R Mohan Nonvolatile memory systems with embedded fast read and write memories
US10236032B2 (en) * 2008-09-18 2019-03-19 Novachips Canada Inc. Mass data storage system with non-volatile memory modules
JP5198245B2 (en) 2008-12-27 2013-05-15 株式会社東芝 Memory system
US8489843B2 (en) * 2010-04-20 2013-07-16 Chip Memory Technology, Inc. Configurable memory device
US9058675B2 (en) * 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
US20120026802A1 (en) * 2010-07-30 2012-02-02 Emanuele Confalonieri Managed hybrid memory with adaptive power supply
US10838646B2 (en) 2011-07-28 2020-11-17 Netlist, Inc. Method and apparatus for presearching stored data
US10380022B2 (en) 2011-07-28 2019-08-13 Netlist, Inc. Hybrid memory module and system and method of operating the same
US10198350B2 (en) 2011-07-28 2019-02-05 Netlist, Inc. Memory module having volatile and non-volatile memory subsystems and method of operation
US8570799B2 (en) * 2011-08-16 2013-10-29 Intel Mobile Communications GmbH Magnetic random access memory with conversion circuitry
EP3712774B1 (en) 2011-09-30 2023-02-15 Tahoe Research, Ltd. Apparatus and method for implementing a multi-level memory hierarchy
EP3451176B1 (en) 2011-09-30 2023-05-24 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
US9342453B2 (en) 2011-09-30 2016-05-17 Intel Corporation Memory channel that supports near memory and far memory access
EP2761480A4 (en) * 2011-09-30 2015-06-24 Intel Corp Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
WO2013062542A1 (en) 2011-10-26 2013-05-02 Hewlett-Packard Development Company Segmented caches
US9697872B2 (en) * 2011-12-07 2017-07-04 Cypress Semiconductor Corporation High speed serial peripheral interface memory subsystem
US9507534B2 (en) 2011-12-30 2016-11-29 Intel Corporation Home agent multi-level NVM memory architecture
KR101380602B1 (en) * 2012-03-07 2014-04-04 한국과학기술원 Wear-Leveling Method for Non-Volatile Memory in Hybrid Memory System and Hybrid Memory System
WO2013165385A1 (en) * 2012-04-30 2013-11-07 Hewlett-Packard Development Company, L.P. Preventing a hybrid memory module from being mapped
US9063864B2 (en) 2012-07-16 2015-06-23 Hewlett-Packard Development Company, L.P. Storing data in presistent hybrid memory
JP6000754B2 (en) * 2012-08-28 2016-10-05 キヤノン株式会社 Image processing apparatus, image processing apparatus control method, and program
CN103631722A (en) * 2012-08-29 2014-03-12 联想(北京)有限公司 Data processing method and electronic equipment
US9471484B2 (en) 2012-09-19 2016-10-18 Novachips Canada Inc. Flash memory controller having dual mode pin-out
US9417819B2 (en) * 2012-11-13 2016-08-16 Toshiba, Corporation Cache device for hard disk drives and methods of operations
EP2923358A4 (en) * 2012-11-20 2016-06-29 Charles I Peddle Solid state drive architectures
WO2015047266A1 (en) * 2013-09-26 2015-04-02 Intel Corporation Block storage apertures to persistent memory
US9436563B2 (en) 2013-10-01 2016-09-06 Globalfoundries Inc. Memory system for mirroring data
US9400745B2 (en) * 2013-11-06 2016-07-26 International Business Machines Corporation Physical address management in solid state memory
CN111274063A (en) * 2013-11-07 2020-06-12 奈特力斯股份有限公司 Hybrid memory module and system and method for operating the same
US10248328B2 (en) 2013-11-07 2019-04-02 Netlist, Inc. Direct data move between DRAM and storage on a memory module
JP2015141575A (en) * 2014-01-29 2015-08-03 京セラドキュメントソリューションズ株式会社 Image formation device and control method
CN103811051B (en) * 2014-02-17 2017-01-11 上海新储集成电路有限公司 Hierarchical memory array and working method thereof
US9684853B2 (en) * 2014-04-15 2017-06-20 Kyocera Document Solutions Inc. Image forming apparatus that writes data from volatile memory to non-volatile memory
TWI525428B (en) * 2014-06-04 2016-03-11 仁寶電腦工業股份有限公司 Management method of hybrid storage unit and electronic apparatus thereof
CA2894936C (en) * 2014-06-27 2018-02-27 Chenyi Zhang Controller, flash memory apparatus, and method for writing data into flash memory apparatus
CN104575595B (en) * 2014-12-12 2017-07-07 杭州华澜微电子股份有限公司 The storage device of non-volatile random access
US20160188414A1 (en) * 2014-12-24 2016-06-30 Intel Corporation Fault tolerant automatic dual in-line memory module refresh
EP3268864B1 (en) 2015-03-11 2021-01-27 Rambus Inc. High performance non-volatile memory module
WO2016171934A1 (en) * 2015-04-20 2016-10-27 Netlist, Inc. Memory module and system and method of operation
US9536619B2 (en) * 2015-05-27 2017-01-03 Kabushiki Kaisha Toshiba Hybrid-HDD with improved data retention
US9904490B2 (en) * 2015-06-26 2018-02-27 Toshiba Memory Corporation Solid-state mass storage device and method for persisting volatile data to non-volatile media
US20170060434A1 (en) * 2015-08-27 2017-03-02 Samsung Electronics Co., Ltd. Transaction-based hybrid memory module
US10838818B2 (en) 2015-09-18 2020-11-17 Hewlett Packard Enterprise Development Lp Memory persistence from a volatile memory to a non-volatile memory
US9761312B1 (en) 2016-03-16 2017-09-12 Micron Technology, Inc. FeRAM-DRAM hybrid memory
US20190095136A1 (en) * 2016-03-29 2019-03-28 Sony Corporation Memory control device, storage device, and information processing system
CN106201902A (en) * 2016-06-24 2016-12-07 中电海康集团有限公司 The composite array module of a kind of SRAM bit and non-volatile memories bit composition and read/writing control method thereof
CN107515729A (en) * 2016-06-24 2017-12-26 中电海康集团有限公司 The composite array module and method of work of a kind of SRAM bits and non-volatile memories bit composition
US10354716B2 (en) * 2016-09-16 2019-07-16 Aspiring Sky Co. Limited SRAM based memory structures and methods thereof
WO2018106441A1 (en) 2016-12-09 2018-06-14 Rambus Inc. Memory module for platform with non-volatile storage
KR20180078512A (en) * 2016-12-30 2018-07-10 삼성전자주식회사 Semiconductor device
US10785301B2 (en) * 2017-08-03 2020-09-22 Toshiba Memory Corporation NVM express over fabrics
US10437499B2 (en) * 2017-12-22 2019-10-08 Nanya Technology Corporation Hybrid memory system and method of operating the same
US10691805B2 (en) * 2018-02-14 2020-06-23 GM Global Technology Operations LLC Resident manufacturing test software based system for mitigating risks associated with vehicle control modules
US11307779B2 (en) * 2019-09-11 2022-04-19 Ceremorphic, Inc. System and method for flash and RAM allocation for reduced power consumption in a processor
CN115145489B (en) * 2022-07-22 2023-03-24 北京熵核科技有限公司 Object scanning method based on cache structure

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430859A (en) 1991-07-26 1995-07-04 Sundisk Corporation Solid state memory system including plural memory chips and a serialized bus
US5359569A (en) * 1991-10-29 1994-10-25 Hitachi Ltd. Semiconductor memory
JPH05216775A (en) * 1991-10-29 1993-08-27 Hitachi Ltd Semiconductor memory device
JPH05299616A (en) * 1992-04-16 1993-11-12 Hitachi Ltd Semiconductor storage device
JP2768618B2 (en) * 1992-08-28 1998-06-25 シャープ株式会社 Semiconductor disk device
JPH07200390A (en) * 1993-12-28 1995-08-04 Toshiba Corp Data access method
US5475854A (en) 1994-01-28 1995-12-12 Vlsi Technology, Inc. Serial bus I/O system and method for serializing interrupt requests and DMA requests in a computer system
US5404460A (en) 1994-01-28 1995-04-04 Vlsi Technology, Inc. Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus
JPH0877066A (en) * 1994-08-31 1996-03-22 Tdk Corp Flash memory controller
JPH08129509A (en) * 1994-11-01 1996-05-21 Canon Inc Unit and method for memory control
US5636342A (en) 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
US6418506B1 (en) 1996-12-31 2002-07-09 Intel Corporation Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array
US6453365B1 (en) 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US6144576A (en) 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
US6304921B1 (en) 1998-12-07 2001-10-16 Motorola Inc. System for serial peripheral interface with embedded addressing circuit for providing portion of an address for peripheral devices
JP2000288238A (en) * 1999-04-02 2000-10-17 Konami Co Ltd Game system
US7827348B2 (en) * 2000-01-06 2010-11-02 Super Talent Electronics, Inc. High performance flash memory devices (FMD)
JP2001051896A (en) 1999-08-04 2001-02-23 Hitachi Ltd Storage device
US6513094B1 (en) * 1999-08-23 2003-01-28 Advanced Micro Devices, Inc. ROM/DRAM data bus sharing with write buffer and read prefetch activity
US6484250B1 (en) 2000-01-19 2002-11-19 Qualcomm, Incorporated Hash technique eliminating pointer storage to reduce RAM size
JP2001265708A (en) * 2000-03-16 2001-09-28 Toshiba Corp Electronic equipment and substrate for the same
US6816933B1 (en) 2000-05-17 2004-11-09 Silicon Laboratories, Inc. Serial device daisy chaining method and apparatus
US6658509B1 (en) 2000-10-03 2003-12-02 Intel Corporation Multi-tier point-to-point ring memory interface
JP3992960B2 (en) * 2000-10-26 2007-10-17 松下電器産業株式会社 Recording apparatus and program
EP1466326A2 (en) * 2001-01-17 2004-10-13 Honeywell International Inc. Enhanced memory module architecture
US6763424B2 (en) 2001-01-19 2004-07-13 Sandisk Corporation Partial block data programming and reading operations in a non-volatile memory
JP4017177B2 (en) 2001-02-28 2007-12-05 スパンション エルエルシー Memory device
US6996644B2 (en) 2001-06-06 2006-02-07 Conexant Systems, Inc. Apparatus and methods for initializing integrated circuit addresses
JP2003015928A (en) * 2001-07-04 2003-01-17 Nec System Technologies Ltd Data storage device for flash memory and data storage method used therefor
US6928501B2 (en) 2001-10-15 2005-08-09 Silicon Laboratories, Inc. Serial device daisy chaining method and apparatus
JP2003186579A (en) * 2001-12-19 2003-07-04 Toshiba Corp Electronic device and operation control method of the same
ITTO20020118A1 (en) 2002-02-08 2003-08-08 St Microelectronics Srl INTEGRATING DEVICE A NON VOLATILE MEMORY MATRIX AND A VOLATILE MEMORY MATRIX.
JP2003256269A (en) 2002-02-27 2003-09-10 Matsushita Electric Ind Co Ltd Control method for nonvolatile storage device, and memory device
US7073022B2 (en) 2002-05-23 2006-07-04 International Business Machines Corporation Serial interface for a data storage array
US7231484B2 (en) * 2002-09-30 2007-06-12 Telefonaktiebolaget Lm Ericsson (Publ) Method and memory controller for scalable multi-channel memory access
CN100339823C (en) * 2002-10-08 2007-09-26 松下电器产业株式会社 Program updating method and terminal device
US7032039B2 (en) 2002-10-30 2006-04-18 Atmel Corporation Method for identification of SPI compatible serial memory devices
CN1717662B (en) * 2002-11-28 2010-04-28 株式会社瑞萨科技 Memory module, memory system, and information device
US7308524B2 (en) 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US6775184B1 (en) 2003-01-21 2004-08-10 Nexflash Technologies, Inc. Nonvolatile memory integrated circuit having volatile utility and buffer memories, and method of operation thereof
US20040193782A1 (en) * 2003-03-26 2004-09-30 David Bordui Nonvolatile intelligent flash cache memory
JP4460850B2 (en) 2003-05-21 2010-05-12 株式会社東芝 IC card and IC card processing method
CN100353336C (en) * 2003-06-27 2007-12-05 富士通株式会社 Data transmission method and system
US20050132128A1 (en) 2003-12-15 2005-06-16 Jin-Yub Lee Flash memory device and flash memory system including buffer memory
US7031221B2 (en) 2003-12-30 2006-04-18 Intel Corporation Fixed phase clock and strobe signals in daisy chained chips
JP4628684B2 (en) 2004-02-16 2011-02-09 三菱電機株式会社 Data transmitting / receiving apparatus and electronic certificate issuing method
US7269708B2 (en) * 2004-04-20 2007-09-11 Rambus Inc. Memory controller for non-homogenous memory system
US6950325B1 (en) 2004-10-07 2005-09-27 Winbond Electronics Corporation Cascade-connected ROM
KR100578143B1 (en) * 2004-12-21 2006-05-10 삼성전자주식회사 Storage system with scheme capable of invalidating data stored in buffer memory and computing system including the same
KR100626393B1 (en) 2005-04-07 2006-09-20 삼성전자주식회사 Non-volatile memory device and multi-page copyback method thereof
EP1712985A1 (en) * 2005-04-15 2006-10-18 Deutsche Thomson-Brandt Gmbh Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data I/O bus
KR101257848B1 (en) * 2005-07-13 2013-04-24 삼성전자주식회사 Data storing apparatus comprising complex memory and method of operating the same
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7516267B2 (en) * 2005-11-03 2009-04-07 Intel Corporation Recovering from a non-volatile memory failure
CN100507886C (en) * 2005-12-22 2009-07-01 北京中星微电子有限公司 Method of direct storage access for non-volatility storage and its device
JP2007206799A (en) * 2006-01-31 2007-08-16 Toshiba Corp Data transfer device, information recording reproduction device and data transfer method
KR100765786B1 (en) * 2006-06-12 2007-10-12 삼성전자주식회사 Flash memory system, host system for programming and program method thereof
US7685393B2 (en) * 2006-06-30 2010-03-23 Mosaid Technologies Incorporated Synchronous memory read data capture
US7539811B2 (en) * 2006-10-05 2009-05-26 Unity Semiconductor Corporation Scaleable memory systems using third dimension memory
US7508724B2 (en) * 2006-11-30 2009-03-24 Mosaid Technologies Incorporated Circuit and method for testing multi-device systems
US7554855B2 (en) * 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
KR100909965B1 (en) * 2007-05-23 2009-07-29 삼성전자주식회사 A semiconductor memory system having a volatile memory and a nonvolatile memory sharing a bus and a method of controlling the operation of the nonvolatile memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109741777A (en) * 2018-12-28 2019-05-10 上海新储集成电路有限公司 A kind of memory for improving speed and keeping data time

Also Published As

Publication number Publication date
TW201517051A (en) 2015-05-01
US20090279366A1 (en) 2009-11-12
US20080155185A1 (en) 2008-06-26
US20110153973A1 (en) 2011-06-23
KR101495928B1 (en) 2015-02-25
KR20090102767A (en) 2009-09-30
US20140185379A1 (en) 2014-07-03
KR101495975B1 (en) 2015-02-26
KR20130005305A (en) 2013-01-15
CN101563729B (en) 2013-09-25
TWI476780B (en) 2015-03-11
JP2010514017A (en) 2010-04-30
CN103558993A (en) 2014-02-05
US8670262B2 (en) 2014-03-11
JP2013200889A (en) 2013-10-03
EP2100306A1 (en) 2009-09-16
EP2100306A4 (en) 2010-03-10
US7924635B2 (en) 2011-04-12
JP2013061997A (en) 2013-04-04
JP5619423B2 (en) 2014-11-05
US7554855B2 (en) 2009-06-30
TW200841352A (en) 2008-10-16
JP2016026346A (en) 2016-02-12
CN101563729A (en) 2009-10-21
WO2008074140A1 (en) 2008-06-26

Similar Documents

Publication Publication Date Title
US8670262B2 (en) Hybrid solid-state memory system having volatile and non-volatile memory
US8041884B2 (en) Controller for non-volatile memories and methods of operating the memory controller
US10915475B2 (en) Methods and apparatus for variable size logical page management based on hot and cold data
US11232041B2 (en) Memory addressing
US8817537B2 (en) Nonvolatile memory systems with embedded fast read and write memories
US5627783A (en) Semiconductor disk device
US20050015557A1 (en) Nonvolatile memory unit with specific cache
US6366977B1 (en) Semiconductor storage device employing cluster unit data transfer scheme and data management method thereof
US20160231941A1 (en) Solid state memory (ssm), computer system including an ssm, and method of operating an ssm
US10991422B2 (en) Data storage device using a host memory buffer for single-level cell storage and control method for non-volatile memory
US20050055493A1 (en) [method for accessing large block flash memory]
US8745312B2 (en) Storage device and method of mapping a nonvolatile memory based on a map history
US20090210612A1 (en) Memory controller, nonvolatile memory device, and nonvolatile memory system
KR20090042077A (en) File management system and method
US11182286B2 (en) Data storage device and control method for non-volatile memory
KR20100055374A (en) File management system and method

Legal Events

Date Code Title Description
EEER Examination request
FZDE Discontinued

Effective date: 20161212