CN100399288C - Memory backup device and method - Google Patents
Memory backup device and method Download PDFInfo
- Publication number
- CN100399288C CN100399288C CNB2005101125077A CN200510112507A CN100399288C CN 100399288 C CN100399288 C CN 100399288C CN B2005101125077 A CNB2005101125077 A CN B2005101125077A CN 200510112507 A CN200510112507 A CN 200510112507A CN 100399288 C CN100399288 C CN 100399288C
- Authority
- CN
- China
- Prior art keywords
- memory
- backup
- rambus
- write
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
A back-up device of internal memory is prepared as connecting internal memory to waiting storage controller being used to latch address bus and data bus of internal memory, copying content of internal memory into nonvolatile storage connected with waiting storage controller by waiting storage controller when internal memory bus is on idle state for finalizing internal memory back-up, connecting waiting storage controller on bus of internal memory and setting operation of internal memory controller to be prior than that of waiting storage controller.
Description
Technical field
The present invention relates to memory backup device and method, relate in particular to and utilize nonvolatile memory to carry out the apparatus and method of Dram backup.
Background technology
Internal memory plays an important role in computing machine as the operation carrier of all computer programs.Calculator memory all is to adopt the storer that easily loses type at present, though travelling speed is fast, when not having the power supply power supply, the content in the storer all can be lost.If internal memory adopts nonvolatile memory, because its access speed is too slow, so can't satisfy the service requirement of present computer system.
In order to overcome the above problems, common way is that the content in the internal memory is stored in the large-scale nonvolatile memory (for example hard disk) at present, and computing machine can cut off the power supply then.But, will cause the speed of switching slack-off to and fro from the disk copy data.
In S3 (S3 is commonly referred to STR (Suspend to RAM), suspends to internal memory), promptly, to close hard disk behind the operating data write memory, because the storer of CPU inside (such as cache memory, register etc.) can't keep content, have to be in internal memory with the environment copy, use standby (STANDBY) power supply to power then, provide and write with a brush dipped in Chinese ink circuit, guarantee to keep the content in the internal memory to internal memory, the power-off of other parts of system then, comprise CPU, hard disk, peripheral hardware etc.Deng when system is recovered again, cpu reset restarts the content in the running memory again.
In this case, system depends on the reliability of S3, if S3 feed circuit instability will cause loss of data.For this reason, existing United States Patent (USP) has proposed to copy the content in the internal memory to solution such in the hard disk for the 6th, 389, No. 556 and has overcome the problems referred to above.But, in this solution,, and need can underspeed like this through being transformed into the IDE bus through pci bus again after the processing of south bridge because the speed of content copy is slow.
In addition, in United States Patent (USP) 6,546, the disposal route that has disclosed a kind of about Memory Backup No. 472, it accelerates the speed of access by reducing each access in the internal memory to the content on the hard disk, but this disposal route need be through the intervention of operating system, implementation procedure more complicated.And it is slow to solve harddisk access speed equally, must be through the problem of south bridge north bridge conversion.
In addition, be subjected to present technical limitation, the access speed of nonvolatile memory is slower, if directly connect internal memory, it will drag slow rambus, even causes loss of data.
And existing various bussing techniques such as PCI, all are to utilize method such as wait to carry out the coordination of the bus of friction speed.Like this, in the visit slow devices, in order to guarantee the correct read-write of access content, bus often adopts the mode of wait, pins data-signal with latch earlier, and then with writing data into memory, latch discharges then.During this period, bus is if read and write, owing in the visit slow devices, finish so bus must be waited for the visit of this slow devices, thereby whole read or write speed all can be affected.
Therefore, be necessary to provide a kind of speed of Memory Backup, apparatus and method that the while does not influence the internal memory normal running of improving.
Summary of the invention
First purpose of the present invention is to provide a kind of speed of Memory Backup, memory backup device that the while does not influence the internal memory normal running of improving.
Second purpose of the present invention is to provide a kind of speed of Memory Backup, Memory Backup method that the while does not influence the internal memory normal running of improving.
According to first purpose of the present invention, a kind of memory backup device is provided, comprising internal memory and Memory Controller Hub, Memory Controller Hub utilizes rambus internally to deposit into the row read-write, it is characterized in that, comprise: wait for memory controller and nonvolatile memory, these controllers to be stored link to each other with internal memory on rambus, wherein, wait for that memory controller latchs the address bus and the data bus of internal memory, when rambus is in idle condition, wait for that memory controller with in the nonvolatile memory that the memory content that latchs copies to these controllers to be stored link to each other, carries out Memory Backup, these controllers to be stored linked to each other with interior the existence on the rambus, wherein, the operator precedence of Memory Controller Hub when Memory Controller Hub will internally deposit into the row read-write, stops this Memory Backup in waiting for memory controller, releasing memory bus, and the read-write of internally depositing.
According to second purpose of the present invention, a kind of Memory Backup method that is used for above-mentioned memory backup device is provided, wherein Memory Controller Hub utilizes rambus internally to deposit into the row read-write, and it is characterized in that: address bus and data bus to internal memory latch; And when rambus is in idle condition, memory content is copied in the nonvolatile memory, carry out Memory Backup, wherein, Memory Controller Hub has precedence over this Memory Backup to the read-write of internal memory, when Memory Controller Hub will internally deposit into the row read-write, stop this Memory Backup, and the read-write of internally depositing.
The invention has the beneficial effects as follows: though Memory Controller Hub has precedence over the Memory Backup of nonvolatile memory to the read-write of internal memory, make that the Memory Backup of nonvolatile memory is always interrupted, but utilize rambus idle period of time to carry out Memory Backup, so can copy in the nonvolatile memory at the full content with internal memory of shutdown (power down) preceding prestissimo, realize the dynamic backup of memory content, and saved the Memory Backup time; Because Memory Controller Hub is preferential action to the read-write of internal memory,, nonvolatile memory do not influence the normal running of internal memory on bus so linking to each other with internal memory; After the power down, can maintain most information; And it is fast to restart speed, does not need from the hard disk reading of data, and can recover full memory.
Description of drawings
Fig. 1 has shown the structured flowchart according to memory backup device of the present invention;
Fig. 2 has shown the concrete structure block diagram according to wait memory controller 3 of the present invention;
Fig. 3 has shown the concrete structure block diagram according to the memory backup device of preferred embodiment of the present invention;
Fig. 4 has shown the concrete synoptic diagram according to structure annexation in the memory backup device of preferred embodiment of the present invention.
Embodiment
The present invention preserves memory content by adopting nonvolatile memory, thereby improves the speed of Memory Backup.Different with the method for being mentioned in the above-mentioned background technology is that the present invention directly links to each other with internal memory by the nonvolatile memory on rambus, to improve the speed of backup access.
Fig. 1 has shown the structured flowchart according to memory backup device of the present invention.As shown in Figure 1, comprise internal memory 1, Memory Controller Hub 2, wait for memory controller 3 and nonvolatile memory 4 according to memory backup device of the present invention.
Wherein, internal memory 1 and Memory Controller Hub 2 link to each other by rambus according to prior art, thereby Memory Controller Hub 2 controls are to the storage of internal memory 1.Difference from prior art is, waits for that memory controller 3 links to each other on rambus with Memory Controller Hub 2 with internal memory 1, and waits for that memory controller 3 links to each other with nonvolatile memory 4.
At this moment,, wait for memory controller 3 in the control of carrying out Memory Backup, do not require that non-volatile memory catches up with the variation of internal memory constantly, and take the way of losing though nonvolatile memory 4 directly links to each other with internal memory 1.Concrete backup procedure is: under the control of waiting for memory controller 3, change little in 4 elder generations of nonvolatile memory copy memory content, perhaps change slower memory contents, thereby can guarantee that most of memory content can obtain backup on nonvolatile memory 4, therefore, before power down, only need be to nonvolatile memory 4 the content stores of remaining not backup in the memory content, thus finish Memory Backup.So just accelerated whole memory content is backuped to speed on the nonvolatile memory 4.
But, wait for so can not when writing Fei Yishi storer 4, make rambus continue (HOLD), thereby need in control, set up back mechanism rambus because 1 read or write speed is all very fast from Memory Controller Hub 2 to internal memory.
Back mechanism provided by the present invention is set up override mechanism exactly: when nonvolatile memory 4 utilizes rambus to carry out Memory Backup, if 2 pairs of internal memories of Memory Controller Hub 1 carry out read-write motion, then the read-write of 2 pairs of internal memories 1 of Memory Controller Hub is preferential action, and rambus discharges to memory read-write simultaneously; When having only rambus to be idle condition, nonvolatile memory 4 just uses rambus under the control of waiting for memory controller 3.
Therefore, according to above Memory Backup process and back mechanism, the present invention has following advantage: though the read-write of 2 pairs of internal memories 1 of Memory Controller Hub has precedence over the Memory Backup of nonvolatile memory 4, make that the Memory Backup of nonvolatile memory 4 is always interrupted, but utilize rambus idle period of time to carry out Memory Backup, so can copy in the nonvolatile memory 4 at the full content with internal memory of shutdown (power down) preceding prestissimo, realize the dynamic backup of memory content, and saved the Memory Backup time; Because the read-write of 2 pairs of internal memories 1 of Memory Controller Hub is preferential action,, nonvolatile memory 4 do not influence the normal running of internal memory 1 on bus so linking to each other with internal memory 1; After the power down, can maintain most information; And it is fast to restart speed, does not need from the hard disk reading of data, and can recover full memory.
To specify below and wait for that 3 pairs of memory controllers utilize nonvolatile memory 4 to carry out the control of Memory Backup.
The wait memory controller 3 that the present invention is provided with between Memory Controller Hub 2 and nonvolatile memory 4 adopts the control hierarchy lower to rambus.In other words, set up arbitration mechanism between Memory Controller Hub 2 and the wait memory controller 3, promptly for rambus, the rank of Memory Controller Hub 2 is than the priority level height of waiting for memory controller 3.Thereby when two controllers are all want rambus controlled, wait for that memory controller 3 makes way for Memory Controller Hub 2, operate by Memory Controller Hub 2.Wait for that memory controller 3 only just takies bus in bus during for idle condition, copies memory content in the nonvolatile memory 4 to.
Fig. 2 has shown the concrete structure block diagram according to wait memory controller 3 of the present invention.
As shown in Figure 2, wait for that memory controller 3 comprises bus arbitration controller 31, data latches 32 and non-volatile memory driver 33.
Wherein, bus arbitration controller 31, data latches 32 and non-volatile memory driver 33 interconnect respectively, and bus arbitration controller 31 and data latches 32 be connected in rambus, and non-volatile memory driver 33 is connected in nonvolatile memory 4.
When carrying out Memory Backup, because the changed condition of rambus is too fast, nonvolatile memory 4 does not catch up with the pace of change of rambus, so data latches 32 is at first handled the address and the data of memory content, address bus and data bus is latched.
When bus is in idle condition, bus arbitration controller 31 is triggered automatically, thereby control is to the backup of memory content, the address and the data of the memory content that utilizes non-volatile memory driver 33 and latch according to data latches 32 are carried out the dynamic memory (storage that can be interrupted) of memory content at nonvolatile memory 4.
Therefore when bus was in idle condition, memory backup device of the present invention can carry out Memory Backup automatically, does not disturb the read-write of 2 pairs of internal memories 1 of Memory Controller Hub.
To be further detailed embodiments of the present invention according to specific embodiment below.
Preferred embodiment
Fig. 3 has shown the concrete structure block diagram according to the memory backup device of preferred embodiment of the present invention.
As shown in Figure 3, the memory backup device of present embodiment comprises DIMM (two-wire internal memory module) Memory Controller Hub 41, DIMM internal memory 42, read write command controller 43, data latches 44 and FLASH (quickflashing) storer 45.Wherein the set of read write command controller 43 and data latches 44 and the non-volatile memory driver that do not show is corresponding to aforesaid wait memory controller 3.
Wherein DIMM Memory Controller Hub 41 and DIMM internal memory 42 are by rambus (data bus, address bus and command line) link to each other, link to each other by command line between read write command controller 43 and DIMM Memory Controller Hub 41 and the DIMM internal memory 42, link to each other with address bus by data bus between data latches 44 and DIMM Memory Controller Hub 41 and the DIMM internal memory 42, read write command controller 43 and data latches 44 interconnect, and read write command controller 43 is linked to each other with FLASH storer 45 by command line, and data latches 44 is linked to each other with FLASH storer 45 by command line.
Because FLASH storer 45 can not be caught up with the fast-changing state of rambus, so data latches 44 is at first handled the address and the data of memory content, address and data is latched.FLASH storer 45 can slowly carry out dynamic Memory Backup afterwards, and does not disturb the operation of rambus.
When 41 pairs of DIMM internal memories 42 of DIMM Memory Controller Hub are read and write (rambus is in the state that takies), read write command controller 43 is not operated; When rambus is in idle state, read write command controller 43 is triggered, thereby according to data latches 44 latched data, control data copies in the FLASH storer 45, thereby finish dynamic backup to memory content, till the content in all the elements in FLASH storer 45 and the DIMM internal memory 42 is consistent.
It should be noted that this read write command controller 43 is similar to DMA (direct memory access) controller, only this read write command controller 43 does not need software trigger, but hardware triggers the i.e. just triggering bus free time automatically.
Table one has shown the control signal truth table of DIMM Memory Controller Hub 41 and read write command controller 43.It has further shown the read-write of DIMM internal memory 42 and the access relationships between FLASH storer 45 and the DIMM internal memory 42.
Table one control signal truth table
| /MW | /MR | /FW | /FR | /MO | State |
| H | L | X | X | L | Internal memory is write |
| L | H | X | X | L | Internal memory is read |
| H | L | H | L | H | Internal memory is toward FLASH storer copy |
| L | H | L | H | H | The FLASH storer is toward memory copying |
Wherein, MW represents the rambus write signal, and MR represents the rambus read signal, and FW represents the FLASH memory write signals, FR represents FLASH memory read signal, and MO represents operation signal, and "/" expression low level is effective, H represents high level, and L represents low level, and no matter X represents what state.
To specifically introduce below between internal memory in the memory backup device shown in Figure 3 (DIMM internal memory) and the nonvolatile memory (FLASH storer) and be connected corresponding relation.
Fig. 4 has shown according to the connection of the structure in the memory backup device of preferred embodiment of the present invention corresponding relation.Here be example description architecture annexation with 8 position datawires, it should be noted that memory backup device of the present invention can comprise the long numeric data line.
As shown in Figure 4, here to wait for read write command controller 43, data latches 44 that shows in memory controller 3 presentation graphs 3 and the non-volatile memory driver that does not show.Wherein, this DIMM Memory Controller Hub 42 comprises 8 memory block D0, the D1...D7s corresponding with 8 position datawires; These controllers 3 to be stored comprise 8 sub-controllers corresponding with 8 position datawires; And this FLASH storer 45 comprises 8 quantum memories corresponding with 8 position datawires.That is to say corresponding memory block on each data line, a sub-controller and a quantum memory.
Corresponding a memory block on each data line, a sub-controller, carry out as shown in Figure 1 operation with a quantum memory, promptly when rambus is in idle condition, sub-controller copies the content of corresponding memory block in the corresponding FLASH quantum memory to, just adopt the copy mode of bit-by-bit back-to-back, thereby realize the dynamic content backup.
It should be noted that the number of data line number, memory block, the number of sub-controller and the number of quantum memory are corresponding, and can be arbitrary value.
Because present embodiment utilizes minor structure to copy, thereby realize the bit-by-bit copy mode, guarantee the accurate copy of data.
In sum, memory backup device provided by the invention and method have following advantage: though the read-write of 2 pairs of internal memories 1 of Memory Controller Hub has precedence over the Memory Backup of nonvolatile memory 4, make that the Memory Backup of nonvolatile memory 4 is always interrupted, but utilize rambus idle period of time to carry out Memory Backup, so can copy in the nonvolatile memory 4 at the full content with internal memory of shutdown (power down) preceding prestissimo, realize the dynamic backup of memory content, and saved the Memory Backup time; Because the read-write of 2 pairs of internal memories 1 of Memory Controller Hub is preferential action,, nonvolatile memory 4 do not influence the normal running of internal memory 1 on bus so linking to each other with internal memory 1; After the power down, can maintain most information; And it is fast to restart speed, does not need from the hard disk reading of data, and can recover full memory.
Concerning those skilled in the art, can associate other advantage and distortion easily according to above embodiment.Therefore, the present invention is not limited to above-mentioned specific embodiment, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.In the scope that does not deviate from aim of the present invention, those of ordinary skills can replace resulting technical scheme by various being equal to according to above-mentioned specific embodiment, but these technical schemes all should be included in the scope of claim of the present invention and the scope that is equal within.
Claims (10)
1. memory backup device, comprising internal memory and Memory Controller Hub, Memory Controller Hub utilizes rambus internally to deposit into the row read-write, it is characterized in that, comprising: wait for memory controller and nonvolatile memory, these controllers to be stored link to each other with internal memory on rambus, wherein
Wait for that memory controller latchs the address bus and the data bus of internal memory, when rambus is in idle condition, wait for that memory controller is with in the nonvolatile memory that the memory content that latchs copies to these controllers to be stored link to each other, carry out Memory Backup, these controllers to be stored linked to each other with interior the existence on the rambus, wherein, the operator precedence of Memory Controller Hub is in waiting for memory controller, when Memory Controller Hub will internally deposit into the row read-write, stop this Memory Backup, releasing memory bus, and the read-write of internally depositing.
2. memory backup device as claimed in claim 1, wherein,
When rambus was in idle condition, these controllers to be stored are triggered automatically carried out Memory Backup.
3. memory backup device as claimed in claim 2, wherein,
Memory content is copied in the process of nonvolatile memory at these controllers to be stored, these controllers to be stored at first copy changing little memory content.
4. memory backup device as claimed in claim 3, wherein,
Memory content is copied in the process of nonvolatile memory at these controllers to be stored, between internal memory and nonvolatile memory, adopt the copy mode of bit-by-bit back-to-back.
5. memory backup device as claimed in claim 4, wherein,
The number of the sub-controller that the number of the memory block that this internal memory has and these controllers to be stored have and the number of the quantum memory that nonvolatile memory has are corresponding, and on each data line corresponding one by one a memory block, a sub-controller and a quantum memory.
6. Memory Backup method, wherein Memory Controller Hub utilizes rambus internally to deposit into the row read-write, it is characterized in that:
Address bus and data bus to internal memory latch; And
When rambus is in idle condition, the memory content that latchs is copied in the nonvolatile memory, carry out Memory Backup, wherein, Memory Controller Hub has precedence over this Memory Backup to the read-write of internal memory, when Memory Controller Hub will internally deposit into the row read-write, stops this Memory Backup, releasing memory bus, and the read-write of internally depositing.
7. Memory Backup method as claimed in claim 6, wherein,
When rambus is in idle condition, triggers automatically and carry out Memory Backup.
8. Memory Backup method as claimed in claim 7, wherein,
Memory content is being copied in the process of nonvolatile memory, at first copying changing little memory content.
9. Memory Backup method as claimed in claim 8, wherein,
Memory content is being copied in the process of nonvolatile memory, between internal memory and nonvolatile memory, adopting the copy mode of bit-by-bit back-to-back.
10. Memory Backup method as claimed in claim 9, wherein,
The number of the memory block that internal memory had, the number of the quantum memory in amount of capacity and the nonvolatile memory, amount of capacity is corresponding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101125077A CN100399288C (en) | 2005-09-30 | 2005-09-30 | Memory backup device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101125077A CN100399288C (en) | 2005-09-30 | 2005-09-30 | Memory backup device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1940876A CN1940876A (en) | 2007-04-04 |
| CN100399288C true CN100399288C (en) | 2008-07-02 |
Family
ID=37959086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101125077A Expired - Fee Related CN100399288C (en) | 2005-09-30 | 2005-09-30 | Memory backup device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100399288C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI474165B (en) | 2009-03-13 | 2015-02-21 | Prolific Technology Inc | Data storage system and backup method thereof |
| CN101609435B (en) * | 2009-03-24 | 2012-01-04 | 成都市华为赛门铁克科技有限公司 | Method of power failure protection of equipment, electronic equipment and network system |
| CN104077245B (en) * | 2013-03-27 | 2018-05-29 | 南通研祥智能科技有限公司 | A kind of NVRAM control methods and system |
| CN104102750B (en) * | 2013-04-11 | 2018-04-27 | 深圳市腾讯计算机系统有限公司 | Operation data recording method, device and server |
| CN107219999B (en) | 2013-08-31 | 2020-06-26 | 华为技术有限公司 | Data migration method of memory module in server and server |
| EP3206127B1 (en) | 2013-11-22 | 2019-03-06 | Huawei Technologies Co., Ltd. | Method, computer, and apparatus for migrating memory data |
| EP3229140B1 (en) | 2013-12-02 | 2019-02-20 | Huawei Technologies Co., Ltd. | Data processing device and data processing method |
| CN108572926B (en) * | 2017-03-13 | 2022-02-22 | 阿里巴巴集团控股有限公司 | Method and device for synchronizing caches of central processing units |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6389556B1 (en) * | 1999-01-21 | 2002-05-14 | Advanced Micro Devices, Inc. | Mechanism to prevent data loss in case of a power failure while a PC is in suspend to RAM state |
| US6546472B2 (en) * | 2000-12-29 | 2003-04-08 | Hewlett-Packard Development Company, L.P. | Fast suspend to disk |
| CN1570874A (en) * | 2003-07-17 | 2005-01-26 | 鸿富锦精密工业（深圳）有限公司 | Single memory automatic staring back-up system and method |
-
2005
- 2005-09-30 CN CNB2005101125077A patent/CN100399288C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6389556B1 (en) * | 1999-01-21 | 2002-05-14 | Advanced Micro Devices, Inc. | Mechanism to prevent data loss in case of a power failure while a PC is in suspend to RAM state |
| US6546472B2 (en) * | 2000-12-29 | 2003-04-08 | Hewlett-Packard Development Company, L.P. | Fast suspend to disk |
| CN1570874A (en) * | 2003-07-17 | 2005-01-26 | 鸿富锦精密工业（深圳）有限公司 | Single memory automatic staring back-up system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1940876A (en) | 2007-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100399288C (en) | Memory backup device and method | |
| US20190205222A1 (en) | High performance persistent memory | |
| US10885004B2 (en) | Method and apparatus to manage flush of an atomic group of writes to persistent memory in response to an unexpected power loss | |
| EP3531292B1 (en) | Methods and apparatus for supporting persistent memory | |
| US9727462B2 (en) | Runtime backup of data in a memory module | |
| US5574874A (en) | Method for implementing a checkpoint between pairs of memory locations using two indicators to indicate the status of each associated pair of memory locations | |
| US20030084245A1 (en) | Storage control unit with a volatile cache and a non-volatile backup cache, for processing read and write requests | |
| US20080195807A1 (en) | Destage Management of Redundant Data Copies | |
| US10445236B2 (en) | Method to consistently store large amounts of data at very high speed in persistent memory systems | |
| CN101923499A (en) | Techniques to perform power fail-safe caching without atomic metadata | |
| US9507534B2 (en) | Home agent multi-level NVM memory architecture | |
| US20190050344A1 (en) | Techniques for an all persistent memory file system | |
| CN106104515A (en) | Utilize File system design and the fault recovery method of nonvolatile memory | |
| WO2018004928A1 (en) | Techniques for write commands to a storage device | |
| JPH04102948A (en) | Data processing system and method | |
| CN102800357B (en) | Procedure code is written into and access method, Memory Controller and memorizer memory devices | |
| US20190324868A1 (en) | Backup portion of persistent memory | |
| JP2006099802A (en) | Storage controller, and control method for cache memory | |
| US11157342B2 (en) | Memory systems and operating methods of memory systems | |
| CN102521173A (en) | Method for automatically writing back data cached in volatile medium | |
| CN116472512A (en) | Enhanced endurance of a System On Chip (SOC) | |
| US20160210234A1 (en) | Memory system including virtual cache and management method thereof | |
| US20150113244A1 (en) | Concurrently accessing memory | |
| US20200264681A1 (en) | Power management for partial cache line sparing | |
| US11734184B2 (en) | Effective avoidance of line cache misses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080702 Termination date: 20200930 |