CN100518272C - Solid-state high-definition videocorder - Google Patents

Abstract

Said invented solid state high definition videocorder includes high definition AV coder/decoder, TV, AV input circuit, video decoder, audio amplification and audio ADC, digital video and digit audio input, USB OTG interface and controller, IEEE 1394 interface and controller, DV decoder, DDR SDRAM circuit, solid memory, remote controller, press key and display circuit, audio DAC, audio filtering, digit audio and digital video output, video filtering, AV output circuit and power supply.

Description

Solid-state high-definition videocorder

Technical field

The present invention relates to video tape recorder, mainly be meant a kind of solid-state high-definition videocorder.This video tape recorder both can be used as family's audio-video product, can be used as vehicle-mounted audio-video product again, also can be used as the palm machine, and amusement, news interview, anti-thefting monitoring, traffic monitoring, public security scouting etc. are provided, belong to the 4th generation video tape recorder.

Background technology

At present, video tape recorder has experienced three generation products, and the first generation is called for short VTR (Video Tape Recorder) video tape recorder, and it mainly is made up of machine driven system, servo system and vision signal and audio signal processing; Its shortcoming is a complicated in mechanical structure, signal record and play the employing contact, after repeatedly using, the broadcasting effect and will reduce of video tape.In addition, its machine driven system is made up of DM drum module and capstan drive unit, tape transmission device, tep reel mechanism and machine control unit, complex structure, failure rate height, costs an arm and a leg.

The second generation is VCD optical disk recorder optical disk recorder with what the MPEG1 codec chip was made, also is VCD DiscRecorder, is called for short VDR..Popularizing and making a price reduction along with DVD afterwards, optical disk recorder with the manufacturing of MPEG2 codec chip has appearred, it is DVD optical disk recorder, also be DVD Disc Recorder, be called for short DDR, it is on the basis of DVD Player, but increased the function of imprinting, but movement adopt imprinting movement, as long as with CD-RW, CD+RW, DVD-R/RW and DVD+R/RW video disc, can imprinting.Master chip adopts the DVD codec, the employing single-chip that has, i.e. and encoding and decoding are synthesized together, and have plenty of the encoder branch and come and do.Second generation video tape recorder has many weak points, and is big as (1) volume, complex structure; (2) circuit complexity, element is many; (3) power consumption is big, and the power consumption of complete machine normal play is generally greater than 30W, and power consumption is bigger during record; The phenomenon that crashes appears in (4) poor stability sometimes during imprinting; (5) owing to be not easy to carry, its many purposes have been limited; (6) shaven head is easily aging, and working life is short.

Becoming increasingly abundant and upload lifting with speed of download along with Internet resources, third generation DVR has appearred, also be HDD DVD Recorder, be HDR, the basic principle of its encoding and decoding is just the same with optical disk recorder, just casts aside movement and servo theory, with hard disk as Storage Media, it is servo to replace DVD ROM movement and DVD, and its benefit is: (1) power consumption reduces, and the power when operate as normal is less than 5W; (2) volume-diminished, weight saving: optical disk recorder is a box-type, and volume is big, and heaviness, DVR are pockets, and volume is little, and is light; (3) conveniently use and carry; (4) without video disc, information is from various digital products such as internet resource, PC, TV, AV CD player, video camera, digital cameras.The weak point of third generation video tape recorder is that volume is bigger than normal, and the mechanical structure of hard disk is still very complicated, motor high speed rotating during work, and heating is serious.

Summary of the invention

The purpose of this invention is to provide a kind of solid-state high-definition videocorder, should belong to the 4th generation product, be characterized in mainly adopting high definition AV codec and solid-state memory, with the solid-state storage medium as medium, fully phase out the mechanical type medium, accomplished volume littler (can accomplish also littler than cigarette case), weight is lighter, and is with better function.And by with the combining of products such as mobile phone, TV, security protection, wireless network card, game machine, MP3, digital camera, e-dictionary and PDA, realized having the multimedia palm machine of extensive use.

Realize that technical scheme of the present invention is: this video tape recorder comprises high definition AV codec, the TV tuner, the AV input circuit, Video Decoder, audio frequency amplifies and audio A C, digital video and digital audio input, USB OTG interface and controller, IEEE1394 interface and controller, the DV decoder, DDR SDRAM circuit, solid-state memory, remote controller, button and display circuit, audio frequency DAC, audio frequency filtering, digital audio and digital video output, video filtering, parts such as AV output circuit and power supply; Its primary structure is described

The decoded portion of high definition AV codec comprises the solid-state memory interface, memory bus, the bit stream input interface, bit stream processor, the direct access controller, audio decoder DSP, dual HD video decoder, cpu bus, the HOST interface, the ROM interface, kernel, MIPS CPU, pci interface, sdram interface, the external AV input interface, audio process, the 2D bit processor, the video format conversion video-stream processor, video encoder, the SD digital to analog converter, high definition digital to analog converter and serial I/O memory card interface, I ²The perimeter interface that C interface, timer and UART etc. form.

The coded portion of high definition AV codec comprises host interface, microprocessor controller, timer and GPIO, phase-locked loop, cpu bus, audio frequency analog to digital converter, rate conversion device, audio frequency DSP kernel, Video Decoder, digital video input processor controls, HD video encoder/transducer, direct memory access (DMA) controller, sdram interface, sequential flow/program flow MUX etc.

Solid-state memory comprises the power down not memory integrated circuit or the storage card of obliterated data, and it is connected with high definition AV codec.

Described RF IN recording signal flows to high definition AV codec through TV tuner and channel decoder, and wherein the TV tuner can receiving digital television and HDTV (High-Definition Television) signal, according to different countries and regions, can adopt different standards; And as the input circuit of realizing RF IN recording function.

Described AV IN vision signal converts digital signal to through Video Decoder, audio frequency amplification and audio A C respectively and flows to high definition AV codec, the module that AV IN Video Decoder, audio frequency amplify and audio A C is constituted wherein, its objective is the analog audio-video conversion of signals is become digital signal and video formats conversion, so that record.

Described digital video signal and digital audio and video signals flow to high definition AV codec through digital video module and digital audio module respectively, wherein the direct receiving digital television signal of digital video and digital audio input module.

Described USB OTG interface connects high definition AV codec through the USB controller, its can be not by PC directly and other USB device upload and data download.

Described IEEE1394 interface via controller and DV decoder connect high definition AV codec, and it can be directly and device talk such as video camera, and realize the digital recording function.

Described DDR SDRAM Synchronous Dynamic Random Access Memory connects high definition AV codec, it can realize the function of the Code And Decode of HD video and audio frequency, under play mode, both can be by decoding broadcast line by line, also can play by the interlacing decoding, its resolution is respectively 720P, 1080P and more than the 1080I.

Described high definition AV codec is exported high tone quality high definition AV through audio frequency DAC conversion and audio frequency filtering, digital audio output, digital video output, video filtering respectively, and wherein the AV output circuit can be exported high tone quality audio-video signal and high definition video signal.

Described solid-state memory comprises FLASH memory or EPROM or E2PROM or ferroelectric memory or MS card or SMC or XD card or SD card or MMC or CF card etc.

Described remote controller and button display circuit can be realized infrared remote control, feature operation and show.

The beneficial effect that the present invention has:

1. low in energy consumption, the power consumption that adopts pocket is less than 1W;

2. volume is little, and is in light weight, easy to carry;

3. high definition, resolution is respectively 720P, 1080P and more than the 1080I;

4. shock resistance is strong;

5. upload with speed of download fast;

6. many interfaces, function is strong, practicality.

Description of drawings

Fig. 1 is a complete machine basic structure block diagram of the present invention.

Fig. 2 is the decoded portion internal structure block diagram of high definition AV codec among Fig. 1.

Fig. 3 is the coded portion internal structure block diagram of high definition AV codec among Fig. 1.

Fig. 4 is All-in-One card circuit theory diagrams.

Fig. 5 is DDR SDRAM circuit theory diagrams.

Fig. 6 1394 controller circuitry schematic diagrams.

Fig. 7 is a FLASH memory circuitry schematic diagram.

Fig. 8 is the high-definition media interface circuit theory diagrams.

Fig. 9 is high definition AV codec master chip U21A circuit theory diagrams.

Figure 10 is high definition AV codec master chip U21B circuit theory diagrams.

Figure 11 is high definition AV codec master chip U21C circuit theory diagrams.

Figure 12 is high definition AV codec master chip U21D circuit theory diagrams.

Figure 13 is Video Decoder U28A circuit theory diagrams.

Figure 14 is Video Decoder U28B circuit theory diagrams.

Embodiment

The present invention will be further described below in conjunction with accompanying drawing:

A. operation principle

Fig. 4 is an All-in-One card circuit.For the pin function of the various cards of clear reflection, the figure of various cards is drawn respectively, adopt the All-in-One deck to do but be actually, cards commonly used such as it can the compatible to SD card, MMC, MS card, XD card, CF1 card, CF2 card, SMC card and MICRODRIVER.Basically can satisfy users' needs.

Fig. 5 is a DDR SDRAM circuit.U8 and U9 are 16M * 16DDR SDRAM.As preferably, its model is K4H561638B.This circuit cooperates master chip as data buffer, finishes the AV codec functions.

Fig. 6 is 1394 controller circuitrys.The model of U4 is TSB41AB1, it is IEEE1394A-2000 single port cable transceiver/arbiter, the effect of this circuit is to make solid-state high-definition videocorder carry out communication with the equipment with IEEE1394 interface, compatible these the three kinds of forms of 100/200/400MbPS of its transfer rate.

Fig. 7 is the FLASH memory circuitry.Be mainly used to store the file that to record and to play.As preferably, U11 ~ U14 adopts NAND FLASH, and its model all is K9KDG08UOD, and capacity is respectively 128Gb (being 16GB), and total capacity is 64GB.The described NAND FLASH of this circuit has three big features:

(1). 8 bus EMD[0:7 that carry out communication with master chip] can transmit data, order and address;

(2). be subjected to the signal of master chip control to have 7, be described below respectively:

R/XB is preparing state/busy output signal.It indicates the operating state of this device.When low level, its instruction program, deletion or read operation is underway at random.When high level, its indicating device is in preparing state.

EM-RD reads to enable input signal.It is used to control serial data output and when effective driving data enters input/output bus.

NAND-CE1～NAND-CE4 is respectively that the sheet choosing of U11～U14 enables input signal, and low level is effective, and its effect is to select corresponding FLASH device.When that FLASH busy the time, the high level of corresponding chip selection signal is out in the cold, and when program or deletion action, this FLASH can not turn back to the preparing state pattern.

NAND-CLE is the command latch enable input signal.It is used for the active path that control command is delivered to command register.When high level is effective, on the NAND-XWE signal, locked into command register by the order of I/O port.

NAND-ALE is that address latch enables input signal.It is used for the active path that control address is latched into the home address register.Under the situation that is accompanied by the NAND-ALE high level, the address is latched on the rising edge of NAND-XWE.

NAND-XWE writes to enable input signal.It is used for control and writes I/O port.Order, address and data latching are at the rising edge of NAND-XWE pulse.

NAND-XWP is a write protect signal.During power supply transition, NAND-XWP provides inadvertent and writes/delete protection.When the NAND-WP low level was effective, internal high voltages produced and resets.When LOCKPRE is a logic high, when NAND-XWP was logic low, the place module entered lock-out state.

(3). the NANDFLASH capacity difference that is adopted, but encapsulation and pin function are identical, like this, substitute just very convenient.

Fig. 8 is high-definition media interface (HDMI) circuit.CON15 is the HDMI socket.High definition output can be supported following video format:

(1).1280×720P@59.94/60Hz；

(2).1920×1080I@59.94/60Hz；

(3).1280×720P@50Hz；

(4).1920×1080I@50Hz。

HP-DET is the plug detection signal, and HDMI-SDA and HDMI-SCL are the I of HDMI ²The C bus.HDMI-SDA is a serial data transmitted in both directions signal, and HDMI-SCL is a serial clock signal.TX-C-and TX-C+ are reflector clock difference pairing signals.TX0-and TX0+, TX1-and TX1+, TX2-and TX2+ are respectively emitter data difference pairing signals, "+" represents signal in the same way, "-" expression reverse signal.

Fig. 9-the 11st, master chip and peripheral circuit thereof, it finishes the encoding and decoding work of looking audio frequency, and each circuit is controlled, and it is an acp chip.Only conduct a kind of selection wherein, its model is HPR3889, certainly, other chip that can select to have its function fully.

Other circuit description

The audio codec circuit, the U2 of the main chip of this circuit, its model is WM8776, it is 24 192KHz stereo coding/decoding devices, has 5 passage I/P multiplexers.Its main effect is: (1).Change audio analog signals into digital signal, be convenient to storage.(2)。With digital signal transition is analog signal, is convenient to play.Its inside is made up of input mixer, amplifying circuit, stereo ADC, automatic electric-level control, audio interface and digital filtering, stereo DAC, low pass filter and Earphone Amplifier etc.

The audio frequency and video input circuit.The model of U3 is 74LCX257, and it is a logical device.U4 is that model is MC14052B～D, and it is demultiplexer and two 4 tunnels analogy multiplexer.U5 is 24 stereo ADC of 96KHz, and its main effect is that stereo analog signal conversion is become digital signal.

Audio output circuit.From CON7A output, export from fiber-optical socket CON9 and coaxial socket CON8 respectively after shaping by digital audio SPDIF signal behind low pass filter for analog stereo signal.

The DV decoder circuit.The model of U10 in the circuit is PDI1394L40, and it is the IEEE1394 controller.

Button and display circuit.VFD1 is a fluorescent display screen, and its model is GTD-637B.U16 is VFD display driver and control integrated circuit, and its model is PT6317.

U17 is real-time clock/perpetual calendar integrated circuit, and its model is PCF8563T or M41T80, and it comprises 16 and has 1 eight bit register, 1 monolithic 32 that has 1 integrated capacitance that increases the address automatically.The oscillator of 768KHz, 1 I that the frequency drives of source clock, 1 programmable clock output, 1 timer, 1 alarm, 1 low voltage detector and 1 400KHz are provided for real-time clock control (RTC) ²The C bus interface.The model of U18 is HR3800, and it is that infrared remote control receives head.The model of U19 is AT24C04, and it is E ²PROM.U20 is the battery of 3V, provides the energy to guarantee the long-term correct timing of clock.

The most basic circuit of power supply.Power supply is imported from supply socket CON18 from the 12V power supply.U22 is the DC/DC integrated circuit, and as preferably, its model is LM2576S, is used to produce VCC voltage, and U23 is the voltage adjuster of low-voltage difference, and as preferably, its model is AMS1117, is used to produce VDD33 voltage.U24 is an integrated regulator, and as selection, its model is NJM78L05, be used to produce STBY voltage (+5V).U25 is the DC/DC voltage adjuster, and as preferably, its model is LP3965ES, is used to produce 1.8V voltage (P1V8).U26 also is the DC/DC voltage adjuster, and as preferably, its model is LP3964, is used to produce 2.5V voltage (P2V5).

Television high frequency head circuit.Only as selection, TUN1 is a TV TUNER module, is TMDZ9-731A with reference to model.The master chip control circuit passes through I ²C bus (IDC-SDA and IDC-SCL) is controlled it, and the model of amplifier U27 is LM393, by AFT-OUT, produces the output of tuner detection signal.

Usb circuit, CON20 are USB socket, and USB-DO-and USB-DO+ are that USB differential data input/output signal is right.Adopt USB OTG high-speed interface mode, speed can reach 480MbPS.

The video decode circuit.The effect of U28 is that analog video signal is changed at digital video signal, and video format is carried out conversion.As a kind of selection, its model is TVP5146.Y5, R198, C209 and C210 and U28 internal oscillator module constitute 14.The 31818MHz oscillating circuit.

Video output circuit can be exported composite video signal, S vision signal, YUV signal or rgb signal.On each passage, all form by clamp circuit about video filtering circuit and the diode.In addition, terminal has: CON22 is the composite video lead-out terminal, and CON23B is the S terminal, and CON24 is RCA 3 * 1 terminals.

B. annexation

1. being connected of master chip and SDRAM, see Table 1

Table 1 master chip U21 is connected with SDRAM U8 and U9's

Memonic symbol	Title	Explanation
			SDRAM_A[15..0]	16 bit address buses	Data message is deposited in position, so that deposit and call, it is to be input to the address register of SDRAM and mode register from master chip.
SDRAM_DQ[31..00]	32 I/O data/address buss	Data transmit by 32 bit patterns, and data are two-way, both can be input to the multiplexed data input/output (i/o) buffer of SDRAM from master chip, also can be input to master chip from SDRAM, and the main content that transmits is a data message.
			SDRAM_CLK0 SDRAM_CLK#0 SDRAM_CLK1 SDRAM_CLK#1	System clock	All other input be with reference to the rising edge clock on the corresponding SDRAM.
SDRAM-CLKE	The clock enable signal	The control internal clock signal, high level is effective.When not activating, SDRAM is one of state in the middle of low-power consumption, time-out or self-refresh.
			SDRAM-RAS#	The row address strobe signal	Low level is effective, and this signal is the timing register module that is input to SDRAM from master chip.
SDRAM-CAS#	The column address strobe signal	Low level is effective, and this signal is the timing register module that is input to SDRAM from master chip.
			SDRAM-CS0	Chip enable signal	Low level is effective, and this signal is the timing register module that is input to SDRAM from master chip.
SDRAM-WE#	Write enable signal	Low level is effective, and this signal is the timing register module that is input to SDRAM from master chip.Again from timing register output LWE signal controlling i/o controller.When SDRAM-WE# is low level, allow to write data
			SDRAM-DQM0 SDRAM-DQM1 SDRAM-DQS0 SDRAM-DQS1 SDRAM-DQM2 SDRAM-DQM3 SDRAM-DQS2 SDRAM-DQS3	Data I/O shielding	At reading mode, be used to control output buffer; At WriteMode, be used to shield dateout, they are controlled by master chip.

2. master chip and FLASH memory is connected

Model at FLASH memory U11～U14 employed in figure 7 all is K9KDG08UIM, their capacity is respectively 16GB, and total capacity is 64G, and their main effect is a store various kinds of data information, they are to store by the mode of file, and the annexation of they and master chip sees Table 2

Table 2 master chip U21 is connected with FLASH memory U11～U14's

Memonic symbol	Title	Explanation
			EMD[0:7]	Order, address and data I/O	During read operation, dateout. when the FLASH memory does not have selected or output when being cancelled, the I/O mouth suspends and is high-impedance state.
EM-RD	Read enable signal	Be used to control serial data output. when activating solid-state memory, data are on the I/O bus.
			NAND-XCE1 NAND-XCE2 NAND-XCE3 NAND-XCE4	Sheet selected control system signal	NAND-XCE1～NAND-XCE4 is respectively applied for and selects U11～U14, and low level is effective.
NAND-ALE	Address latch enables	It is used for the active path of control address to the home address register.When ALE was high level, the address was locked in the rising of NAND-XWE

		Along last.
			NAND-XWE	Write enable signal	It is used for control and writes the I/O mouth, order. and address and data are latched on the rising edge of NAND_XWE pulse. and when output was effective, NAND_XWE must keep high level.
NAND-XWP	Write protect signal	During power source conversion, it provides inadvertent and writes/delete protection.When the XWP pin was effective low level, the internal high voltages generator resetted.
			NAND-CLK	Clock signal	At synchronous reading mode, this signal is used for FLASH and system bus frequency is synchronous.
R/XB	Preparing state/busy attitude conversion	The state of R/XB output indication FLASH memory operation.When low level, its instruction program. deletion or at random read operation be in process, and turn back to high-impedance state and finish.When the FLASH memory did not have selected or exports cancellation, it was out to leak output, and is not suspended to high-impedance state.

3. master chip and All-in-One card is connected

(1). master chip U21 is connected with CF card CON14's, sees Table 3

Table 3

Memonic symbol	Direction	Describe
			CF-D[00:15]	Two-way	16 bit data bus
CF-A[00:10]	U21 is to CON14	11 bit address buses
			CF-WP/IOIS16	CON14 is to U21	Write protect signal
CF-CHK1 CF-CHK2	CON14 is to U21	Detection signal
			CF-CE2	U21 is to CON14	The card enable signal
CF-VS1 CF-VS2	CON14 is to U21	Voltage detection signal
			CF-IORD	U21 is to CON14	The I/O RS
CF-WE	U21 is to CON14	Write enable signal
			CF-RDY/BSY /IREQ	CON14 is to U21	Preparing state/busy signal/request signal
CF-CSEL	U21 is to CON14	Master slave mode is selected
			CF-RESET	U21 is to CON14	Reset signal, high level is effective
CF-WAIT	CON14 is to U21	Waiting signal
			CF-INPACK	CON14 is to U21	The input identification signal
CF-REG	U21 is to CON14	Register type is selected
			CF-BVD1 CF-BVD2	Two-way	The battery voltage detection signal

(2). master chip is connected with the SD/MMC/MS/SMC/XD card

This is similar to the FLASH memory, sees Table 4

Table 4 master chip U21 is connected with the SD/MMC/MS/SMC/XD card

Memonic symbol	Direction	Explanation
			SMC[0:7]	Two-way	Order, address and data I/O
SMC-RE	Master chip is to card	Read enable signal
			SMC-ALE	Master chip is to card	Address latch enables
SMC-WE	Master chip is to card	Write enable signal
			SMC-WP	Master chip is to card	Write protect signal
SMC-R/B	Master chip is to card	Preparing state/busy attitude conversion

SMC-CMD	Master chip is to card	Command signal
			SMC-CHK	Snap into master chip	Detection signal
SMC-CLK	Master chip is to card	Clock signal
			SMC-DAT	Two-way	The serial data I/O

4. being connected of master chip and 1394 controllers, see Table 5

Table 5 master chip U21 is connected with 1394 controller U10's

5. being connected of master chip and HDMI, see Table 6

Table 6 master chip U21 is connected with HDMI connector CON15's

6. being connected of master chip and Video Decoder, see Table 7

Table 7 master chip U21 is connected with Video Decoder U28's

Memonic symbol	Direction	Explanation
			VI-D[9..0]	U28 is to U21	The digital video signal data bus
SCL	U21 is to U28	Serial clock signal
			SDA	Two-way	Serial data signal
E5-GPIO×6	U21 is to U28	General I/O port is as interrupt signal
			E5-GPIO×7	U21 is to U28	General I/O port is as reset signal
VI-CLK0	U28 is to U21	Linear lock given data clock
			VI-VSYNC	U28 is to U21	Field sync signal

Part english abbreviation speech is explained: the ME engine mechanism; DCT/QIQ/IDCT discrete cosine transform/quantification inverse quantization/inverse discrete cosine transform; The input of VBI variable-ratio bit stream; The real-time bit stream control of TBC; The digital ratio of NR; The OTG online communication; The SDRAM synchronous DRAM; The DSP digital signal processor; TUNER electronic tuning unit (tuner); RISC reduced instruction set computer calculator; The UART UART Universal Asynchronous Receiver Transmitter; The HOST main frame; The grand integrated circuit treatment system of MIPS; The GPIO general I/O port; The MUX multi-channel modem; The LSI large scale integrated circuit.

Specify

The present invention can make pocket, the family expenses formula with vehicular, and can increase or delete function according to requirement of client, all belong within the protection range of this patent.The basic concept of this patent is to adopt solid-state memory to make the video tape recorder of high definition as medium.

Along with improving constantly of semiconductor process techniques, the capacity of memory is done bigger and bigger, and valency appearance ratio will be more and more lower.Now, the capacity of FLASH memory can be accomplished 16G, soon, the realization of 70nm, 60nm and 50nm (nanometer) technology and stack technology, the capacity of FLASH memory can be accomplished 32G, 64G, 128G ... just no problem.Therefore, I propose invention solid-state high-definition videocorder (Solid State HD Recorder, be SSHDR), in time, meet the era development trend. Here it is the 4th generation video tape recorder. as medium, volume reduces greatly with the solid-state storage medium for it, can accomplish also littler than cigarette case, and it is in light weight, powerful.Along with reaching its maturity of technology, products such as mobile phone, TV, security protection, wireless network card, game machine, MP3, digital camera, e-dictionary and PDA may be combined, and microminiaturized, be exactly very practical new product.。。。。Multimedia palm machine.

Claims (9)

1. a solid-state high-definition videocorder comprises high definition AV codec, TV tuner, AV input circuit, Video Decoder, audio frequency amplification and audio A C, digital video and digital audio input, USB OTG interface and controller, IEEE1394 interface and controller, DV decoder, DDR SDRAM circuit, solid-state memory, remote controller, button and display circuit, audio frequency DAC, audio frequency filtering, digital audio and digital video output, video filtering, AV output circuit and power supply; It is characterized in that as described below

The decoded portion of high definition AV codec comprises the solid-state memory interface, memory bus, the bit stream input interface, bit stream processor, the direct access controller, audio decoder DSP, dual HD video decoder, cpu bus, the HOST interface, the ROM interface, kernel, MIPS CPU, pci interface, sdram interface, the external AV input interface, audio process, the 2D bit processor, the video format conversion video-stream processor, video encoder, the SD digital to analog converter, the high definition digital to analog converter is by serial I/O memory card interface, I ²The perimeter interface that C interface, timer and UART form;

The coded portion of high definition AV codec comprises host interface, microprocessor controller, timer and GPIO, phase-locked loop, cpu bus, audio frequency analog to digital converter, rate conversion device, audio frequency DSP kernel, Video Decoder, digital video input processor controls, HD video encoder/transducer, direct memory access (DMA) controller, sdram interface, sequential flow/program flow MUX;

Solid-state memory comprises the power down not memory integrated circuit or the storage card of obliterated data, and it is connected with high definition AV codec;

RF IN recording signal flows to high definition AV codec through TV tuner and channel decoder.

2. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described AV IN vision signal converts digital signal to through Video Decoder, audio frequency amplification and audio A C respectively and flows to high definition AV codec.

3. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described digital video signal and digital audio and video signals flow to high definition AV codec through digital video module and digital audio module respectively.

4. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described USB OTG interface connects high definition AV codec through the USB controller.

5. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described IEEE1394 interface via controller and DV decoder connect high definition AV codec.

6. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described DDR SDRAM Synchronous Dynamic Random Access Memory connects high definition AV codec.

7. solid-state high-definition videocorder as claimed in claim 1, it is characterized in that described high definition AV codec respectively through audio frequency DAC conversion and audio frequency filtering, digital audio output, digital video export, video filtering, export high tone quality audio frequency and high definition video respectively.

8. solid-state high-definition videocorder as claimed in claim 1 is characterized in that described solid-state memory comprises FLASH memory or EPROM or E2PROM or ferroelectric memory or MS card or SMC or XD card or SD card or MMC or CF card.

9. solid-state high-definition videocorder as claimed in claim 1 is characterized in that

Master chip U21 is connected with SDRAM U8 and U9's, and its corresponding interface comprises SDRAM_A[15..0], SDRAM_DQ[31..00], SDRAM_CLK0, SDRAM_CLK#0, SDRAM_CLK1, SDRAM_CLK#1, SDRAM-CLKE, SDRAM-RAS#, SDRAM-CAS#, SDRAM-CS0, SDRAM-WE#, SDRAM-DQM0, SDRAM-DQM1, SDRAM-DQS0, SDRAM-DQS1, SDRAM-DQM2, SDRAM-DQM3, SDRAM-DQS2, SDRAM-DQS3;

Master chip U21 is connected with FLASH memory U11-U14's, and its corresponding interface comprises EMD[0:7], EM-RD, NAND-XCE1, NAND-XCE2, NAND-XCE3, NAND-XCE4, NAND-ALE, NAND-XWE, NAND-XWP, NAND-CLK, R/XB;

Master chip U21 is connected with the All-in-One card, and wherein the connecting interface with CF card CON14 comprises CF-D[00:15], CF-A[00:10], CF-WP/IOIS16, CF-CHK1, CF-CHK2, CF-CE2, CF-VS1, CF-VS2, CF-IORD, CF-WE, CF-RDY/BSY/IREQ, CF-CSEL, CF-RESET, CF-WAIT, CF-INPACK, CF-REG, CF-BVD1, CF-BVD2; Comprise SMC[0:7 with the connecting interface of SD/MMC/MS/SMC/XD card], SMC-RE, SMC-ALE, SMC-WE, SMC-WP, SMC-R/B, SMC-CMD, SMC-CHK, SMC-CLK, SMC-DAT;

Master chip U21 is connected with 1394 controller U10's, and its corresponding interface comprises PHY-DQ[0..7], PHY-CTL0, PHY-CTL1, PHY-CREQ, PHY-50MHZ, LINK-LPS, AV2-D[0..7], LINK-D[0..7], LINK-RSTN, HIF-DRD-N, HIF-INT1-N, HIF-DWR-N, HIF-CS1-N, HIF-A[0..15], HIF-D[0..7];

Master chip U21 is connected with HDMI connector CON15's, and its corresponding interface comprises HP_DET, HDMI_SDA, HDMI_SCL, TX-C-, TX-C+, TX0-, TX0+, TX1-, TX1+, TX2-, TX2+;

Master chip U21 is connected with Video Decoder U28's, and its corresponding interface comprises VI-D[9..0], SCL, SDA, E5-GPIO * 6, E5-GPIO * 7, VI-CLK0, VI-VSYNC.

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