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專利

  1. 進階專利搜尋
公開號CN101477829 B
出版類型授權
申請書編號CN 200810184950
發佈日期2012年5月23日
申請日期2001年11月26日
優先權日期2000年12月20日
其他公開專利號CN1734668A, CN1734668B, CN1828766A, CN1832028A, CN1905059A, CN1905059B, CN100530417C, CN100530418C, CN101452737A, CN101452737B, CN101477829A, CN101477830A, CN101582290A, CN101582290B
公開號200810184950.9, CN 101477829 B, CN 101477829B, CN 200810184950, CN-B-101477829, CN101477829 B, CN101477829B, CN200810184950, CN200810184950.9
發明人山崎雅文, 川崎健一, 松崎康郎, 鎌田心之介, 铃木孝章
申請者富士通半导体股份有限公司
匯出書目資料BiBTeX, EndNote, RefMan
外部連結:  中華人民共和國國家知識產權局, 歐洲專利局
Multiport memory based on dynamic random access memory core
CN 101477829 B
摘要
The present invention provides a multi-port memory based on a plurality of dynamic random access memory cores. A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
聲明所有權(10)  原文語言:中文
1.半导体存储器件,包括:数量为N的多个外部端口,每个外部端口都接收指令; 数量为N的多条总线,它们与各个外部端口对应; 多个存储块,它们与N条总线连接,所述存储块包括DRAM存储单元阵列; 一个地址比较电路,它比较由输入到N个各外部端口中的指令存取的地址;和一个判优电路,它确定当所述地址比较电路根据地址比较结果检测到同一个存储块的存取时,执行存取同一个存储块的指令中的哪一个或哪几个和不执行存取同一个存储块的指令中的哪一个或哪几个。 A semiconductor memory device, comprising: a number of the plurality of N external ports, each port receives an external instruction; N the number of multiple buses, they correspond to the respective external ports; a plurality of memory blocks, they N buses connection, the storage block includes DRAM memory cell array; address an address comparator circuit comparing the input into N respective external ports accessible instruction; and an arbiter, which determines when the address comparator circuit according to address comparison result is detected with an access memory block, perform access the same memory block of instruction in which one or a few, and the instruction does access the same memory block in which one or a few .
2.权利要求1所述的半导体存储器件,其中所述判优电路响应不执行给定指令的确定结果,输出指示不执行给定指令的信号。 The semiconductor memory device according to claim 1, wherein the arbiter is not performed in response to the determination result of the instruction, the output is not performed to the signal indicative of the instruction.
3.权利要求2所述的半导体存储器件,其中从与给定指令对应的一个端口输出指示不执行给定指令的信号。 The semiconductor memory device according to claim 2, wherein, in which a given instruction from a port corresponding to the signal output indicates that no execution of the instruction.
4.权利要求1所述的半导体存储器件,其中所述半导体存储器件包括一个刷新电路, 它确定刷新存储单元的定时,其中在第一模式中,响应输入到N个外部端口中的至少一个端口的刷新指令刷新存储单元,在第二模式中,在所述刷新电路指示的定时刷新存储单元。 At least one port semiconductor memory device according to claim 1, wherein said semiconductor memory device includes a refresh circuit which defines a timing of refreshing the memory cell, wherein in a first mode in response to input of the N external ports The refresh command to refresh the memory cell, in the second mode, the memory cells are refreshed at the timing indicated by the refresh circuit.
5.权利要求4所述的半导体存储器件,其中当所有N个外部端口都处于去激活状态中时进行第二模式。 The semiconductor memory device according to claim 4, wherein the second mode when all the N external ports are in the deactivated state.
6.权利要求4所述的半导体存储器件,进一步包括一个产生要被刷新的地址的刷新地址计数器,其中所述刷新地址计数器响应从所述判优电路发出的刷新指令对地址进行计数。 The semiconductor memory device according to claim 4, further comprising an address counter generates a refresh address to be refreshed, wherein the refresh address counter in response to a refresh command issued from the arbiter of the address were counted.
7.权利要求1所述的半导体存储器件,其中所述存储块中的每一个都包括一个控制电路,所述控制电路响应与所述控制电路的存储块对应的在一条所述总线中的地址检测结果,从该条总线取得指令信号。 The semiconductor memory device according to claim 1, wherein said memory blocks each comprising a control circuit, said control circuit is responsive to the control circuit and the memory blocks in the corresponding one of said address bus test results, obtained command signal from which the bus.
8.权利要求7所述的半导体存储器件,其中所述存储块中的每一个都进一步包括一个总线选择装置,所述总线选择装置使所述该条总线与存储单元阵列连接。 The semiconductor memory device according to claim 7, wherein said storage block each further comprises a bus selecting means, said bus selector means and said memory cell array section bus connection.
9.权利要求1所述的半导体存储器件,其中N个外部端口中的每一个都包括: 一个电路,它将串行接收的数据作为并行数据提供给N条总线中的一条对应总线;和一个电路,它将从N条总线中的一条对应总线提供的并行数据作为串行数据输出到器件外部。 The semiconductor memory device according to claim 1, wherein the N external ports each comprising: a circuit that receives serial data as parallel data to the N buses corresponding to a bus; and an circuit which corresponds to the parallel data bus provides the N bus from one output as serial data to an external device.
10.权利要求9所述的半导体存储器件,其中输入到N个各外部端口的指令包括读指令和写指令,所述判优电路,响应将所述读指令输入外部端口的定时和将对于所述写指令的串行输入数据的最后一个数据项输入外部端口的定时,确定指令中的哪一个或哪几个要被执行和指令中的哪一个或哪几个不被执行。 The semiconductor memory device according to claim 9, wherein the input into the N respective external ports include a read instruction command and a write command, the arbitration circuit, in response to the read command input timing to the external port and the The last data item of said serial input data write command input timing of the external ports to determine instruction in which one or a few is to be executed and instruction in which one or a few is not executed.
說明  原文語言:中文

基于动态随机存取存储器核心的多端口存储器 Dynamic random access memory core of the multi-port memory

[0001] 本分案申请是基于申请号为01139358.0,申请日为2001年11月沈日,发明名称为“基于动态随机存取存储器核心的多端口存储器”的中国专利申请的分案申请。 [0001] The sub-text application is based on Application No. 01139358.0, filed in November 2001, Shen Day, titled "Dynamic random access memory core of the multi-port memory" divisional patent filed in China. 更具体说,本分案申请是基于申请号为200510083508. 3,申请日为2001年11月沈日,发明名称为“基于动态随机存取存储器核心的多端口存储器”的分案申请的再次分案申请。 More specifically, the sub-text application is based on Application No. 200510083508.3, filed in November 2001, Shen Day, titled "Dynamic random access memory core of the multi-port memory," the divisional application again points application filed.

技术领域 Technical Field

[0002] 本发明一般涉及半导体存储器件,特别是涉及装备有多个端口的半导体存储器。 [0002] The present invention generally relates to semiconductor memory devices, and more particularly to a plurality of ports equipped with a semiconductor memory. 背景技术 Background

[0003] 多端口存储器,它们是装备有多个端口的半导体存储器,可以分成不同的类型。 [0003] The multi-port memory, a semiconductor memory which is equipped with a plurality of ports, can be divided into different types. 当下文中使用术语“多端口存储器”时,它指的是具有多个端口的存储器,该多端口存储器允许从任何一个端口独立地存取到一个公共存储器阵列。 When the next used herein the term "multi-port memory," which refers to a memory having a plurality of ports, which allows multi-port memory independently from any port access to a common memory array. 这样一个存储器可以有一个A端口和一个B端口,并允许对于公共存储器阵列从与A端口链接的CPU和从与B端口链接的CPU 独立地进行读/写操作。 Such a memory may have an A port and a B port, and allows the public memory array from the A port links the CPU and independently from the CPU and the B port link read / write operations.

[0004] 一个多端口存储器装备有一个称为判优器的判优电路。 [0004] A multi-port memory is equipped with a called arbiter arbiter. 判优器确定从多个端口接收的各存取要求的优先权,存储器阵列的控制电路根据确定的优先权一个接一个的进行存取操作。 Arbiter determine the access requests received from the plurality of ports priority control circuit, the memory array is accessed one after the operation according to the determined priority. 例如,一个存取要求越早到达一个端口,就会给予该存取越高的优先权。 For example, an earlier access requests arrive at a port, the access will be given higher priority.

[0005] 在这种情形中,因为随机地从多个接口存取存储器阵列,所以在执行了读或写的存取操作后需要立即使存储器阵列复位,从而保证存储器阵列已经为下一次存取作好了准备。 [0005] In this case, you need to reset the memory array immediately because random access memory arrays from multiple interfaces, so the execution of the read or write access operations, to ensure that the memory array has been accessed for the next ready. 即,如果响应一个来自一个给定端口的存取使一条字线保持在一个选出的状态,和如一般在DRAM中使用的列存取操作中那样连续地动移各列地址以便读出连续的数据,则在该操作期间来自另一个端口的存取将一直等待着。 That is, if the response to an access from a given port of a word line is maintained in a selected state, and is as generally used in the DRAM access operations are successively shifted to read out the address of each column in a row The data, during this operation from another access port will be kept waiting. 因此,在每次读或写操作后需要立即使存储器阵列复位。 Therefore, after each read or write operation needs to reset the memory array immediately.

[0006] 常规地,已经典型地将一个SRAM用作一个多端口存储器的一个存储器阵列。 [0006] Conventionally, an SRAM has typically been used as a memory array of a multi-port memory. 这是因为一个SRAM允许高速随机存取,而且可以进行非破坏性读操作。 This is because an SRAM allows high-speed random access, and can be non-destructive read operation.

[0007] 在一个具有两个端口的多端口存储器中,例如,一个SRAM存储单元具有两组字线和各位线对。 [0007] In the multi-port memory having two ports, for example, a SRAM memory cell has two sets of word lines and bit line pairs. 一个端口用一组字线和一个位线对实施读/写操作,另一个端口用另一组字线和一个位线对实施读/写操作。 A port with a set of word line and a bit line for a read / write operation, the other port with another set of word line and a bit line for a read / write operations. 在这种方式中,能够从两个不同的端口独立地实施读/写操作。 In this way, it is possible to implement read from two different ports independently / write operations. 然而,因为当两个端口企图在同一时间将数据写入同一存储单元时不可能同时进行两个写操作,所以给予一个端口进行写操作的优先权,而给予另一个端口一个BUSY (忙碌) 信号。 However, since when the two ports attempt to write data at the same time in the same storage unit can not perform two write operations simultaneously, so give a write port priority accorded to another port a BUSY (busy) signal . 这称为一个BUSY状态。 This is called a BUSY state.

[0008] 当开发一个系统使它有改善的性能时,可以由该系统处理数据量也增加了。 [0008] When developing a system to have improved performance, and can also increase the amount of data processed by the system. 结果, 一个多端口存储器需要很大的容量。 As a result, a multi-port memory needs a large capacity. 然而,SRAM型多端口存储器有一个缺点,即存储单元的尺寸大。 However, SRAM-type multi-port memory has a drawback in that the size of the memory cell is large.

[0009] 为了消除这个缺点,在一个多端口存储器中采用一个DRAM阵列是可以理解的。 [0009] In order to eliminate this disadvantage, the use of a DRAM array in a multi-port memory is understandable. 为了得到比多端口SRAM高得非常多的电路密度,需要用于多端口存储器的一个DRAM存储单元以与一个典型的DRAM单元相同的方式只与一条字线和一条位线连接。 In order to obtain a very high number of circuit density than multi-port SRAM, a need for a DRAM memory cell with the multi-port memory of a typical DRAM cell is only connected to the same manner as a word line and a bit line. 如果以这样一种方式用DRAM元件制成存储块,则如果一个端口正在对一个给定的存储块执行读或写操作, 另一个端口就不能存取该存储块。 If in such a manner DRAM memory element is made of blocks, if a port is performing reading of a given block or write operation, the other port can not access the memory block. 这是因为在一个DRAM存储单元中只可以有一个非破坏性读操作。 This is because a DRAM memory cell can have only one non-destructive read operation. 即,当读信息时,不能选择在同一个存储块中的另一条字线直到在存储单元中这个信息被放大和恢复与一条字线和一条位线被预先充电为止。 That is, when reading the information, you can not select another word line in the same memory block in the storage unit until this information is amplified and restored and a word line and a bit line is pre-charged so far.

[0010] 因为这个原因,如果一个给定的端口存取一个正在被另一个端口存取的存储块, 则将检测出一个BUSY状态。 [0010] For this reason, if a given port accesses a memory block port being used by another access, it will detect a BUSY state. 只有当多个端口同时对同一个存储单元发出写要求时,在SRAM 型多端口存储器中才会出现BUSY状态。 Only when multiple ports simultaneously on the same storage unit issues a write request, the SRAM-type multi-port memory appears BUSY state. 另一方面,当多个端口同时对同一个存储单元发出任何类型的存取要求时,在DRAM型多端口存储器中会出现BUSY状态。 On the other hand, when multiple ports simultaneously send any type of access requests to the same memory cell in the DRAM-type multi-port memory appears BUSY state. 所以在DRAM型存储器中出现BUSY状态的概率非常大于在SRAM型存储器中出现BUSY状态的概率。 So the probability of BUSY state in DRAM-type memory is very larger than the probability of occurrence in the SRAM type memory BUSY state. 进一步,一旦处在BUSY状态中,DRAM型多端口存储器就会受到不能进行希望的操作或由于等待时间处理变得很慢这种问题的困扰。 Further, once in a BUSY state, DRAM-type multi-port memory will not be subjected to the desired processing operations or due to waiting time becomes very slow plagued this problem.

[0011] 然而,与SRAM型多端口存储器不同,DRAM型多端口存储器需要一个周期地进行的刷新操作以便保持存储的信息,从而必须采取某种措施保证适当的刷新定时。 [0011] However, unlike SRAM-type multi-port memory is different from the refresh operation of the DRAM-type multi-port memory needs a period to carry out in order to keep the information storage, so you must take some measures to ensure the proper refresh timing.

[0012] 因此,本发明的目的是提供能够消除特别与DRAM有关的各问题的DRAM型多端口存储器。 [0012] Accordingly, the object of the present invention is to provide a DRAM capable of eliminate the problems of each type multi-port memory particularly the DRAM related.

发明内容 DISCLOSURE

[0013] 本发明的一个一般的目的是提供能够基本上消除由已有技术的限制和缺点引起的一个或多个问题的半导体存储器件(多端口存储器)。 [0013] A general object of the present invention is to provide the ability to substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art semiconductor memory device caused by (multi-port memory).

[0014] 我们将在下列描述中提出本发明的特点和优点,并且一部分特点和优点将从描述和所附各图变得很清楚,或者可以根据描述中提供的指导通过实践本发明来了解这些特点和优点。 [0014] we will present the features and advantages of the invention in the following description, and some of the features and advantages from the description and the appended figures become apparent, or may be based on the guidance provided in the description to understand these by practice of the invention Features and Benefits. 我们将通过用使普通的熟练的技术人员能够实施本发明的那种完整,清楚,扼要和精确的术语在说明书中具体指出由一个多端口存储器能够实现和得到的本发明的各目的以及各其它的特点和优点。 We will by making the ordinary skilled in the art to practice the invention that a complete, clear, concise, and exact terms particularly pointed out in the specification of each object is achieved by a multi-port memory can be realized and attained by the present invention and each other The features and advantages.

[0015] 为了实现这些和其它的优点及根据本发明的目的,如在这里具体地和广泛地描述的那样,本发明提供这样一个半导体存储器件,该器件包括每个端口都接受指令的数量为N的多个外部端口和一个在输入到一个外部端口的各指令的最小时间间隔期间至少执行N 次存取操作的内部电路。 [0015] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly in the manner described herein, the present invention provides a semiconductor memory device, the device comprising each port number to receive instructions access operation executed N times the internal circuit of at least a plurality of N external ports and during an input to each instruction in an external port of the minimum time interval.

[0016] 进一步,提供一个判优电路,该判优电路确定一个内部电路执行输入到N个外部端口的多个指令时的指令执行次序。 [0016] Further, there is provided an arbiter, the arbitration circuit determines instruction execute multiple instructions input to an internal circuit N external ports when the execution order.

[0017] 在上面描述的本发明中,当指令进入N个端口时,所有的与N个端口对应的N个指令在任何给定的端口的最小指令周期内被一个接着一个地执行。 [0017] In the present invention, as described above, when the instruction enters N ports, all of the N ports corresponding N instructions are executed one after another in any given minimum instruction cycle port. 因此,一个与任何给定端口有关的存取指令出现在器件外部中并在最小指令周期内被执行。 Thus, one appears related to any given port access commands and are executed within the minimum instruction cycle in the external device. 在这种情形中,只有当从多个端口存取同一个地址时才会发生一个BUSY信号。 In this case, only when accessing the same address from a plurality of ports BUSY signal will occur. 这样就可以得到和SRAM型多端口存储器的BUSY状态出现概率一样低的BUSY状态出现概率。 So that you can get and BUSY state SRAM-type multi-port memory appears as a low probability of occurrence probability BUSY state.

[0018] 而且在本发明的半导体存储器件中,内部电路包括一个存储单元阵列,该阵列是由许多动态型存储单元和一个定义各存储单元被刷新的定时的刷新电路组成的。 [0018] Also in the semiconductor memory device of the present invention, the internal circuit includes a memory cell array, which is composed of a number of dynamic type memory cells and a refresh timer circuit defines the memory cells are refreshed composition. 在第一模式中,响应一个输入到N个外部端口中的至少一个端口的刷新指令刷新各存储单元,在第二模式中,在刷新电路确定的定时刷新各存储单元。 In a first mode, in response to an input to the N external ports, at least one port of the refresh command to refresh the memory cells, in the second mode, the refresh circuit determines the timing of refreshing the memory cells.

[0019] 如上面描述的本发明具有第一个操作模式,其中响应一个来自一个外部端口的指令执行刷新操作,和第二个操作模式,其中响应内部刷新电路执行刷新操作。 [0019] As described above, the present invention has a first mode of operation, wherein in response to an instruction from an external port of the refresh operation is performed, and the second mode of operation, wherein in response to the internal refresh circuit performs refresh operations. 因为这个配置,允许一个外部端口像一个用于刷新管理的端口那样地操作,以便在各琠w的时间间隔接收刷新指令,或者如果这个用于刷新管理的端口处在一个去激活状态,则内部刷新电路实施刷新操作。 Because of this configuration, allow an external port as a port for refresh management operation as to, in order to receive the respective constant time intervals a refresh command, or if this port for refresh in a deactivated state management, the internal refresh Circuit refresh operation. 这使按照系统配置以一种灵活的方式管理刷新操作成为可能。 This allows the system configuration according to a flexible way to manage refresh operations become possible.

附图说明 Brief Description

[0020] 图1是用于解释本发明原理(第1方面)的图; [0020] FIG. 1 is for explaining the principle (first aspect) of the present invention, FIG;

[0021] 图2是表示当只有一个端口正在被使用时实施的一个刷新操作的图。 [0021] FIG. 2 is a diagram showing a refresh operation when only one port is being used implementation.

[0022] 图3A到3C是在2个端口,3个端口和N个端口的情形中用于解释本发明原理的图; [0022] FIG. 3A to 3C are two ports, three ports, and N ports in a scenario to explain the principles of the present invention, FIG;

[0023] 图4是表示根据本发明(第1方面)的多端口存储器的第1实施例的方框图; [0023] FIG. 4 is a block diagram of the multi-port memory according to the first embodiment of the present invention (first aspect); and

[0024] 图5是与到一个判优器的指令输入有关的电路方框图; [0024] FIG. 5 is a command arbiter circuit block diagram of an input-related;

[0025] 图6A和6B是表示判优器的一个配置的电路图; [0025] FIG. 6A and 6B is a circuit diagram of an arbiter configuration;

[0026] 图7是表示判优器操作的定时图; [0026] FIG. 7 is a timing chart showing the operation of the arbiter;

[0027] 图8是与到一个DRAM芯的地址输入有关的电路方框图; [0027] FIG. 8 is a DRAM core address input circuit block diagram relating;

[0028] 图9是与数据输出有关的电路方框图; [0028] FIG. 9 is a circuit block diagram relating to the data output;

[0029] 图10是表示一个传输信号发生电路的配置的电路图。 [0029] FIG. 10 is a circuit diagram showing the configuration of a transmission signal generating circuits.

[0030] 图11是与数据输入有关的电路方框图; [0030] FIG. 11 is a circuit block diagram relating to the data input;

[0031] 图12是表示当连续输入Read(读)指令时实施的操作的定时图; [0031] FIG. 12 is a timing chart showing the operation when the continuous input Read (read) command implementation;

[0032] 图13是表示当连续输入Write (写)指令时实施的操作的定时图; [0032] FIG. 13 is a timing chart showing the operation when the continuous input Write (write) command implementation;

[0033] 图14是表示当A端口和B端口两者都操作在最大时钟频率上时的定时图; [0033] FIG. 14 is a timing chart when both the A port and the B port operate at the maximum clock frequency of;

[0034] 图15是表示当A端口和B端口两者都操作在最大时钟频率上时的定时图; [0034] FIG. 15 is a timing chart when both the A port and the B port operate at the maximum clock frequency of;

[0035] 图16是表示当指令从Read指令改变到Write指令时的操作的定时图; [0035] FIG. 16 is changed when the instruction from the Read instruction to the timing chart showing an operation when Write instruction;

[0036] 图17是表示当指令从“Read”改变到“feite”时输入一个刷新指令的定时的图; [0036] FIG. 17 shows when the instruction from "Read" to change the input "feite" a refresh command timing diagram;

[0037] 图18是表示当使一个端口去激活时实施的操作的定时图; [0037] FIG. 18 is a timing diagram showing the operation when one of the ports is deactivated when implemented;

[0038] 图19是表示当使两个端口去激活时实施的操作的定时图; [0038] FIG. 19 is a timing chart showing the operation when the two ports are deactivated implementation;

[0039] 图20A和20B是表示DRAM芯操作的定时图; [0039] FIG. 20A and 20B is a timing chart DRAM core operations;

[0040] 图21是表示当只使一个端口操作时实施的两倍速率操作的定时图; [0040] FIG. 21 is a timing chart showing double-rate operation when only the implementation of a port operation;

[0041] 图22是表示当通过使时钟频率两倍高使数据传输速率两倍时两倍速率操作的定时图; [0041] FIG. 22 is a view showing a frequency twice as high by the clock rate is twice the data transfer rate is twice the operation timing chart;

[0042] 图23是用于解释本发明(第1方面)的第2实施例的图; [0042] FIG. 23 is used to explain the present invention (first aspect) in view of the second embodiment;

[0043] 图M是表示根据本发明(第1方面)的多端口存储器的第2实施例的方框图; [0043] FIG M is a block diagram showing a second embodiment of the present invention (first aspect) of the multi-port memory;

[0044] 图25A和25B是用于解释连续模式的定时图; [0044] Figure 25A and 25B is a timing chart to explain the continuous mode;

[0045] 图沈是表示当对于A端口的Read指令和B端口的feite指令产生BUSY信号时实施的操作的定时图; [0045] FIG Shen is a timing chart showing the operation when the instruction for feite A port and B port Read instruction generating BUSY signal;

[0046] 图27是表示当对于A端口的Read指令和B端口的feite指令产生BUSY信号时实施的操作的定时图;[0047] 图28是表示当对于A端口的feite指令和B端口的feite指令产生BUSY信号时实施的操作的定时图; [0046] FIG. 27 is a timing chart showing the operation when the instruction for feite A port and B port Read instruction generating BUSY signal; [0047] FIG. 28 is a port when feite for A and B ports feite instruction BUSY signal is generated when a timing chart of the operation of the instruction;

[0048] 图四是表示当对于A端口的feite指令和B端口的feite指令产生BUSY信号时实施的操作的定时图; [0048] Figure IV is a timing chart showing the operation when the instruction for feite A port and B port feite instruction generating BUSY signal;

[0049] 图30是表示在一个能够处理由控制器发出的中断指令的配置中操作的定时图; [0049] FIG. 30 is a timing diagram can handle an interrupt instruction issued by the controller operating configuration;

[0050] 图31是表示根据本发明(第1方面)的第2实施例的多端口存储器的一个地址比较器,一个BUSY I/O系统,和一个中断系统的配置的图; [0050] FIG. 31 is a diagram according to the present invention (first aspect) of a second embodiment of the multi-port memory of an address comparator, a BUSY I / O system, and an interrupt configuration of the system of FIG;

[0051] 图32是表示主器件操作的定时图; [0051] FIG. 32 is a timing chart showing the main operation of the device;

[0052] 图33是表示从器件操作的定时图; [0052] FIG. 33 is a timing chart showing the operation of the device;

[0053] 图34是表示当两个端口的写地址相同时实施的主器件操作的定时图; [0053] FIG. 34 is a timing chart when the master of the write addresses of the two ports are the same implementation of operations;

[0054] 图35是表示当两个端口的写地址相同时实施的从器件操作的定时图; [0054] FIG. 35 is a timing chart showing operation of the device when the write addresses of the two ports of the same embodiment;

[0055] 图36是表示当两个端口的写地址相互匹配使控制器发出中断指令时主器件操作的定时图; [0055] FIG. 36 is a write address when the two ports match each other so that the controller issues an interrupt instruction timing chart when the master device operation;

[0056] 图37是表示当两个端口的写地址相互匹配使控制器发出中断指令时从器件操作的定时图; [0056] FIG. 37 is a write address when the two ports match each other so that the controller issues an interrupt instruction from the timing chart of operation of the device;

[0057] 图38是用于解释本发明(第2方面)的原理的图,表示当对于两个端口实施读操作时的情形; [0057] FIG. 38 is used to explain the present invention (second aspect) of the principle of showing respect to the two ports when read operations of circumstances;

[0058] 图39是用于解释本发明(第2方面)的原理的图,表示脉冲串长度为4的例子; [0058] FIG. 39 is for explaining the present invention (second aspect) of the principle diagram showing an example of the burst length is 4;

[0059] 图40是表示在2和3个端口的情景情形中在一个最小外部指令周期和各内部操作周期之间的关系的图; [0059] FIG. 40 is a scene at 2 and 3 in the case of port between a minimum external command cycle and internal operation cycles in Fig relations;

[0060] 图41是表示在η个端口的情形中在一个最小外部指令周期和各内部操作周期之间的关系的图; [0060] FIG. 41 is a view showing η ports in case of showing the relationship between a minimum external command cycle and internal operation cycles in between;

[0061] 图42是表示根据本发明(第2方面)的一个实施例的多端口存储器的配置的图; [0061] FIG. 42 is a multi-port memory according to the present invention (second aspect) of an embodiment of a configuration diagram;

[0062] 图43Α到43C是表示根据本发明(第2方面)的实施例的多端口存储器的配置的图; [0062] FIG 43Α to 43C is a multi-port memory according to the present invention (second aspect) of the configuration of an embodiment;

[0063] 图44是表示根据第1实施例与指令处理有关的各装置的配置的图; [0063] FIG. 44 is a diagram showing the configuration related to the respective processing apparatus according to the first embodiment of FIG instruction;

[0064] 图45是表示根据第1实施例与指令处理有关的各装置的配置的图; [0064] FIG. 45 is a diagram showing the configuration related to the respective processing apparatus according to the first embodiment of FIG instruction;

[0065] 图46是判优器的实施例; [0065] FIG. 46 is an embodiment of the arbiter;

[0066] 图47是表示根据第1实施例与地址处理有关的部分的配置的图; [0066] FIG. 47 is a process-related portion of the configuration of a first embodiment according to the address;

[0067] 图48是表示根据第1实施例与数据输出有关的部分的配置的图; [0067] FIG. 48 is a diagram showing the configuration of a portion relevant to data outputting according to the first embodiment;

[0068] 图49是表示图48的传输信号发生电路的图。 [0068] FIG. 49 is a diagram showing a transmission signal generating circuit of Figure 48.

[0069] 图50是表示根据第1实施例与数据输入有关的部分的配置的图; [0069] FIG. 50 is input according to the first embodiment of the data configuration of a portion relevant;

[0070] 图51是表示当将Read指令接连地输入两个端口时实施的操作的图; [0070] FIG. 51 is a diagram showing the operation of the time when the Read instruction successively input two ports implemented;

[0071] 图52是表示当将Read指令接连地输入两个端口时实施的操作的图; [0071] FIG. 52 is a diagram showing the operation of the time when the Read instruction successively input two ports implemented;

[0072] 图53表示当接连地输入Write指令时的例子; [0072] Figure 53 shows an example of when input successively when Write instruction;

[0073] 图M表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作; [0073] FIG M means that when both the A port and the B port operate operation performs Read operations at the maximum clock frequency of implementation;

[0074] 图55表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作;[0075] 图56是表示当A端口和B端口两者都操作在最大时钟频率上进行Write操作时实施的操作的图; [0074] FIG. 55 indicates that when both the A port and the B port operate operation performs Read operations at the maximum clock frequency is implemented; [0075] FIG. 56 is a port when both A and B port operate at the maximum clock frequency Write operations performed on the implementation of the operation diagram;

[0076] 图57是表示当两个端口都操作在最高频率,并用内部产生的刷新指令使从Write 指令改变到Read指令时实施的操作的时间图; [0076] FIG. 57 is when both ports operate at the highest frequency, and with internally generated refresh command enables Write command change from the time when the Directive showing the operation of Read;

[0077] 图58是表示当两个端口都操作在最高频率,并用内部产生的刷新指令使从写指令改变到读指令时实施的操作的时间图; [0077] FIG. 58 is a when both ports operate at the highest frequency, and with internally generated refresh command to make time showing the operation of the write command is changed to read instructions from the implementation;

[0078] 图59A和59B是DRAM芯操作的定时图; [0078] FIG. 59A and 59B is a timing diagram of the DRAM core operations;

[0079] 图60是表示刷新电路的配置的电路图; [0079] FIG. 60 is a circuit diagram showing a configuration of the refresh circuit;

[0080] 图61是表示第2判优器的电路配置的图; [0080] FIG. 61 is a second arbiter circuit configuration diagram;

[0081] 图62表示两个端口经受Write — Read的指令改变,和在REF传输禁止期间发生一个刷新定时器事件的情形; [0081] FIG. 62 shows two ports subjected Write - Read the instructions to change a refresh timer event occurs during the case and prohibit REF transmission;

[0082] 图63表示两个端口经受Write — Read的指令改变,和在REF传输禁止期间发生一个刷新定时器事件的情形; [0082] FIG. 63 shows the two ports is subjected to Write - Read the instructions to change a refresh timer event occurs during the case and prohibit REF transmission;

[0083] 图64表示两个端口如上面情形一样经受Write — Read的指令改变,但是在REF 传输禁止期间前发生一个刷新定时器的情形; [0083] Figure 64 shows the same two ports as in the case above, it is subjected to Write - Read the instructions to change, but the case of the occurrence of a refresh timer before a REF transfer prohibition period;

[0084] 图65表示两个端口如上面情形一样经受Write — Read的指令改变,但是在REF 传输禁止期间前发生一个刷新定时器的情形; [0084] FIG. 65 shows two ports as is the case as above is subjected to Write - Read the instructions to change the situation but a refresh timer occurs before a REF transfer prohibition period in;

[0085] 图66表示只有A端口经受feite — Read的指令变迁,和在REF传输禁止期间发生一个刷新定时器事件的情形; [0085] FIG. 66 shows only the A port withstand feite - Read the instruction changes, and a refresh timer event occurs during a REF transfer prohibition circumstances;

[0086] 图67表示只有A端口经受feite — Read的指令变迁,和在REF传输禁止期间发生一个刷新定时器事件的情形; [0086] FIG. 67 shows only the A port withstand feite - Read the instruction changes, and a refresh timer event occurs during a REF transfer prohibition circumstances;

[0087] 图68表示在两个端口连续写的情形的定时图; [0087] FIG. 68 shows the case of two ports continuous writing timing chart;

[0088] 图69表示在两个端口连续写的情形的定时图; [0088] FIG. 69 shows the case of two ports continuous writing timing chart;

[0089] 图70表示与图57和图58所示的第1实施例操作对应的第2实施例操作的定时图; [0089] FIG. 57 and FIG. 70 shows a first embodiment of the operation of the second embodiment corresponding to the operation timing chart shown in Figure 58;

[0090] 图71表示与图57和图58所示的第1实施例操作对应的第2实施例操作的定时图; [0090] FIG. 71 shows a second embodiment of a timing diagram illustrating the operation of the first embodiment corresponding to the operation of FIG. 57 and shown in FIG. 58;

[0091] 图72表示与图56所示的第1实施例操作对应的第2实施例操作的定时图; [0091] FIG. 72 and FIG. 56 shows a first embodiment of the operation of the second embodiment corresponding to the operation timing chart shown;

[0092] 图73是用于解释本发明(第3方面)的原理的图,表示对于两个端口实施读操作的情形; [0092] FIG. 73 is used to illustrate the present invention (third aspect) the principle of showing respect to the case of two ports of read operations;

[0093] 图74是用于解释本发明(第3方面)的原理的图,表示脉冲串长度为4的例子; [0093] FIG. 74 is used to illustrate the present invention (third aspect) principle, and shows an example of the burst length is 4;

[0094] 图75是表示在2和3个端口情形中在一个最小外部指令周期和各内部操作周期之间关系的图; [0094] FIG. 75 is a 2 and 3-port case in showing the relationship between a minimum external command cycle and internal operation cycles of each;

[0095] 图76是表示在N个端口情形中在一个最小外部指令周期和各内部操作周期之间关系的图; [0095] FIG. 76 shows the case of N ports in the relationship between a minimum external command cycle and internal operation cycles in the graph;

[0096] 图77是表示根据本发明(第3方面)的一个实施例的多端口存储器的配置的图; [0096] FIG. 77 is a diagram according to the present invention (third aspect) of a multi-port memory configuration of the embodiment of FIG;

[0097] 图78A到78C是表示根据本发明(第3方面)的上述实施例的多端口存储器的配置的图; [0097] FIG. 78A to 78C is a multi-port memory according to the present invention (third aspect) of the above configuration of an embodiment;

[0098] 图79是表示根据第1实施例与指令处理有关的各装置的配置的图;[0099] 图80是表示根据第1实施例与指令处理有关的各装置的配置的图; [0098] FIG. 79 shows a processing configuration of each device related to a first embodiment in accordance with FIG instruction; [0099] FIG. 80 is a diagram showing the first embodiment of the instruction processing configuration of each apparatus in accordance with the relevant;

[0100] 图81是判优器的实施例; [0100] FIG. 81 is an embodiment of the arbiter;

[0101] 图82是表示指令寄存器的配置的图; [0101] FIG. 82 is a diagram showing the configuration of an instruction register;

[0102] 图83是表示指令寄存器的配置的图; [0102] FIG. 83 is a diagram showing the configuration of an instruction register;

[0103] 图84A和图84B表示寄存器控制电路的操作; [0103] FIG. 84A and 84B represent register controls operation of the circuit;

[0104] 图85是表示指令寄存器操作的图; [0104] FIG. 85 is a diagram showing the instruction register operations;

[0105] 图86是表示指令寄存器操作的图; [0105] FIG. 86 is a diagram showing the instruction register operations;

[0106] 图87是表示根据第1实施例与地址处理有关的部分的配置的图; [0106] FIG. 87 is a process-related portion of the configuration of a first embodiment according to the address;

[0107] 图88是表示根据第1实施例与数据输出有关的部分的配置的图; [0107] FIG. 88 is a diagram showing the configuration of a portion relevant to data outputting according to the first embodiment;

[0108] 图89是表示图88的传输信号发生电路的图; [0108] FIG. 89 is a diagram showing a transmission signal generator 88 of FIG circuit;

[0109] 图90是表示根据实施例与数据输入有关的部分的配置的图; [0109] FIG. 90 shows an embodiment in accordance with the input data relating to the configuration of FIG portion;

[0110] 图91是表示根据实施例与数据输入有关的部分的配置的图; [0110] FIG. 91 shows an embodiment in accordance with the input data relating to the configuration of FIG portion;

[0111] 图92表示当将Read指令接连地输入两个端口时实施的操作; [0111] FIG. 92 shows when the operation will enter Read instruction successively implemented two ports;

[0112] 图93表示当将Read指令接连地输入两个端口时实施的操作; [0112] FIG. 93 indicates when the operation will enter Read instruction successively implemented two ports;

[0113] 图94表示当将接连地输入Write指令时的例子; [0113] FIG. 94 represents an example of when the succession input when Write instruction;

[0114] 图95表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作; [0114] FIG. 95 indicates that when both the A port and the B port operate at the maximum clock operating frequency Read operation is implemented;

[0115] 图96表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作; [0115] FIG. 96 indicates that when both the A port and the B port operate operation performs Read operations at the maximum clock frequency of implementation;

[0116] 图97是表示当A端口和B端口两者操作在最大时钟频率上进行Write操作时实施的操作的图; [0116] FIG. 97 is a diagram showing the operation of the time when both the A port and the B port operations Write operations at the maximum clock frequency of implementation;

[0117] 图98是表示当两个端口操作都在最高频率,并用内部产生的刷新指令使从Write 指令改变到Read指令时实施的操作的时间图; [0117] FIG. 98 is a diagram showing the operation when the two ports are at the highest frequency, and with internally generated refresh command enables Write command change from the time when the Directive showing the operation of Read;

[0118] 图99是表示当两个端口都操作在最高频率,并用内部产生的刷新指令使从Write 指令改变到Read指令时实施的操作的时间图; [0118] FIG. 99 is a diagram when both ports operate at the highest frequency, and with internally generated refresh command enables Write command change from the time when the Directive showing the operation of Read;

[0119] 图100A和100B是DRAM芯操作的定时图; [0119] FIG. 100A and 100B are timing charts DRAM core operations;

[0120] 图101是表示根据本发明(第4方面)的多端口存储器的实施例的方框图; [0120] FIG. 101 is a block diagram illustrating an embodiment of the present invention (fourth aspect) of the multi-port memory;

[0121] 图102是表示根据本发明(第4方面)的多端口存储器操作的一个例子的定时图; [0121] FIG. 102 is a multi-port memory according to the present invention (fourth aspect) is an example of the operation timing chart;

[0122] 图103是表示根据本发明(第4方面)的多端口存储器操作的一个例子的定时图; [0122] FIG. 103 is in accordance with the present invention (fourth aspect) multi-port memory operation timing diagram of an example;

[0123] 图104是表示根据本发明(第4方面)的多端口存储器操作的另一个例子的定时图; [0123] FIG. 104 is in accordance with the present invention (fourth aspect) multi-port memory operation timing diagram of another example;

[0124] 图105是表示指令译码器寄存器的方框图; [0124] FIG. 105 is a block diagram of the instruction decoder register;

[0125] 图106是根据本发明(第4方面)的实施例的判优器的方框图; [0125] FIG. 106 is a block diagram of an arbiter according to an embodiment of the present invention (fourth aspect); and

[0126] 图107是表示判优器操作的定时图; [0126] FIG. 107 is a timing chart showing the operation of the arbiter;

[0127] 图108是地址缓冲器/寄存器和地址改变电路的方框图; [0127] FIG. 108 is a block diagram of the address buffer / register and address change circuit;

[0128] 图109是存储块的方框图; [0128] FIG. 109 is a block diagram of a memory block;

[0129] 图IlOA和IlOB是表示存储块操作的定时图;[0130] 图111表示根据本发明(第5方面)的多端口存储器的第1实施例; [0129] FIG IlOA and IlOB is a timing chart showing the operation of the memory block; [0130] FIG. 111 denotes according to the present invention (fifth aspect) of a first embodiment of the multi-port memory;

[0131] 图112表示多端口存储器的I/O电路5010和存储块MB的详细情况; [0131] FIG. 112 represents I / O circuit 5010 and the details of the multi-port memory block MB of memory;

[0132] 图113表示地址比较电路的详细情况; [0132] FIG. 113 showing the details of the address comparing circuit;

[0133] 图114表示比较器的详细情况; [0133] Figure 114 shows the details of the comparator;

[0134] 图115表示当加到加到输入/输出端口PORT-A和P0RT-B的行地址信号RA相互匹配时实施的比较器操作; [0134] FIG. 115 represents the time when the comparator is added to the input / output ports PORT-A and P0RT-B of the row address signals RA match each other to implement the operation;

[0135] 图116表示当行地址信号RA在输入/输出端口PORT-A和PORT-B之间不匹配时比较器的操作; [0135] FIG. 116 indicates when the operation of the comparator when the address signals RA do not match between the input / output ports PORT-A and PORT-B line;

[0136] 图117表示当加到输入/输出端口PORT-A和P0RT-B的行地址信号RA在时钟信号CLKA与时钟信号CLKB具有不同周期的条件下匹配时比较器的操作; [0136] FIG. 117, when applied to the operation of the comparator input / output ports PORT-A and P0RT-B of the row address signals RA match in the clock signal and the clock signal CLKA CLKB conditions have different periods;

[0137] 图118表示提供给图112所示的判优电路的判优控制电路; [0137] FIG. 118 indicates to the arbiter of the arbitration control circuit 112 shown in FIG;

[0138] 图119表示当加到输入/输出端口PORT-A和P0RT-B的行地址信号匹配时实施的判优控制电路的操作; [0138] FIG. 119 showing the operation when the row address signal is applied to match the input / output ports PORT-A and P0RT-B of the implementation of the arbitration control circuit;

[0139] 图120表示当加到输入/输出端口PORT-A和P0RT-B的行地址信号RA相互匹配时实施的操作; [0139] 120 indicates that when applied to the operation of the input / output ports PORT-A and the row address signals RA P0RT-B match each other embodiment;

[0140] 图121表示当时钟信号CLKA和CLKB的周期相同,时钟信号CLKA的相位超前时钟信号CLKB的相位多于半个周期时实施的操作; [0140] Figure 121 shows the same when the clock signals CLKA and CLKB cycles, more than half of the operation cycle of the clock signal CLKA embodiment of a phase advance of the phase of the clock signal CLKB;

[0141] 图122表示当几乎同时加到输入/输出端口PORT-A和P0RT-B的行地址信号RA 相互不同时的操作; [0141] FIG. 122 indicates when almost simultaneously supplied to the input / output ports PORT-A and P0RT-B of the row address signals RA differ from each other in the operation;

[0142] 图123表示多端口存储器的第2实施例和根据本发明(第5方面)控制多端口存储器的方法; [0142] FIG. 123 shows a second embodiment of the multi-port memory and control of multi-port memory according to the (fifth aspect) of the present invention method;

[0143] 图IM表示多端口存储器的第3实施例和控制根据本发明(第5方面)控制多端口存储器的方法; The method of the third embodiment and the control of the control multi-port memory according to (fifth aspect) of the present invention [0143] FIG IM represents multi-port memory;

[0144] 图125表示判优控制电路的详细情况; [0144] 125 shows the details of the arbitration control circuit;

[0145] 图1¾表示当加到输入/输出端口PORT-A和PORT-B的行地址信号相互匹配时实施的判优控制电路的操作; [0145] FIG 1¾ means that when applied to the operation of the input / output ports PORT-A and the row address signal PORT-B match each other to implement the arbitration control circuit;

[0146] 图127表示当输入/输出端口PORT-A和P0RT-B接收有效指令ACT和相同的行地址信号RA时实施读操作的方法; [0146] FIG. 127 indicates when the input / output ports PORT-A and P0RT-B reception method embodiments when read operation active commands ACT and the same row address signals RA;

[0147] 图1¾表示当将有效指令ACT和相互不同的行地址信号RA加到输入/输出端口PORT-A和PORT-B时实施读操作的方法; [0147] FIG 1¾ indicates when active commands ACT and mutually different row address signals RA supplied to the input / output ports PORT-A method and implementation PORT-B during a read operation;

[0148] 图1¾表示当输入/输出端口PORT-A和PORT-B接收有效指令ACT和相同行地址信号RA时实施写操作的方法; [0148] FIG 1¾ indicates when the input / output ports PORT-A and PORT-B receive active commands writes manner when ACT and the same row address signals RA;

[0149] 图130表示对于输入/输出端口PORT-A连续地实施写操作和读操作,和对于输入/输出端口PORT-B相继地实施指向与输入/输出端口PORT-A的写操作的行地址信号RA相同的行地址信号RA的写操作和指向与输入/输出端口PORT-A的读操作的行地址信号RA 相同的行地址信号RA的写操作的情形; [0149] FIG. 130 represents the input / output port PORT-A is continuously write operation and a read operation, and the input / output port PORT-B are successively write operation of the row address at the input / output ports PORT-A's write and point to the input / read row address signals RA output port PORT-A of the same row address signals RA signal RA circumstances writes the same row address signals RA;

[0150] 图131表示对于输入/输出端口PORT-A连续地实施写操作和读操作,和对于输入/输出端口PORT-B相继地实施指向与输入/输出端口PORT-A的写操作的行地址信号RA相同的行地址信号RA的读操作和指向与输入/输出端口PORT-A的读操作的行地址信号RA相同的行地址信号RA的写操作的情形; [0150] FIG. 131 shows how an input / output port PORT-A is continuously write operation and a read operation, and the input / output port PORT-B are successively write operation of the row address at the input / output ports PORT-A's read and pointing and input / read row address signals RA same row address signals RA writes situation output port PORT-A of the same row address signals RA signals RA;

[0151] 图132表示在时钟信号CLKA和CLKB具有不同的时钟周期的情形中当加到输入/ 输出端口PORT-A和PORT-B的行地址信号相互匹配时实施的操作; [0151] FIG. 132 shows a clock signal CLKA and CLKB having different clock cycles when applied to the case of operating the input / output ports PORT-A and the row address signal PORT-B match each other embodiment;

[0152] 图133表示多端口存储器的第4实施例和根据本发明(第5方面)控制多端口存储器的方法; [0152] FIG. 133 shows a fourth embodiment of the multi-port memory and control of multi-port memory according to the (fifth aspect) of the present invention method;

[0153] 图134表示当输入/输出端口PORT-A和PORT-B接收有效指令ACT和相同的行地址信号RA时实施读操作的方法; [0153] FIG. 134 indicates when the input / output ports PORT-A and PORT-B receives the method of implementation of the read operation when active commands ACT and the same row address signals RA;

[0154] 图135表示当将有效指令ACT和不同的行地址信号RA加到输入/输出端口PORT-A 和PORT-B时实施读操作的方法; [0154] FIG. 135 indicates when active commands ACT and different row address signals RA supplied to the input / output ports PORT-A method and implementation PORT-B during a read operation;

[0155] 图136表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,实施写操作,接着加上有效指令ACT和不同的行地址信号RA,导致实施写操作的情形; [0155] FIG. 136 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, a write operation, followed by active commands ACT and different row address signals RA, leading to in the case of a write operation embodiment;

[0156] 图137表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,实施写操作,接着加上有效指令ACT和相同的行地址信号RA,导致在输入/输出端口PORT-A实施读操作和在输入/输出端口PORT-B实施写操作的情形; [0156] FIG. 137 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, a write operation, followed by active commands ACT and the same row address signals RA, leading to read operation on the input / output ports PORT-A and the input / output port PORT-B implementation case write operation;

[0157] 图138表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,实施写操作和读操作,接着加上有效指令ACT和不同的行地址信号RA,导致实施写操作和读操作的情形; [0157] FIG. 138 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, a write operation and a read operation, followed by active commands ACT and different row address signals RA, resulting in a write operation and read the case;

[0158] 图139表示根据多端口存储器的第5实施例的多端口存储器的操作和控制本发明(第5方面)的多端口存储器的方法。 [0158] FIG. 139 denotes a multi-port memory according to the operation of the multi-port memory of the fifth embodiment and the control of the present invention (fifth aspect) multi-port memory approach.

具体实施方式 DETAILED DESCRIPTION

[0159] 下面,我们参照所附各图描述本发明的各实施例。 [0159] Next, with reference to the accompanying figures we described various embodiments of the present invention.

[0160][本发明第1方面] [0160] [a first aspect of the present invention]

[0161] 我们首先描述本发明(第1方面)的原理。 [0161] We first describe the principles of the present invention (first aspect).

[0162] 图1是用于解释本发明(第1方面)的原理的图。 [0162] FIG. 1 is used to explain the present invention (first aspect) of the principle of the. 虽然图1表示用于解释2个端口情形中的原理的图,但是即便提供了两个以上的端口(N个端口)也可以得到相同的操作。 Although Figure 1 shows two ports for explaining the principle of the case, but even more than two ports provided (N ports) can be obtained the same operation.

[0163] 等效于内部电路(DRAM芯)操作的两个周期的时间跨度定义为外部指令周期的一个周期。 [0163] equivalent to two cycles of the internal circuit (DRAM-core) operation is defined as a period time span external instruction cycle. 即,芯操作周期是外部指令周期的速率的两倍。 That is, core operation cycles are double the rate of the external command cycle. 由内部存储器在两倍速率以指令越早到达就越早处理指令的这种次序对进入A端口和B端口的指令进行处理。 Twice the rate of internal memory in order to reach the sooner the earlier instruction processing instructions in this order to enter the A port and the B port of instruction processing. 然后将输出数据传送到每个端口。 Then transmits the output data to each port. 即,在一个芯操作周期中实施包括选择一条字线,放大数据,选择一条列线,读和写操作,预冲电操作的一系列操作,从而对相关的存储块完成一个存取操作。 That is, in one embodiment of the core operating cycle, including the selection of a word line, amplification data, select a column line, read and write operations, a series of pre-shoot operation electrically operated, and thus the associated memory blocks to complete an access operation.

[0164] 例如,在与图1的A端口有关的外部指令周期的定时Cl,在A端口进入一个Read 指令。 [0164] For example, in the timing Cl A port of FIG. 1 relating to the external command cycle, the A port to enter a Read instruction. 进一步,在一个与B端口有关的外部指令周期的定时Cl',在B端口进入一个Read 指令。 Further, at a timing of Cl B port external command cycle relevant to the 'in entering a Read command of the B port. 因为A端口的Read指令的定时稍微早一些,所以这个Read指令在进入B端口的读指令之前被执行。 Read the instruction due to timing A port is slightly earlier, so the Read instruction is executed before entering the B port read instruction. 这里,一个外部指令周期对应于4个时钟脉冲周期。 Here, one external command cycle corresponds to four clock cycles. 如图1所示,在与1 个芯操作周期对应的2个时钟脉冲周期中执行和完成每个Read指令。 As shown in Figure 1, the implementation and completion of each of the Read instruction with a core operation cycle corresponding to two clock cycles. 因此,响应在等效于一个外部指令周期的4个时钟脉冲周期的时间间隔中进入A端口和B端口的Read指令,能够实施读操作,而不会产生一个BUSY状态即便来自A端口的读存取和来自B端口的读存取都指向同一个存储块。 Therefore, the response into the Read command of the A port and the B port at the equivalent to an external command cycle of four clock cycles time interval, the read operation can be implemented without generating a BUSY state even read memory from A port Take and read access from the B port is point to the same memory block. 这通过在2个时钟脉冲周期中执行和完成每个存取来实现。 This is achieved by implementing and completing each access in two clock cycles to achieve.

[0165] 在这种方式中,即便多个端口同时存取同一个存储块,因为内部存储器能够以两倍的速度进行相继的和连续的处理,所以也不会产生一个BUSY状态。 [0165] In this manner, even when a plurality of ports simultaneously access the same memory block, because the internal memory can be twice as fast and continuous successive process, so it will not generate a BUSY state.

[0166] 而且,当如图1所示从器件外部(例如在A端口)给出一个刷新指令时,在该器件内部能够实施刷新操作而不会影响来自另一个端口(即本例中的B端口)的存取。 [0166] Further, when 1 from an external device (e.g., the A port) is given when a refresh command, in the interior of the device can be implemented without affecting the refresh operation from another port (i.e. in this example the B port) access. 在这种情形中,可以选择多个端口中的一个(即图1例中的A端口)作为进行刷新管理的端口,总是从这个端口进入刷新指令。 In this case, you can select one of the plurality of ports (ie Port A Figure 1 case) as the refresh management port always enters refresh command from the port.

[0167] 而且,数据输出可以取来从多个列地址并行地读出数据和通过在输出时将并行数据变换成串行数据输出数据的脉冲串的形式。 [0167] Further, the data output can be taken in parallel to read data from a plurality of column addresses and by the parallel output data into the form of bursts of serial data output data. 这增加了数据传输速率并使响应连续的Read 指令连续地输出数据成为可能。 This increases the data transfer rate in response to continuous Read commands and successively outputs the data becomes possible.

[0168] 图2是表示当只有一个端口正在被使用时实施的刷新操作的图。 [0168] FIG. 2 is a diagram showing when only one port is being used to implement a refresh operation.

[0169] 如图2所示,当提供2个端口,例如,A端口和B端口时,不需要让2个端口都操作。 [0169] As shown in Figure 2, while providing two ports, for example, when the A port and the B port, do not need to make two port operations. 在器件内提供一个刷新定时器使内部产生刷新指令成为可能。 Provided a refresh timer inside the device makes it possible to internally generated refresh command.

[0170] 如图2所示,例如,当一个端口(例如,B端口)不在操作时能够内部产生刷新指令,从而执行刷新指令而不会影响在A端口的存取。 [0170] As shown in Figure 2, for example, when a port (e.g., B port) is not in operation when a refresh command can be internally generated, thereby executing a refresh command without affecting access at the A port.

[0171 ] 现在我们考虑一个例子,其中当进行刷新管理时,控制器A控制A端口,控制器B 控制B端口。 [0171] We now consider an example in which when the refresh management, the controller A controls the A port, the controller B controls the B port. 在这种情形中,如果存在一个如上述的内部刷新功能,则当只用A端口时B端口能够完全停止。 In this case, if there is an internal refresh function as described above, then when only the A port B port can be completely stopped. 这就能够减少由于下面的系统操作的改变引起的功率消耗。 This operating system can be reduced due to the change of power consumption due to the following.

[0172] 图3A到3C是当2个端口,3个端口和N个端口时用于解释本发明原理的图。 [0172] FIG. 3A to 3C when the two ports, three ports, and N ports to explain the principles of the present invention are used in FIG.

[0173] 如上面所描述的,本发明也可应用于有3个或更多端口的多端口存储器。 [0173] As described above, the present invention may be applied to have three or more multi-port memory port. 图3A表示在如图1和图2所示的提供2个端口的情形中1个端口的操作。 3A shows an operation of the port providing two-port 2 shown in Figures 1 and the case. 图:3B表示在3个端口的情形中1个端口的操作,图3C表示N个端口的情形。 FIG: 3B shows the three ports in the case of a port operation, Fig. 3C shows the case of the N ports. 如图3C所示,可以适当地将内部操作周期的长度设定在1/N与N个端口存储器的情形中的外部指令周期一样长。 3C, the length may be appropriately set internal operation cycles in the case of 1 / N with N-port of the memory as long as the external command cycle.

[0174] 下面,我们描述根据本发明的一个实施例的半导体存储器件。 [0174] Here, we describe a semiconductor memory device according to one embodiment of the invention.

[0175] 图4是表示根据本发明的多端口存储器的第1实施例的方框图。 [0175] FIG. 4 is a block diagram according to the first embodiment of the multi-port memory of the present invention. 在这个例子中, 提供了具有2个端口,即A端口和B端口的配置。 In this case, it provided that the A port and the B port configuration has two ports.

[0176] 图4的多端口存储器10包括A端口11,B端口12,自刷新电路13,DRAM芯14,判优器15,刷新指令寄存器16,指令寄存器A 17,指令寄存器B 18,刷新地址寄存器19,地址寄存器A 20,地址寄存器B 21,写数据寄存器A 22,写数据寄存器B 23,传输门A 24,和传输门B 25。 [0176] FIG. 4 is a multi-port memory 10 includes a port A 11, B port 12, a self-refresh circuit 13, DRAM core 14, an arbiter 15, a refresh command register 16, the command register A 17, the command register B 18, a refresh address register 19, the address register A 20, an address register B 21, the write data register A 22, the write data register B 23, a transfer gate A 24, and the transfer gate B 25.

[0177] A端口11包括模寄存器31,CLK缓冲器32,数据I/O电路33,地址缓冲器;34,和指令译码器35。 [0177] A port 11 includes a mode register 31, CLK buffer 32, the data I / O circuit 33, an address buffer; 34, 35, and instruction decoder. 进一步,B端口12包括模寄存器41,CLK缓冲器42,数据I/O电路43,地址缓冲器44,和指令译码器45。 Further, B port 12 includes a mode register 41, CLK buffer 42, the data I / O circuit 43, an address buffer 44, and the instruction decoder 45. 在A端口11和B端口12,分别与时钟信号CLKA和CLKB同步地独立地建立到外部总线的存取和来自外部总线的存取。 In the A port 11 and the B port 12, respectively, and the clock signal CLKA and CLKB established independently in synchronization to an external bus access and access from an external bus. 模寄存器31和41能够在其中存储对于各端口的模式设定如数据等待时间和脉冲串长度。 Mode registers 31 and 41 can store therein mode for each port settings such as data latency and a burst length. 在这个实施例中,A端口11和B端口12两者都具有各自的模寄存器,使每个端口都能进行模式设定。 In this embodiment, A port 11 and the B port 12 both of which have their own mode register, so that each port can make mode settings. 然而,可以将模寄存器只安排在一个端口中,例如,使得对于2个端口的设置可以由对这一个端口的设置来实现。 However, we can arrange a mode register only in a port, for example, that for two-port settings can be made in these settings to achieve a port.

[0178] 自刷新电路13包括刷新定时器46和刷新指令发生器47。 [0178] Self-refresh circuit 13 includes a refresh timer 46 and a refresh command generator 47. 自刷新电路13在器件中产生刷新指令,分别从A端口11和B端口12接收信号CKEAl和CKEBl。 Self-refresh circuit 13 generates a refresh command inside the device, respectively, from the A port 11 and the B port 12 receives a signal CKEAl and CKEBl. 信号CKEAl和CKEBl是分别用CLK缓冲器32和42对外部信号CKEA和CKEB进行缓冲得到的。 CKEAl and CKEBl signal CLK buffers are respectively 32 and 42 for external signal buffering CKEA and CKEB obtained. 用外部信号CKEA和CKEB暂停各端口的时钟缓冲器并使各端口去基活。 External signal CKEA and CKEB suspend clock buffers on each port and each port to base alive. 如果使A端口11和B端口12中的一个进入去激活状态,则自刷新电路13开始它的操作。 If the A port 11 and the B port 12 to enter a deactivated state, the self-refresh circuit 13 starts its operation. 在模寄存器31和41中进行了设置,使得一个端口负责刷新管理的情形中,当负责刷新管理的的端口变得不操作时可以激活自刷新电路13。 Was set up in the mode registers 31 and 41, making a port responsible for refresh management scenario, when the port responsible for refresh management becomes no operation can activate the self refresh circuit 13.

[0179] 进一步,DRAM芯包括存储器阵列51,译码器52,控制电路53,feiteAmp(写放大器)54和读出缓冲器55。 [0179] Further, DRAM core includes a memory array 51, a decoder 52, a control circuit 53, feiteAmp (write amplifier) 54 and the read-out buffer 55. 存储器阵列51在其中存储被写和被读的数据,并包括DRAM存储单元,单元门晶体管,字线,位线,读出放大器,列线,列门等。 The memory array 51 in which the storage is written and read data, and includes DRAM memory cells, cell gate transistors, word lines, bit lines, sense amplifiers, column lines, column doors. 译码器52对被存取的地址进行译码。 An address decoder 52 for decoding to be accessed. 控制电路53控制DRAM芯14的操作。 The control circuit 53 controls the operation of the DRAM core 14. feiteAmp 54放大写入存储器阵列51的数据。 feiteAmp 54 amplification of writing data to the memory array 51. 读出缓冲器阳放大从存储器阵列51读出的数据。 Yang enlarged sense buffer reads data from the memory array 51.

[0180] 将到A端口11的输入传输给地址寄存器A 20,刷新指令寄存器16,指令寄存器A 17和写数据寄存器A 22。 [0180] The transmission port 11 to the A input to the address register A 20, the refresh command register 16, a command register A 17 and write data register A 22. 进一步,将到B端口12的输入加到地址寄存器B 21,刷新指令寄存器16,指令寄存器B 18和写数据寄存器B 23。 Further, the input port 12 to B is added to the address register B 21, the refresh command register 16, a command register B 18, and write data register B 23.

[0181] 判优器(判优电路)15确定指令进入的次序,以便确定将用于在A端口11和B端口12之间进行处理的优先权给予哪个指令。 [0181] arbiter (arbitration circuit) 15 determines that the instruction in order to determine the A port 11 will be used for processing and between B port 12 which gives priority to instruction. 以确定的次序,判优器15将指令,地址和数据(在写操作的情形中)从各寄存器传输给DRAM芯14。 In order to determine the arbiter 15 will command, address and data (in the case of a write operation) from the registers transferred to the DRAM core 14. DRAM芯14根据接收的数据进行操作。 DRAM core 14 operates based on the received data. 在Read指令的情形中,将从DRAM芯14读出的数据传输给输入相应指令的端口,然后将该数据从并行数据变换成串行数据,接着与这个端口的时钟同步地输出。 In the case of a Read command, from the DRAM core 14 reads out the data corresponding to the input command port, and then the data is converted from parallel data to serial data, and then output the port with the clock synchronization.

[0182] 图5是与输入到判优器15的指令有关的电路的方框图; [0182] FIG. 5 is a block diagram of the circuit input to the arbiter 15 associated instruction;

[0183] 指令译码器35包括输入缓冲器61,指令译码器62和(n_l)时钟延迟电路63。 [0183] command decoder 35 includes an input buffer 61, command decoder 62, and (n_l) clock delay circuit 63. 而且,指令译码器45包括输入缓冲器71,指令译码器72和(n-1)时钟延迟电路73。 Moreover, the instruction decoder 45 includes an input buffer 71, command decoder 72 and the (n-1) clock delay circuit 73. 指令寄存器A 17包括读指令寄存器17-1和写指令寄存器17-2。 Command register A 17 includes a read-command register 17-1 and a write command register 17-2. 而且,指令寄存器B 18包括读指令寄存器18-1和写指令寄存器18-2。 Also, the command register B 18 includes a read-command register 18-1 and a write command register 18-2.

[0184] 在Read指令的情形中,分别通过指令译码器62或72将输入到输入缓冲器61或71的指令传输给读指令寄存器17-1或18-1,而没有任何定时操作。 [0184] In the case of a Read command, respectively, through the instruction decoder 62 or 72 is entered into the command input buffer 61 or 71 is transmitted to the read-command register 17-1 or 18-1 without any timing manipulation. 在^^切指令的情形中,由(n-1)时钟延迟电路63或73使进入的指令延迟(n_l)时钟,然后在当输入一系列要被写的脉冲串数据的第η个数据(即最后一个数据)时的定时将它传输给写指令寄存器17-2 或18-2。 ^^ Cut instruction in the case, the (n-1) clock delay circuit 63 or 73 entering the command delay (n_l) clock, and then when the input range of the first data to be written η burst data ( its timing and final transmission data) to the write command register 17-2 or 18-2.

[0185] 在刷新指令的情形中,将从A端口11,Β端口12或刷新指令发生器47提供的刷新指令传输到刷新指令寄存器16。 [0185] In the case of a refresh command, from the A port 11, Β port 12 or the refresh command generator 47 provides a refresh command is transmitted to the refresh command register 16. 因为并不如此经常地出现刷新指令,所以不需要提供多个刷新指令寄存器。 Because it does not appear so often refresh command, it is not necessary to provide a plurality refresh command register. 进一步,从模寄存器31和41提供输入到刷新指令发生器47的自刷新设置信息,该信息指出各端口中的哪一个负责刷新管理。 Further, from the mode registers 31 and 41 to provide input into the refresh command generator 47 of the self-refresh setting information that indicate which one of the ports is responsible for refresh management.

[0186] 判优器15检测将指令传输到各指令寄存器的次序,并以这个次序将指令一个接着一个地传输到DRAM控制电路53。 [0186] The arbiter 15 detects the command is transmitted to the order of the instruction register, and in this order one after the instruction is transmitted to the DRAM control circuit 53.

[0187] 当接收指令时(或当接近指令执行的结束时),DRAM控制电路53产生RESETl信号,让判优器15为下一个指令作好准备。 [0187] When receiving the instruction (or when near the end of instruction execution), DRAM control circuit 53 generates RESETl signals to the arbiter 15 to prepare for the next instruction. 在这个实施例的特定的配置中,当RESETl信号结束时DRAM控制电路53接收下一个指令。 In this particular configuration of the embodiment, when the end RESETl signal DRAM control circuit 53 receives the next instruction.

[0188]接收 RESETl 信号时,判优器15 将复位信号ResetRA,ResetffA, ResetRB, ResetffB和ResetREF中的一个加到指令寄存器A 17,指令寄存器B 18和刷新指令寄存器16中相应的一个。 [0188] RESETl signal is received, the arbiter 15 a reset signal ResetRA, ResetffA, ResetRB, ResetffB and ResetREF one added to the command register A 17, the command register B 18 and the refresh command register 16 corresponding one. 通过这个操作,使在其中存储了已经传输给DRAM芯14的指令的指令寄存器复位, 在这个指令寄存器中准备接收下一个指令。 With this operation, so in which to store the instruction has been transmitted to the DRAM core 14 of the instruction register is reset, ready to receive the next instruction in the instruction register.

[0189] 图6A和6B是表示判优器15的配置的电路图。 [0189] FIG. 6A and 6B is a circuit diagram showing the configuration of the arbiter 15.

[0190] 如图6A所示,判优器15包括比较器80-1到80-10,AND (“与,,)电路81-1到81-5, AND电路82-1到82-5,AND电路83-1到83-5,延迟电路84-1到84-5,倒相器85到87, NAND ( “与非”)电路88和倒相器89和90。比较器80-1到80-10每个都具有相同的电路配置,如图6B所示,包括NAND电路91和92和倒相器93和94。 [0190] FIG. 6A, the arbiter 15 includes comparators 80-1 to 80-10, AND ("and ,,) circuits 81-1 to 81-5, AND circuits 82-1 to 82-5, AND circuits 83-1 to 83-5, the delay circuit 84-1 to 84-5, inverter 85 through 87, NAND ("and not") circuit 88 and inverters 89 and 90. The comparators 80-1 to 80-10 each having the same circuit configuration, shown in Figure 6B, comprises a NAND circuit 91 and inverters 92 and 93 and 94.

[0191] 将来自指令寄存器A 17的读指令信号RA2和写指令信号WA2,来自指令寄存器B 18的读指令信号RB2和写指令信号WB2,和来自刷新指令寄存器16的刷新指令REF2加到判优器15。 [0191] A read from the instruction register command signal RA2 17 and a write command signal WA2, read instruction signal 18 RB2 and a write command signal WB2 from the command register B, and from the refresh command register 16, a refresh command REF2 applied to arbitration 15. 对于由选择5个指令信号中的2个得到的全部10个组合,10个比较器80-1到80-10根据指令到达的定时确定哪一个指令比另一个早。 For the five selection instruction signal 2 obtained all 10 combinations, 10 comparators 80-1 through 80-10 determines which instruction reaches an instruction based on the timing earlier than the other.

[0192] 每个比较器比较2个指令的定时,将各输出中的一个设置在HIGH(高),它与在其它输入前已经接收了HIGH的输入相应。 [0192] Each comparator compares the two instruction timings, each one of the outputs provided on HIGH (high), it has been received before the other input of the corresponding input HIGH. 例如,比较器80-1到80-4中的每一个确定来自A 端口11的读指令信号RA2或4个其它的指令中对应的一个中哪一个是较早的。 For example, the comparator 80-1 to 80-4 in each of the read-command signal RA2 determination or four other instructions from the A port 11 of a corresponding one of which is the earlier. 如果读指令信号RA2比4个其它的指令中的任何一个早,则将从AND电路81_1输出的读指令信号RA31设置在HIGH。 If the read-command signal RA2 than four other commands in any one of the early, then from the read command signal RA31 AND circuit 81_1 output is set in HIGH. 当RESETl信号是LOW(低)时,从判优器15将这个读指令信号RA31力口到DRAM芯14作为读指令信号RA3。 When RESETl signal is LOW (low) from the arbiter 15 will force the read command signal RA31 mouth DRAM core 14 as a read command signal RA3.

[0193] 当DRAM芯14接收指令时,DRAM芯14产生是HIGH的RESETl信号。 [0193] When the DRAM core 14 receives instructions, DRAM core 14 generates a RESETl signal is HIGH. 由倒相器85 到87,NAND电路88和倒相器89将这个RESETl信号变换成脉冲信号,并加到AND电路83_1 到83-5。 Inverter 85 through 87, NAND circuit 88 and inverter 89 this RESETl signal is converted into a pulse signal, and applied to the AND circuit 83_1 to 83-5. 当Read指令信号RA31是HIGH时,例如,通过延迟电路84_1产生使其中具有接收至_指令的指令寄存器复位的信号。 When the Read command signal RA31 is HIGH, for example, generated by the delay circuit 84_1 to make _ having received instruction instruction register reset signal.

[0194] 图7是表示判优器15的操作的定时图。 [0194] FIG. 7 shows arbiter 15 is a timing chart.

[0195] 具有图7中列举的名字的信号表示在图6A的各位置中。 Signal [0195] FIG. 7 has listed the names of representation at each position of FIG. 6A. 图7是表示当将Read指令加到A端口11和B端口12上时判优器15的操作。 Figure 7 shows the operation when Read commands are supplied to the arbiter 15, 11 and 12 when the B port A port. 如图7所示,选择与A端口11对应的Read指令RA2作为具有优先权的指令,从而产生RA31,使得芯电路实施读操作READ-A。 7, the selection and the A port 11 in FIG Read command RA2 corresponding to the instruction as having priority, thereby generating RA31, so that the core circuit performs a read operation READ-A. 响应由此产生的复位信号RESETl,使读指令信号RA2复位。 Thereby generating a reset signal in response to RESETl, the read command signal RA2 is reset. 对应地,选择与B端口12对应的Read指令RB2,从而产生RB31。 Correspondingly, select the B port 12 corresponding to a Read command RB2, thereby generating RB31. 当复位信号RESETl变成LOW时,将读指令信号RB3加到芯电路,从而执行读操作READ-B。 When the reset signal RESETl becomes LOW, the read command signal RB3 is applied to the core circuit, thereby performing a read operation READ-B.

[0196] 图8是与输入到一个DRAM芯14的地址有关的电路方框图。 [0196] FIG. 8 is a block diagram of the address input to a DRAM core 14 of the associated circuits.

[0197] A端口11的地址缓冲器;34包括输入缓冲器;34-1,传输门;34_2和0R( “或”)电路34-3。 Address buffer [0197] A port 11; 34 includes an input buffer; 34-1, a transfer gate; 34_2 and 0R ("or") circuit 34-3. 加入具有与从图5所示的指令译码器62输出的读指令信号RAl的前沿对应的脉冲的脉冲信号作为加到OR电路34-3的一个输入端的RA1P。 Accession has the leading edge of the read instruction signal from the instruction decoder 62 RAl output shown in Figure 5 corresponds to a pulse of the pulse signal is applied to the OR circuit 34-3 as an input RA1P. 进一步,加入具有与从图5所示的指令译码器62输出的写指令信号WAl的前沿对应的脉冲的脉冲信号作为加到OR电路34-3的另一个输入端的WA1P。 Further, the write command signal having added WAl pulses corresponding to the leading edge of the pulse signal from the instruction decoder 62 shown in FIG. 5 as the output is applied to the other input terminal of the OR circuit 34-3 WA1P. 下文中,在它的信号名称的未端具有字母“P”的信号代表具有从对应的信号名称的信号的前沿产生的脉冲的信号。 Hereinafter, in the end it did not signal the name has the letter "P" signal represents a pulse signal from the leading edge signal corresponds to the name of the generated signal.

[0198] B端口12的地址缓冲器44包括输入缓冲器44_1,传输门44_2和OR电路44_3。 [0198] The address buffer 12 of 44 B port includes an input buffer 44_1, a transfer gate 44_2 and OR circuit 44_3.

[0199] 地址寄存器A 20包括地址锁存器101,传输门102,地址锁存器103,传输门104, 传输门105,地址锁存器106,和传输门107。 [0199] address register A 20 102, address latch 103, transfer gate 104, transfer gate 105, address latch 106, and the transfer gate includes an address latch 101, transfer gate 107. 进一步,地址寄存器B 21包括地址锁存器111,传输门112,地址锁存器113,传输门114,传输门115,地址锁存器116,和传输门117。 Further, the address register B 21 includes an address latch 111, transfer gate 112, address latch 113, transfer gate 114, transfer gate 115, address latch 116, and the transfer gate 117.

[0200] 刷新地址寄存器19包括刷新地址计数器/寄存器19-1,倒相器19-2,和传输门19-3。 [0200] refresh address register 19 includes a refresh address counter / register 19-1, inverter 19-2, and the transfer gate 19-3. 由刷新地址计数器/寄存器19-1产生和保持刷新地址。 19-1 to generate and maintain a refresh address from the refresh address counter / register.

[0201] 通过上述电路配置的操作,当从器件外输入Read指令或feite指令时,将与指令一起进入的地址传输到地址锁存器101或111。 [0201] The operation of the circuit configuration, when the input feite Read instruction or instruction from outside the device, will together with the command to enter the address transmitted to the address latch 101 or 111. 在Read指令的情形中将地址传输到地址锁存器105或116而不需任何时间操作。 In the case of a Read command in the address transmitted to the address latch 105 or 116 without any time operation. 在Write指令的情形中在取得一系列写数据的最后一个数据的定时将地址传输到地址锁存器103或113。 In the case of a Write command of writing data in the acquired series of the timing of the last data transfer address to the address latch 103 or 113.

[0202] 如图8的电路配置所示,响应与各从判优器15传输到DRAM芯14的指令信号RA3, WA3, RB3,WB3和REF3对应的脉冲信号RA3P,WA3P, RB3P,WB3P和REF3P,将地址信号从一个地址锁存器传输到DRAM芯14。 Circuit Configuration [0202] FIG. 8, in response to each transmitted from the arbiter 15 to the DRAM core command signal RA3 14's, WA3, RB3, WB3, and REF3 corresponding pulse signal RA3P, WA3P, RB3P, WB3P and REF3P the address signal is transmitted from an address latch to the DRAM core 14.

[0203] 图9是与数据输出有关的电路方框图。 [0203] FIG. 9 is a circuit block diagram of the data output related.

[0204] 与数据I/O电路33的数据输出有关的部分包括数据锁存器121,传输门122,数据锁存器123,并行串行变换器124,输出缓冲器125和传输信号发生电路126。 [0204] the data output of data I / O circuit 33 includes a part relating to data latch 121, transfer gate 122, a data latch 123, a parallel-serial converter 124, an output buffer 125 and the transmission signal generating circuit 126 . 而且,与数据I/O电路43的数据输出有关的部分包括数据锁存器131,传输门132,数据锁存器133,并行串行变换器134,输出缓冲器135和传输信号发生电路136。 Further, the data output of data I / O circuit 43 includes a part relating to data latch 131, transfer gate 132, a data latch 133, a parallel-serial converter 134, an output buffer 135 and the transmission signal generating circuit 136.

[0205] 从存储器阵列51读出的数据被读出缓冲器55放大,分别通过传输门A 24或传输门B 25加到数据I/O电路33或数据I/O电路43。 [0205] read out from the memory array 51 data is read out to enlarge the buffer 55, respectively, through the transfer gate A 24 or B 25 to the data transfer gate I / O circuit 33 or data I / O circuit 43. 如果执行的指令与从A端口11的数据读出有关,则传输门AM打开,而如果执行的的指令与从B端口12的数据读出有关,则传输门B 25打开。 If the instruction is executed and the data from the A port 11 is read out, the transfer gate AM open and instructions if you are performing with the B data read out from the port 12, the transfer gate B 25 is opened. 以这种方式提供的数据被数据锁存器121或131锁存和保持。 Data provided in this manner is 121 or 131 data latch latches and retention.

[0206] 传输门122或132响应从传输信号发生电路1¾或136提供的传输信号在一个相应的端口接收读指令后打开预定等待时间。 [0206] transmission gate 122 or 132 response from the transmission signal generating circuit 136 1¾ or transmission signals supplied in a corresponding port receives a read command to open a predetermined waiting time. 于是分别将数据锁存器121或131的数据传输到数据锁存器123或133。 So are the data transfer latch 121 or 131 to the data latch 123 or 133. 此后用并行串行变换器IM或134将数据从并行数据变换到串行数据。 Thereafter IM or with parallel-serial converter 134 converts the data from parallel data to serial data. 然后将该数据传输给输出缓冲器125或135,并从那里输出。 This data is then transferred to the output buffer 125 or 135, and output from there.

[0207] 图10是表示传输信号发生电路126或136的配置的电路图。 [0207] FIG. 10 is a circuit diagram showing a circuit configuration 126 or 136 of the transmission signal occurs.

[0208] 传输信号发生电路1¾或136包括触发器141到144和多路复用器145。 [0208] 1¾ or transmission signal generating circuit 136 includes a flip-flop 141-144 and the multiplexer 145. 将读指令信号RAl或RBl加到触发器141,并连续地与时钟信号CLKAl或CLKBl同步地从一个触发器传输到下一个。 The read command signal to the flip flop 141 RAl or RBl and continuously with the clock signal CLKAl or CLKBl synchronously transmitted from a trigger to the next. 将等待时间信息A和B加到多路复用器145。 The latency information A and B is applied to the multiplexer 145. 这个等待时间信息例如用时钟周期的数目确定等待时间的长度。 This latency information such as the length of waiting time is determined by the number of clock cycles. 根据等待时间信息,多路复用器145选择一个相应的触发器的Q输出,并将它作为数据传输信号输出。 According latency information, the multiplexer 145 to select a corresponding Q output, and output it as a data transmission signal.

[0209] 图11是与数据输入有关的电路方框图; [0209] FIG. 11 is a circuit block diagram relating to the data input;

[0210] 与数据I/O电路33的数据输入有关的部分包括数据输入缓冲器151,串行并行变换器152和数据传输装置153。 [0210] and data I / O circuit 33 includes a data input section relating to data input buffer 151, a serial to parallel converter 152 and a data transmission device 153. 与数据I/O电路43的数据输入有关的部分包括数据输入缓冲器154,串行并行变换器155和数据传输装置156。 Data and data I / O circuit 43 includes a data input portion relevant input buffer 154, a serial parallel converter 155 and a data transmission device 156.

[0211] 分别用串行并行变换器152或155将串行地输入到数据输入缓冲器151或IM的数据变换成并行数据。 [0211] respectively parallel serial converter 152 or 155 to the serial data input to the data input buffer 151 or the IM is converted into parallel data. 当输入最后一个数据时,将并行数据传输到写数据寄存器A 22或写数据寄存器B 23。 When you enter the last data, the parallel data transfer to write data register A 22 or write data register B 23. 当将Write指令从判优器15传输到DRAM芯14时,响应表示与^^切指令到DRAM芯14的传输相应的定时的信号WA3P或WB3P,将写数据寄存器A 22或写数据寄存器B 23的数据传输到DRAM芯14。 When the Write command 14, the response represents ^^ cut directives to the DRAM core 14 corresponding to the timing of the transmission signal WA3P or WB3P from arbiter 15 is transmitted to the DRAM core, the write data register A 22 or write data register B 23 data transfer to the DRAM core 14.

[0212] 图12是表示当连续进入Read指令时实施的操作的定时图。 [0212] FIG. 12 is a timing chart showing the operation when continuously implemented into the Read instruction. [0213] A端口11和B端口12分别与具有不同频率的时钟信号CLKA和CLKB同步地操作。 [0213] A port 11 and the B port 12 operate in synchronization with the clock signal CLKA and CLKB having different frequencies respectively. 在这个例子中,A端口11用最大时钟频率操作,而B端口12用较低的时钟频率操作。 In this example, A port 11 with a maximum clock frequency, and the B port 12 with a lower clock frequency.

[0214] A端口11具有下列设置:读指令周期=4(CLKA),数据等待时间=4,和脉冲串长度=4。 [0214] A port 11 with the following settings: read-command cycle = 4 (CLKA), data latency = 4, and burst length = 4. B端口12具有下列设置:读指令周期=2(CLKA),数据等待时间=2,和脉冲串长度=2。 B port 12 with the following settings: read-command cycle = 2 (CLKA), data latency = 2, and burst length = 2. 在每个端口的模寄存器中设置数据等待时间和脉冲串长度。 Setting data latency and a burst length in each port mode register.

[0215] 将由端口接收的指令存储在各指令寄存器中。 [0215] by the receiving port instructions stored in the instruction register. 将刷新指令存储在刷新指令寄存器中。 The refresh command is stored in the refresh command register. 判优器监视这些指令寄存器,并以接收指令的次序将指令传输给DRAM芯。 The arbiter monitors these command registers, and in order to receive commands transmitted to the DRAM core instruction. 当完成上一个指令的处理时传输下一个指令。 When processing transfer on completion of a command to the next command.

[0216] 将从DRAM芯读出的数据从读出缓冲器传输到各端口数据锁存器(请参见图9)。 [0216] from a DRAM core data read out from the readout buffer transfer to the respective port data latch (see Figure 9). 以后将数据从并行变换成串行,作为脉冲串输出与外部时钟同步地输出。 After the data is converted from parallel to serial output as a pulse train output in synchronization with the external clock.

[0217] 虽然曾经从A端口输入刷新指令,但是不影响B端口的操作,如图12所示。 [0217] Although the refresh command has been input from port A, but does not affect the operation of the B port, shown in Figure 12.

[0218] 图13是表示当连续输入Write指令时实施的操作的定时图。 [0218] FIG. 13 is a timing chart showing an operation performed when Write commands are input continuously implemented.

[0219] 在写操作时从器件外部输入的数据取脉冲串输入的形式。 [0219] In the write operation data input from the external device takes the form of a pulse train input. Write指令存储在写指令寄存器中的定时是输入脉冲串输入的最后一个数据的定时。 Write command is stored in the timing of the write command register is the timing of the last data of the input pulse train input.

[0220] 如图13所示,从A端口提供的刷新指令不影响B端口的操作。 As shown in [0220] FIG. 13, the refresh command from A port provided does not affect the operation of the B port.

[0221] 图14是表示当A端口和B端口两者都操作在最大时钟频率上时的定时图。 [0221] FIG. 14 is a timing chart when both the A port and the B port operate at the maximum clock frequency.

[0222] 如图14所示,在这些端口的时钟信号之间可能存在相位差。 [0222] 14, may exist between the clock signals of these ports as shown in the phase difference. 两个端口具有下列设置:读指令周期=4,数据等待时间=4,和脉冲串长度=4。 Two ports have the following settings: read-command cycle = 4, data latency = 4, and burst length = 4. 如从图可见的那样,甚至当两个端口都操作在最大时钟频率和连续输入Read指令时关于操作也没有问题。 As seen in the figure above, even when both ports operate at the maximum clock frequency and continuous input Read the instruction on the operation there is no problem.

[0223] 图15是表示当A端口和B端口两者都操作在最大时钟频率上时的定时图。 [0223] FIG. 15 is a timing chart when both the A port and the B port operate at the maximum clock frequency. 在图15中,两个端口连续地接收Write指令。 In Figure 15, both ports receive continuously Write commands.

[0224] 如图15所示,在这些端口的时钟信号之间可能存在相位差。 [0224] As shown in Figure 15, there may be a phase difference between the clock signals of these ports. 两个端口具有下列设置:写指令周期=4,数据等待时间=4,和脉冲串长度=4。 Two ports have the following settings: Write command cycle = 4, data latency = 4, and burst length = 4. 如从图可见的那样,甚至当两个端口都操作在最大时钟频率和连续输入Write指令时也能够进行适当的操作。 As seen in the figure above, even when both ports operate at the maximum clock frequency and continuous input Write instruction can be carried out appropriately.

[0225] 图16是表示当指令从Read指令改变到Write指令时的各操作的定时图; [0225] FIG. 16 is changed when the instruction from the Read instruction to each timing chart showing an operation when Write instruction;

[0226] 如图16所示,当与Irite — Read”或“Read — Write"的指令间隔比较时指令传输“feite —Read”需要一个额外的指令间隔。这是因为我们传输Write指令以便在当进入脉冲串输入的最后一个数据时的定时对它进行处理。相反地,为了对它进行处理传输一个Read指令的定时定义为进入Read指令的定时,使得当相继的指令是“Write — Read"时需要提供一个额外的指令间隔。这样一个需要可以认为是将取脉冲串输入形式的输入数据变换成并行数据这个事实引起的。如果只输入一块数据而不是如脉冲串输入那样输入4块数据,则甚至当两个相继的指令都是“Write — Read”时也不需要提供一个额外的指令间隔。 [0226] As shown in FIG. 16, when the Irite - "Compare instruction command interval transmission" Write feite -Read "needs an extra command interval because we Write command is transmitted to when the - Read" or "Read. When - "Read Write" to enter the last data burst input timing of when it processed the contrary, in order to define its processing and transmission timing for a Read instruction Read instruction is clocked into, so that when the subsequent instruction is. the need to provide an extra command interval. Such a need can be considered converting the input data take the form of a burst input into parallel data caused by the fact that if only one data input instead of four as input data such as pulse train input, then Even when two successive commands are "Write - Read" time does not need to provide an extra command interval.

[0227] 在这种如对于一个Write写指令只输入一块数据那样的配置中,即便用与"Write — feite”或“Read — Read”的情形中相同的指令间隔,也能够对于“feite — Read,, 指令连续性适当地进行操作。 [0227] In such a configuration such as for a write command Write enter only one piece of data, even with the "Write - feite" or "Read - Read" The situation in the same command interval, it is possible to "feite - Read ,, instructions continuity operate properly.

[0228] 图17是表示当指令从“Read”改变到'Irite”时输入刷新指令的定时图。 [0228] FIG. 17 is a refresh command input when the instruction from the "Read" changed to 'Irite "the timing diagram.

[0229] 在图的顶部,表示出应该进入刷新指令的定时。 [0229] In the top of the figure, showing the timing of a refresh command should be entered. 在如说明的期间中在任何定时都能适当地进入刷新指令。 As illustrated during any timed refresh command can properly enter. 例如,即便在图17所示的定时输入刷新指令,刷新指令只有当完成前一Awrite写指令时才开始刷新操作,直到将刷新指令保存在备用状态时为止。 For example, even if the timing of the input shown in FIG. 17 refresh command, refresh command only when the write command is completed before the start of a Awrite refresh operation until the date when the refresh command is stored in a standby state. 因此,只要刷新指令落在与这个备用状态对应的期间内在任何定时都能适当地进入刷新指令。 Therefore, as long as the internal refresh command falls during this standby state corresponding to any timing can properly enter the refresh command.

[0230] 图18是表示当使一个端口去激活时实施的操作的定时图; [0230] FIG. 18 is a timing diagram showing the operation when one of the ports is deactivated when implemented;

[0231] 如图18所示,当使一个端口(即,图18中的A端口)去激活时,根据刷新定时器内部产生刷新指令,从而执行刷新操作。 [0231] 18, when the one port (ie, in FIG. 18 A port) are deactivated, according to the refresh timer generates a refresh command inside, thereby executing a refresh operation.

[0232] 图19是表示当使两个端口去激活时实施的操作的定时图。 [0232] FIG. 19 is a timing chart showing the operation when the two ports are deactivated implementation.

[0233] 如图19所示,当使两个端口去激活时,根据刷新定时器内部产生刷新指令,从而执行刷新操作。 [0233] As shown in Figure 19, when the two ports are deactivated, a refresh command is based on an internal refresh timer, thereby executing a refresh operation.

[0234] 图20A和20B是表示DRAM芯操作的定时图。 [0234] FIG. 20A and 20B is a timing chart DRAM core operations.

[0235] 图20A表示读操作的情形,图20B表示写操作的情形。 [0235] FIG. 20A shows the case of a read operation, FIG. 20B shows the case of a write operation. 在如图20A和20B所示的操作定时,在完成整个操作前通过字线选择,数据放大,写回,和预充电的相继操作发出进入的指令。 Timing of operations as shown in FIG. 20A and 20B, before the completion of the entire operation by word line selection, data amplification, write-back, and subsequent operation enters precharge command is issued.

[0236] 图21是表示当只使一个端口操作时实施的两倍速率操作的定时图; [0236] FIG. 21 is a timing chart showing double-rate operation when only the implementation of a port operation;

[0237] 通过使两个端口中的一个停止操作,可以将到操作端口的指令输入间隔缩短一半。 [0237] by the two ports in a stop operation, can be input to the instruction port halved interval. 当这种情形发生时,外部指令的最快周期和内部动作的最快周期彼此相同。 When this happens, the fastest cycle of external commands and the fastest cycle of internal actions are identical. 在图21的例子中,缩短了指令间隔而没有改变时钟频率。 In the example of FIG. 21, the instruction interval shortened without changing the clock frequency. 在这个情形中,因为脉冲串长度也变得较短,所以数据传输速率与当用两个端口时的相同。 In this case, since the burst length also becomes shorter, so the data transfer rate and when the two ports are identical.

[0238] 图22是表示当通过使时钟频率两倍高使数据传输速率两倍时两倍速率操作的定时图; [0238] FIG. 22 is a view showing a frequency twice as high by the clock rate is twice the data transfer rate is twice the operation timing chart;

[0239] 在图22中,当使两个端口中的一个停止操作时,将输入到操作端口时钟信号设置在高两倍的频率上。 [0239] In FIG. 22, when the two ports of a stop operation, the input clock signal to the operating port is provided on the frequency twice as high. 与此相关,指令输入的时间间隔缩短一半。 Related to this, the time interval between command input halved. 在这个情形中,因为脉冲串长度与当用两个端口时的相同,所以数据传输速率为当用两个端口时的两倍那样快。 In this case, since the burst length and twice when two ports are the same, so the data transfer rate when using two ports as quickly.

[0240] 此外,因为只将外部时钟信号输入I/O电路装置,所以如果将该电路装置设计得能应付高速操作则实际上容易完成两倍速率操作。 [0240] In addition, since only the external clock signal input I / O circuit means, so that if the circuit arrangement is designed to cope with high-speed operation is easily accomplished virtually double the rate of the operation.

[0241 ] 图23是用于解释本发明的第2实施例的图; [0241] FIG. 23 is a diagram for explaining the present invention, a second embodiment;

[0242] 一般,根据其用度扩大存储器。 [0242] In general, expanded memory according to its costs. 这同样应用于多端口存储器的情形,可能存在为了扩大存储空间提供多个多端口存储器的情形。 The same applies to the case of multi-port memory, there may be provided in order to expand the storage space of a plurality of multi-port memory situations.

[0243] 多端口存储器包括判优器,并检测哪一个指令较早进入各端口,接着以检测出的次序执行指令。 [0243] multi-port memory includes an arbiter, and detects which instruction early entry into the ports, followed by executing the instruction sequence detected. 甚至当在几乎相同的定时将指令输入各端口时,也为相继地执行指令确定一个次序。 Even when at almost the same timing of each command input port for successively determining an order execution of instructions. 在图23所示的例子中,提供多个多端口存储器200-1到200-n,从A端口控制器201和B端口控制器202,将相同的指令加到多端口存储器200-1到200_n。 In the example shown in FIG. 23, a plurality of multi-port memories 200-1 to 200-n, from A port controller 201 and the B port controller 202, the same instruction is applied to multi-port memory 200-1 to 200_n . 即便同时将指令加到A端口和B端口,由于信号线有不同的长度和/或电源噪声的影响,指令到达每个多端口存储器的相对定时也可能稍有不同。 Even while the instruction is applied to the A port and the B port, since the signal line has the effect of different lengths and / or power supply noise, instruction reaches the relative timing of each multi-port memory may be slightly different. 在这个情形中,每个多端口存储器的判优器能够以从存储器到存储器不同的次序执行指令。 In this case, each of the multi-port memory arbiter can from memory to memory in a different order execution of instructions.

[0244] 如果到A端口的指令和到B端口的指令指向不同的地址,则存储器件之间执行指令的不同次序可能不会成为一个问题。 Execution of instructions between [0244] A port if the instruction and the instruction B port are directed to different addresses, the memory device in a different order might not be a problem. 然而,当各指令是对于同一个地址时,就会发生问题。 However, when each instruction is for the same address, a problem arises.

[0245] 例如,在当写存取同一个存储单元后读出数据时与当写存取同一个存储单元前读出数据时之间检索的数据是不同的。 [0245] For example, when the post-write access to the same memory cell data is read and write access to data when the same storage unit before reading data retrieval between different. 而且,当在写入A端口的数据后写入B端口的数据时B 端口的数据保留在存储器中,而如果以相反的次序进行操作则A端口的数据保留在存储器中。 Moreover, when data is written after a write A port B port B port data is retained in memory, and if the data in the reverse order to operate the A port is retained in memory.

[0246] 如果以上面描述的方式从存储器到存储器执行指令的次序不同,则关于数据的可靠性就存在严重的问题。 [0246] In the manner described above, if the order of execution of instructions from memory to memory is different, about the reliability of data there is a serious problem.

[0247] 因此,当用多个多端口存储器时,需要使判优器作出的决定在存储器之间保持一致。 [0247] Accordingly, when a plurality of multi-port memory, you need to make the decision made by the arbiter consistent between memory. 为此,本发明的第2实施例指定多端口存储器中的一个为主器件200-1,并用其余的器件作为从器件200-2到200-n。 For this reason, the second embodiment of the present invention to specify a multi-port memory of a master device 200-1, and with the rest of the device as a slave device 200-2 to 200-n. 从器件遵守由主器件的判优器作出的决定。 Abide by the decision by the arbiter of the master device to the slave.

[0248] 图M是表示根据本发明的多端口存储器的第2实施例的方框图。 [0248] FIG M is a block diagram according to the second embodiment of the multi-port memory of the present invention. 本例子的配置具有两个端口即A端口和B端口。 Examples of this configuration has two ports A port and the B port.

[0249] 与图4所示的第1实施例的不同包括A端口IlA和B端口12A分别具有BUSY信号I/O装置36和46这个事实和提供地址比较器沈比较A端口的地址和B端口的地址这个事实。 [0249] and the first embodiment shown in FIG. 4 different port IlA include A and B ports 12A respectively BUSY signal I / O devices 36 and 46 of this fact and provide an address comparator Shen compare A and B port address port The address of this fact. 如果地址比较器沈检测出地址匹配,因此产生匹配信号,则判优器15A将转变DRAM 芯的操作模式以便开始连续模式。 If the address comparator detects the address matching sink, thus producing a match signal, the arbiter 15A will change the operation mode of the DRAM core to begin continuous mode.

[0250] 图25A和25B是用于解释连续模式的定时图。 [0250] FIGS. 25A and 25B is a timing chart to explain the continuous mode.

[0251] 如图(图20)表示的第1实施例的操作所示,将DRAM芯的操作分成R0W(行)操作和C0LUMM(列)操作。 Operation of the first embodiment shown in [0251] As shown (Figure 20), and the DRAM core operation into R0W (row) Operation and C0LUMM (column) operation. 在本发明中,进行ROW操作,COLUMM操作和预充电操作作为一系列的连续执行操作,这定义了单个内部操作周期。 In the present invention, a ROW operation performed, COLUMM operation and precharge operation performed continuously as a series of operations, which defines a single internal operation cycle.

[0252] 在第2实施例中的连续模式与通常的DRAM的列存取操作相同,对于同一个存储单元反复执行一个指令。 [0252] In the continuous mode of the second embodiment and the DRAM column access operation is typically the same, for the same storage unit repeatedly execute an instruction. 即,这个模式在ROW操作后多次执行COLUMM操作后进行预充电。 That is, after this operation mode execution COLUMM several ROW operation after the precharge. 当连续地加上对同一个存储单元地址的Write指令时,执行后面的指令而不执行前面的指令。 When continuously adding to the same memory cell address of Write instruction, instructions are executed without executing the preceding instruction. 这是因为即便相继地执行了这些Write指令,由前面的指令写入的数据将被后面的指令的数据覆盖。 This is because even if these Write successively executed instructions, instruction written by the previous data will be overwritten later instruction data.

[0253] 如图25A所示,连续模式允许使操作缩短到比通常内部操作的2个周期短,从而提供额外的时间。 [0253] 25A, continuous mode allows the operator to shorten cycle is usually shorter than the two internal operations, thereby providing additional time. 将由这个额外时间得到的边边缘分配给在ROW操作和COLUMM操作之间的一个点(下文中将这个边缘称为Wait (等待)期间)。 Obtained by the side edge of the extra time allocated to operations and COLUMM ROW operation between a point (hereinafter, referred to as the edge of the Wait (waiting) period). 在这个Wait期间中,实施用于使主器件和从器件之间的指令执行次序一致的处理。 Wait in this period, the implementation and execution to enable the master order processing from instruction consistent between devices.

[0254] 下面,我们说明用BUSY信号使主器件和从器件之间的操作一致的过程。 [0254] In the following, we illustrate with BUSY signal to the master and slave operation of the device between the consistent process.

[0255] 为了保证在主器件和从器件之间有相同的指令执行次序用BUSY信号。 [0255] In order to ensure that the master and slave have the same instruction execution order with BUSY signal between devices. BUSY信号I/O装置36和46用作输出主器件200-1中的BUSY信号的BUSY输出电路,和用作在从器件200-2到200-n中接收BUSY信号的BUSY输入电路。 BUSY signal I / O devices 36 and 46 are used as the output of the master device 200-1 BUSY BUSY signal output circuit, and is used as a BUSY signal received from the device 200-2 to 200-n in BUSY input circuits. 将指示主器件标识或从器件标识的信息存储在模寄存器31或41中。 The master identification or indication from the information storage device identified in the mode registers 31 or 41.

[0256] 存储器件接收来自一个端口的指令,开始如图20A和20B所示的操作。 [0256] memory device receives an instruction from the operation port, beginning in FIG 20A and FIG 20B.

[0257] 当从其它的端口输入指令,存取在ROW操作期间内的同一个地址时,地址比较器26产生一个匹配信号。 [0257] When the input instruction from other ports, access during ROW operations in the same address, the address comparator 26 signals a match. 在重复这个匹配信号时,判优器15A向DRAM芯14的控制电路53提供连续模式信号。 When repeating this match signal, the arbiter 15A provides a continuous mode signal to the control circuit 14 of the DRAM core 53. 响应连续模式信号,DRAM芯14转移到连续模式如图25B所示。 In response to the continuous mode signal, DRAM core 14 is transferred to the continuous mode shown in Figure 25B.

[0258] 在Wait期间中,主器件200-1根据判优器15A作出的决定产生BUSY-A信号或BUSY-B信号。 [0258] During Wait, the master device 200-1 generates BUSY-A signal or BUSY-B signal based on the decision made by the arbiter 15A. 在这个例子中,对于一个被判优器ISA识别的较早已经收到指令的端口产生BUSY信号。 In this example, for a recognized arbiter ISA older generation has received instruction port BUSY signal.

[0259] 类似地,在Wait期间中,从器件检测由主器件产生BUSY信号,改变由它自己的判优器15A作出的决定,以便如果它不同于BUSY信号的指示就遵从主器件。 [0259] Similarly, during Wait detected BUSY signal generated by the master device, to change the decision by its own arbiter 15A made so that if it is different from the BUSY signal indicates to comply with the master. 然后根据改变了的指令次序实施COLUMM操作。 Then according to the instructions to change the order of implementation COLUMM operation.

[0260] 图沈是表示当对于A端口的Read指令和B端口的feite指令产生BUSY信号时实施的操作的定时图。 [0260] FIG Shen is a timing chart showing the operation when the instruction for feite A port and B port Read instruction generating BUSY signal.

[0261] 在这个实施例中,BUSY信号具有一个指示选择的逻辑级“L”。 [0261] In this embodiment, BUSY signal having a selected logic level indicating "L". 而且,优先地传输和非同步地接收BUSY信号。 Moreover, priority transmission and non-received BUSY signal synchronization. 这是因为需要在有限的Wait期间内迅速地交换BUSY信号。 This is because of the need to exchange the BUSY signal within a limited Wait period rapidly.

[0262] 在图沈的例子中,因为A端口的ReadA2比B端口的feiteB2早,所以主器件在Wait期间中产生指示A端口的BUSY信号。 [0262] In the example of FIG sink because feiteB2 ReadA2 A port B port is earlier than that, so the master generates a BUSY signal indicative of the A port during the Wait. 从器件接收这个BUSY信号,并依靠A端口的ReadA2比B端口的feiteB2早。 Slaves receive this BUSY signal, and rely on the A port ReadA2 earlier than feiteB2 B port. 然后,主器件和从器件以首先ReadA2然后feiteB2的次序执行在连续模式中的列操作。 Then, the master and slave to first ReadA2 then feiteB2 column operations in order to perform continuous mode.

[0263] 图27是表示当对于A端口的Read指令和B端口的feite指令产生BUSY信号时实施的操作的定时图。 [0263] FIG. 27 is a timing chart showing the operation when the instruction for feite A port and B port Read instruction generating BUSY signal. 而图26说明A端口的Read指令较早的情形。 And FIG. 26 illustrates Read instruction A port earlier situation. 图27表示B端口的Write指令较早的情形。 Figure 27 shows a Write command of the B port is earlier case.

[0264] 图28是表示当对于A端口的feite指令和B端口的feite指令产生BUSY信号时实施的操作的定时图。 [0264] FIG. 28 is a timing chart showing the operation when the instruction for feite A port and B port feite instruction generating BUSY signal.

[0265] 图28所示的操作例子是关于A端口的feite指令比B端口的feite指令早的情形。 Operation example shown in [0265] FIG. 28 is on the A port feite instruction earlier than feite instruction B port of the situation. 即,因为A端口的feiteA2比B端口的feiteB2早,所以产生指示A端口的BUSY信号, 并加到从器件上。 That is, since feiteB2 feiteA2 A port B port is earlier than that, so indicative of the A port BUSY signal and added to from the device. 在这种情形中,因为通过执行A端口的feite指令被写入的数据将立即被覆盖,所以只有B端口的写指令因为WriteB2因为它较后进入而被执行。 In this case, since the port A by executing feite instruction is written data will be overwritten immediately, so that only the B port write command WriteB2 because as it enters later is executed.

[0266] 图四是表示当对于A端口的feite指令和B端口的feite指令产生BUSY信号时实施的操作的定时图。 [0266] Figure IV is a timing chart showing the operation when the instruction for feite A port and B port feite instruction generating BUSY signal.

[0267] 图四所示的操作例子是关于B端口的feite指令比A端口的feite指令早的情形。 Operation example shown in [0267] Figure IV is earlier than feite instruction A port of the situation on the B port feite instructions. 在这种情形中,因为通过执行B端口的feite指令被写入的数据将立即被替代,所以只有A端口的写指令feiteA2被执行。 In this case, since the B port feite by executing instructions written data will immediately be replaced, so that only the A port feiteA2 write instruction is executed. 在这个例子中,将A端口的时钟频率设置得稍低于B端口的时钟频率。 In this example, the clock frequency of the A port is set to be slightly lower than the clock frequency of the B port. 虽然当比较指令WriteA2*feiteB2时对于A端口指令输入稍早,但是在接收最后一个数据输入时是B端口较早。 Although the B port when the comparison instruction WriteA2 * feiteB2 when A port for command input earlier, but in the last received data input earlier. 因此,确定B端口的feite指令比A端口的feite 指令早。 Therefore, to determine the B port feite instruction than feite instruction A port early.

[0268] 上面提供的描述还没有参考关于A端口的Read指令和B端口的Read指令的组合起来的情形。 The description provided [0268] The above has no reference on A port Read instruction Read instruction and B ports are combined situation. 因为不管相对的定时如何,数据的可靠性不受影响,所以在这个情形中不需要产生BUSY信号。 Because no matter how relative timing and reliability of the data is not affected, so in this case does not need to produce BUSY signal.

[0269] 图30是表示在能够处理由控制器发出的中断指令的配置中的操作的定时图。 [0269] FIG. 30 is a timing diagram can interrupt instruction issued by the controller configuration operations.

[0270] “中断指令”是当开始BUSY信号时指令改变由主器件的判优器作出的决定的指示。 [0270] "interrupt instruction" is an instruction when starting BUSY signal to change the decision by the master arbiter make the instructions. 造成中断的方法包括: Disruption methods include:

[0271] a)作为指令输入; [0271] a) as a command input;

[0272] b)提供专用的端子销; [0272] b) providing a dedicated terminal pin;

[0273] c)用特定的地址组合;和 [0273] c) a combination with a specific address; and

[0274] d)用BUSY 信号。 [0274] d) with the BUSY signal.

[0275] 方法d)用控制器对与为其产生BUSY信号的端口不同的端口提供BUSY信号,并安排主存储器和从存储器对它进行检测。 [0275] Method d) provide BUSY signal on a different port and its BUSY signal generated by the controller and arranged to detect from the main memory and the memory of it.

[0276] 在图30的例子中,当对于A端口的feite指令和B端口的feite指令发生BUSY信号时产生中断。 [0276] In the example of FIG. 30, an interrupt is generated when the instruction for feite A port and B port feite instruction occurs BUSY signal. 如将图28和图四结合起来进行的描述那样,当Write和feite的组合产生BUSY信号时只有A端口的feite指令和B端口的feite指令中的一个被执行。 As Fig. 28 and description of four combine as Write and feite when a combination of a BUSY signal only feite instruction A port and the B port feite instruction in an execution. 结果, 将失去较早进入的数据。 As a result, the loss of early entry into the data.

[0277] 在图30中,A端口的WriteA2比B端口的WriteB2早,使产生指向A端口的BUSY 信号。 [0277] In Figure 30, WriteA2 A port B port WriteB2 earlier than that generated point A port BUSY signal. 接收到主器件产生的BUSY信号后,控制器产生中断指令以便防止删除A端口的feite 数据。 After receiving the BUSY signal generated by the master, the controller generates an interrupt instruction to prevent deleted A port feite data.

[0278] 主器件和从器件从控制器接收中断指令,改变由判优器作出的决定,接着根据中断指令在等待期间结束后执行Write操作。 [0278] The master and slave receive interrupt instruction from the controller to change the decision made by the arbiter, then perform Write operation according to the interrupt instruction during the waiting period ends. 即,判优器改变它们的决定指出A端口的指令WriteA2比B端口的指令feiteB2晚,实施与WriteA2有关的写操作。 That is, the arbiter change their decision stated instruction than instruction WriteA2 A port B port feiteB2 night, implementation and WriteA2 related write operations. 这能够防止A端口的写数据被删除。 This can prevent the write data of the A port is deleted. 在Write — Write组合的情形中,全部需要只是执行写操作一次,使得可以分配比Read — Write组合或feite — Read组合的连续模式较长的等待期间。 In Write - Write combination of circumstances, but all need to perform a write operation, making it possible to allocate more than Read - Write combination or feite - Read the combined continuous mode waiting for a longer period. 于是可以利用这个等待期间响应BUSY信号执行中断指令。 So you can use this waiting period BUSY signal in response to an interrupt command execution.

[0279] 下面,我们描述用于实现上述操作的地址比较器,BUSY I/O系统和中断系统的配置。 [0279] In the following, we describe the operation for achieving the above address comparator, BUSY I / O system and the interrupt system configuration.

[0280] 图31是表示根据本发明的第2实施例的多端口存储器的地址比较器,BUSY I/O系统,和中断系统的配置的图。 [0280] FIG. 31 is a multi-port memory according to the second address comparator embodiment of the present invention, BUSY I / O system, and the interrupt system configuration diagram.

[0281] 地址比较器沈比较存储在地址寄存器中的地址,并当A端口11的地址和B端口12的地址之间存在匹配时输出匹配信号。 [0281] an address in the address register address comparators compare sink storage and output matching signal when there is a match between the address and the address of B A port 11 port 12. 而且,为了指出哪两个地址是匹配地址,产生信号ARA,AffA, ARB和AWB。 Moreover, in order to indicate which two addresses are matching addresses, a signal ARA, AffA, ARB, and AWB. 例如,当A端口的feite指令的地址和B端口的feite指令的地址显示匹配时,将AWA和AWB设置在“H”。 For example, when the instruction address feite A port address and B ports feite instructions show match, AWA and AWB is set in "H". NAND电路208到210每个都得到这些信号的一个逻辑NAND,使得附,N2和N3中的一个变成“L”。 208-210 each NAND circuit have been a logical NAND of these signals, so attached, N2 and N3 become an "L".

[0282] 在图31左边(在地址比较器沈的下面)提供了BUSY信号I/O装置36和46与中断电路。 [0282] In Fig. 31 on the left (in the following address comparator heavy) provides a BUSY signal I / O devices 36 and 46 and the interrupt circuit. 根据模寄存器31或41的设置,BUSY和I/O硬件控制装置211在主器件情形中响应匹配信号的检测产生激活信号(主),和在从器件情形中产生激活信号(从)。 According to a mode register set 31 or 41, BUSY, and I / O hardware control unit 211 in response to the detection of the match signal to generate an activation signal (master) in the case of the master device, and generating an activation signal (from) the slave situation. 激活信号(主)激活BUSY输出电路212和213,而激活信号(从)激活BUSY输入电路214和215。 Activation signal (master) activates BUSY output circuits 212 and 213, and an activation signal (from) activates BUSY input circuits 214 and 215.

[0283] 在判优器中,将选出的指令作为指令次序中的第一个输出到输出端RA3,WA3,RB3 和WB3中的一个(即输出端中的一个是“H”)。 [0283] In the arbiter, the selected instruction as the first instruction sequence to the output terminal RA3, WA3, RB3, and WB3 one (ie the output of one is "H"). 在主器件情形中,RA3到WB3被锁存器216 和217响应信号N4锁存起来,信号N4是由与匹配信号的前沿对应的脉冲组成的。 In the case of the master device, RA3 to WB3 are latched 216 and 217 latches the response signal N4, the signal N4 is the leading edge pulse corresponding match signal component. 根据锁存的数据输出BUSY-A信号和BUSY-B信号。 BUSY-A signal output and BUSY-B signal based on the latched data.

[0284] 在从器件情形中,如果接收到是“L”的BUSY-A信号,则将从中断电路218输出的信号NlO设置在“L”。 [0284] In the slave case, if the received is "L" of the BUSY-A signal will be output from the signal NlO 218 interrupt circuit is set in the "L". 如果接收到是“L”的BUSY-B信号,则将从中断电路219输出的信号Nll设置在“L”。 If you receive a "L" of the BUSY-B signal, then the output circuit 219 from interrupt signal Nll provided in "L". 当信号NlO和Nll处于去激活状态时,它们是“H”,当检测出BUSY信号或中断指令时它们变成“L”。 When the signal NlO and Nll in a deactivated state, which is "H", when detecting BUSY signal or interrupt instruction they become "L".

[0285] 中断检测装置220检测从控制器提供的中断指令,并输出中断信号A或B。 [0285] detection means 220 detects the interruption command supplied from the controller, and outputs an interrupt signal A or B. 给予中断信号对进入的BUSY信号的优先权,并将它们作为信号NlO和Nll传输出去。 Giving an interrupt signal to the incoming BUSY signal priority, transfer them out as a signal NlO and Nll.

[0286] 图31底部所示的三个比较器80-3,80-5和80_6是判优器15A的比较电路的一部分(请参见图6A和图24)。 Three comparators [0286] FIG. 31 shown at the bottom 80-3,80-5 and 80_6 is part (see Figure 6A and FIG. 24) of the comparator circuit 15A of arbiter. 这些比较器对于需要BUST确定的指令组合进行比较。 These comparators BUST determine the need for instruction combination were compared.

[0287] 图32是表示一个主器件的操作的定时图。 [0287] FIG. 32 is a timing chart showing the operation of a master. 图33是表示一个从器件的操作的定时图。 FIG. 33 is a timing chart showing the operation of the device. [0288] 这三个定时图说明A端口的Read指令的地址和B端口的feite指令的地址相互匹配的情形。 Address [0288] a timing diagram illustrates the three ports A and B Read the instruction address port feite instruction matched case. 图32的主器件决定A端口较早,图33的从器件决定B端口较早。 Figure 32 Master A port is earlier decision and decided to B port from the device of FIG. 33 earlier. 在这种情形中,主器件的比较器80-3输出是“L”的N21和是“H”的N22。 In this case, the output of the master comparator 80-3 is "L" of the N21 and the "H" of the N22. 进一步,从器件的比较器80-3输出是“H”的N21和是“L”的N22。 Further, the output from the comparator device 80-3 is "H" of the N21 and the "L" of the N22. 主器件产生BUSY-A信号,从器件在接收BUSY-A信号时将NlO改变成“L”。 Master generates a BUSY-A signal from the device upon receiving the NlO BUSY-A signal is changed to "L". 因为在这个时间点m是“L”,所以通过NOR(“或非”)电路221和倒相器222将WO的LOW信号加到从器件的比较器80-3上。 Because at this point in time m is "L", so by NOR ("NOR") circuit 221 and inverter 222 WO a LOW signal is applied from the comparator 80-3 of the device. 对应地,从器件的比较器80_3 的输出改变到是“L”的N21和是“H”的N22。 Correspondingly, change the output of the comparator device 80_3 to be from the "L" of the N21 and the "H" of the N22. 在这种方式中,改变了由判优器作出的决定。 In this way, we are changing the decision made by the arbiter.

[0289] 现在我考虑与上述情形相反的A端口的feite指令的地址和B端口的Read指令的地址相互匹配的情形。 [0289] Now I consider the address feite instruction address and the B port Read instruction above case opposite the port of A matched case. 在这种情形中,从器件的比较器80-5输出被改变,从而改变在从器件中由判优器作出的决定。 In this case, the comparator 80-5 is changed from the output of the device to change the decision from the device made by the arbiter.

[0290] 比较WA2和WB2的比较器80_6具有一个不同于比较器80_3和80_5的外围电路配置。 [0290] Comparative WA2 and WB2 comparator has a different from the comparator 80_6 80_3 80_5 and a peripheral circuit configuration. 这是因为当响应Write和feite组合产生BUSY信号时,A端口的指令和B端口的指令中只有一个将被保留。 This is because when responding to Write and feite combined to produce BUSY signal, directives and instructions B port A port, only one will be retained.

[0291] 图34是表示当两个端口的写地址相同时实施的主器件的操作的定时图。 [0291] FIG. 34 is a write address when the two ports simultaneously with the operation of the master timing chart. 图35是表示当两个端口的写地址相同时实施的从器件的操作的定时图。 Figure 35 shows the operation of the device when a timing chart of the write addresses of the two ports at the same time implementation.

[0292] 现在我们考虑如图34所示主器件决定A端口较早,和如图35所示从器件决定B 端口较早的情形。 [0292] We now consider the master decided to FIG. 34 A port is earlier, and as shown in the case of B port is earlier decision from the device as shown in Figure 35. 在地址比较器沈刚刚产生一个匹配信号的瞬间,主器件的比较器80-6 输出是“L”的N25和是“H”的N26,和从器件的比较器80_6输出是“H”的N25和是“L”的N26。 Shen just in address comparator generates a match signal moment, the output of the master comparator 80-6 is "L" of the N25 and the "H" of the N26, and the output from the comparator device 80_6 is "H" of the N25 and is "L" of the N26. 主器件将RA3,WA3,RB3和WB3锁存在这个状态,并输出一个BUSY-A信号。 The master will RA3, WA3, RB3, and WB3 latched in this state, and outputs a BUSY-A signal.

[0293] 当如在本情形中那样在Write-Write组合中产生BUSY信号时,需要删除一个已较早进入的Write指令。 [0293] When a BUSY signal as in the present case in Write-Write combination, you need to delete an early entry into the Write command. 为了这个目的,提供倒相器231,NOR电路232,NAND电路233和234, 倒相器235和236。 For this purpose, there is provided an inverter 231, NOR circuit 232, NAND circuits 233 and 234, inverters 235 and 236. 响应匹配信号,HIGH边沿脉冲电路230产生信号N4的“H”脉冲。 In response to the match signal, HIGH edge pulse circuit 230 generates a signal "H" pulse of N4. 通过某个逻辑操作将信号N4和信号N3组合起来,产生信号N31中的“H”脉冲。 Through a combination of logic operation signal N4 and N3 up signal, a signal N31 in the "H" pulse. 在这个例子中, N26对于主器件是“H”,使N33产生“H”脉冲,导致N25改变成“H”和拟6改变成“L”。 In this example, N26 for the master is "H", so that N33 generates "H" pulse, resulting in N25 is changed to "H" and the proposed 6 changed to "L". 这里,延迟电路237和238用于提供一个能够用来在改变发生前产生BUSY信号的额外时间, 并防止当将已经改变了的状态反馈回到NAND电路233和234时再次被改变。 Here, the delay circuits 237 and 238 can be used for providing a change before the BUSY signal generated extra time and prevents when the state has changed is fed back to NAND circuit 233 and 234 when it is changed again. 在从器件中, 将N25改变成“L”,将N26改变成“H”。 In the device, the N25 is changed to "L", the N26 is changed to "H".

[0294] 如以前描述的那样,主器件产生BUSY-A信号,接收这个信号的从器件使它的WO 改变成“L”。 [0294] As described previously, the master generates a BUSY-A signal, this signal is received from the device of WO changed to make it "L". 因为在这个特定瞬间N3是“L”,所以从器件的比较器80-6再次被反转,导致使N25改变成“H”,使拟6改变成“L”。 Because in this particular instant N3 is "L", so from the comparator 80-6 is reversed again, so N25 is changed to cause "H", so that the proposed 6 changed to "L".

[0295] 延迟电路250接收信号N4,并使这个信号延迟一个预定时间长度,从而产生一个Wait期间。 [0295] The delay circuit 250 receives the signal N4, and delays this signal by a predetermined length of time, resulting in a Wait period. 这里,当选择m或N2时选择Delay (延迟)(tl),当选择N3时选择Delay (t2)。 Here, when the choice of selecting m or N2 Delay (delay) (tl), when selecting N3 is selected Delay (t2).

[0296] 提供NAND电路251和252与倒相器253和2M用于当Wait期间结束时从指令寄存器清除被跳过的Write指令。 [0296] provide NAND circuit 251 and 252 and the inverter 253 and 2M Wait for the end of the period, when the instruction register is cleared from the skipped Write command. 例如,如果在Wait期间结束时N25是“L”和N26是“H”,则将执行A端口的feite指令。 For example, if at the end of the period Wait N25 is "L" and N26 is "H", feite A port command will be executed. 因此,为了从寄存器删除B端口的feite指令产生RESTWB2。 Therefore, in order to remove the B port from the register feite instruction generation RESTWB2. 因为在Wait期间中需要通过BUSY接收或中断改变决定,所以在这个期间指令寄存器中的指令被完整地保留下来。 Because during the Wait through BUSY reception or interruption to change the decision, so in this period of instruction in the instruction register is completely preserved.

[0297] 图36是表示当两个端口的写地址相互匹配使控制器发出中断指令时主器件操作的定时图。 [0297] FIG. 36 is a write address when the two ports match each other so that the controller issues an interrupt instruction timing chart when the master device operation. 图37是表示当两个端口的写地址相互匹配使控制器发出中断指令时从器件操作的定时图。 FIG. 37 is a write address when the two ports match each other to make a timing chart interrupt controller to issue an instruction from operation of the device.

[0298] 如图36所示,在主器件中的指令选择状态由于中断而反转,而且,如图37所示,在从器件中的指令选择状态由于BUSY信号而反转,然后进一步由于中断而反转。 [0298] As shown in Figure 36, the instruction in the state of the master device selection is reversed due to the interruption, and, as shown, in the selection instruction from the device state due to the inverted BUSY signal 37, and further due to the interruption reversed. 这里,由于中断而反转状态的操作与由于BUSY信号而反转状态的操作相同,我们将省略它的详细描述。 Here, since the inverted state of the interruption due to the operation of the operation BUSY signal is the same as the inverted state, we will omit its detailed description.

[0299] 在上述第2实施例的操作中,设计从一个给定的指令到下一个接着的指令扩展的指令周期使它甚至在产生BUSY信号或中断指令后也不改变。 [0299] In operation of the above embodiment 2, designed from a given instruction to the next instruction followed by extended cycles make it even generates a BUSY signal does not change or interrupt instruction.

[0300] 在图26中,例如,虽然响应ReadA2发生BUSY信号,ReadA2 — ReadA3的指令间隔与ReadAl — ReadA2的指令间隔相同。 [0300] In Figure 26, for example, although BUSY signal occurs in response to ReadA2, ReadA2 - ReadA3 instruction interval ReadAl - ReadA2 instruction interval. 要求在Wait期间处理BUSY信号和中断信号。 BUSY signal requires processing and interrupt signal Wait period. 因为这个原因,当由于长的系统总线,大量的从器件,控制器的慢响应等BUSY信号或中断信号的交换需要长时间时,就需要较长的Wait期间。 For this reason, when due to the length of the system bus, a large number of the slave controller slow response, etc. BUSY signal or interruption signal exchange takes a long time, you need a longer period of Wait.

[0301] 为了消除这个问题,当延迟跟随BUSY信号和中断信号的下一个指令输入时可以扩展Wait期间。 [0301] In order to eliminate this problem, when the delay following the BUSY signal and interrupting a command signal input can be expanded during Wait. S卩,当加长Wait期间时可以扩展ReadA2 — ReadA3的指令间隔使它比在图沈中的ReadAl — ReadA2的指令间隔长。 S Jie, when lengthening Wait period can be extended ReadA2 - ReadA3 command interval than it sink in Fig ReadAl - ReadA2 command interval length.

[0302] 为了延迟一个指令输入,可以在设计书中说明指令输入的延迟,和可以设计控制器使它根据数据表进行操作。 [0302] In order to delay a command input, it can make it operate according to the data table design book describing the instructions input delay, and can be designed controller. 如图31所示通过加长延迟电路250的延迟时间达到Wait期间的扩展。 Shown by lengthening the delay time of the delay circuit 250 reaches the extended period Wait in Figure 31. 如果根据用度需要调整Wait期间,则在延迟电路250中可以提供两条或多条延迟线,使通过一个模寄存器的设置改变延迟长度的设置成为可能。 If costs need to be adjusted according to the period Wait, the delay circuit 250 may be provided in two or more delay lines, so that changing a mode register by setting the length of the delay settings possible.

[0303] 当Wait期间以这种方式扩展时,除了响应Write-Write指令组合产生BUSY信号的情形外在其它情形中也能够提供长的Wait期间。 [0303] When in this manner during the Wait extensions, except in response to the case of Write-Write command combination BUSY signal is generated outside other cases it is possible to provide a long period Wait. 考虑到这一点,甚至当响应Read-Write 或feite-Read指令组合出现BUSY信号时控制器也可以发出一个中断指令。 With this in mind, even when the response Read-Write or feite-Read command combination occurs BUSY signal controller may also issue an interrupt instruction.

[0304] 在上面描述的本发明中,当指令进入N个端口时,在任何给定的端口的一个最小指令周期内一个接着一个地执行与N个端口对应的所有的N指令。 [0304] In the present invention, as described above, when the instruction enters N ports, at any given port of a minimum instruction cycle one after implementation of all the N instruction and the corresponding N ports. 因此,一个与任何给定端口有关的存取操作出现在器件外部中在最小指令周期内被实施。 Therefore, occurrence of any given port access operations related to the external device is implemented within a minimum instruction cycle. 在这个情形中,只有当从多个端口存取同一个地址时才会发生BUSY信号。 In this case, only when accessing the same address from the plurality of ports BUSY signal will occur. 于是可以得到BUSY信号发生概率,该概率与SRAM型多端口存储器的BUSY信号发生概率一样低。 Thus the probability of BUSY signal generation can be obtained, the probability and the probability of BUSY signal SRAM-type multi-port memory of the same low occurrence.

[0305] 而且,在本发明的半导体存储器件中,内部电路包括一个存储单元阵列,该阵列由各动态型存储单元和一个定义存储单元被刷新的定时的刷新电路组成。 Timed refresh circuit [0305] Further, in the semiconductor memory device of the present invention, the internal circuit includes a memory cell array, which by the dynamic type memory cell and a memory cell to be refreshed defined composition. 在第1模式中,响应输入到在N个端口中的至少一个的刷新指令刷新存储单元,在第2模式中,在刷新电路确定的定时刷新存储单元。 In the first mode in response to the N input ports of at least one of the refresh command to refresh the memory unit, in the second mode, the memory cells are refreshed regularly refresh circuit determined.

[0306] 即,上面描述的本发明具有第1操作模式,在该模式中响应来自一个外部端口的指令实施刷新操作,和第2操作模式,在该模式中响应内部刷新电路实施刷新操作。 [0306] That is, as described above, the present invention has a first mode of operation, in response to an instruction from an external port in this mode, a refresh operation, and a second mode of operation, in response to the internal refresh mode, a refresh operation circuit. 因为这个配置,允许一个外部端口作为一个用于刷新管理的端口进行操作,以便在琠w的间隔接收刷新指令,或者如果这个用于刷新管理的端口处在去激活状态则内部刷新电路实施刷新操作。 Because of this configuration, allow an external port as a port for refresh management to operate in order to receive refresh commands constant, or if this port for refresh management is in a deactivated state, the internal refresh circuit refresh operation. 这使根据系统配置以一种灵活的方式管理刷新操作成为可能。 This allows the system according to the configuration in a flexible way to manage refresh operations become possible.

[0307][本发明的第2方面] [0307] [second aspect of the present invention]

[0308] 下面我们描述本发明的第2方面。 [0308] In the following description of the second aspect of the present invention.

[0309] 存在若干种多端口存储器。 [0309] There are several kinds of multi-port memory. 下文中,涉及具有多个端口的存储器,并允许从各端口相互独立地存取一个公共存储器阵列。 Hereinafter, it relates to a memory having a plurality of ports, and allows access independently of each other from a common memory array for each port. 例如,两个端口型的多端口存储器装备有一个A端口和一个B端口,并允许从与A端口链接的CPU-A和从与B端口链接的CPU-B独立地进行到公共存储器的读/写存取。 For example, two-port multi-port memory is equipped with an A port and a B port, and allows the A port links and read from CPU-A and B ports linked from CPU-B independently to common memory / write access.

[0310] 作为这类多端口存储器,具有SRAM存储器阵列的存储器是已知的,其中在复制的设置中提供各字线和各位线对,每个存储单元都与2组字线和位线对连接。 [0310] As such a multi-port memory, the memory having SRAM memory array is known, which provides word lines and bit lines in the copied settings for each memory cell associated with the two groups of word lines and bit lines connection. 然而,这种多端口存储器具有电路密度低的问题,其中需要提供字线和位线对的复制组。 However, the multi-port memory having a low circuit density problems, the need to provide word lines and bit lines of the replication group.

[0311] 为了消除这个问题,可以用与具有多个处理器配置的计算机所用的共用存储器相同的机构。 [0311] In order to eliminate this problem, you can use the same mechanism with a shared memory computer with multiple processor configuration used. 共用存储器具有提供给公共存储器的多个端口。 The common memory having a plurality of ports provided for a common memory. 典型地,将SRAM用作存储器,并用离散的IC(集成电路)制成多个端口。 Typically, an SRAM is used as a memory, and a plurality of ports made discrete IC (Integrated Circuit). 当从多个端口同时进行存取时,因为存储器阵列是共用的,所以不能同时进行与多个端口相应的操作。 When accessed from multiple ports, because the memory array is shared, it can not be the appropriate action with multiple ports simultaneously. 防止这种问题发生的最简单的方法是对每个端口产生BUSY信号以便防止当从一个端口进行存取时到另一个端口的存取。 The easiest way to prevent this problem is to create BUSY signal for each port in order to prevent, when accessed from one port to another port access. 然而,这引起限制存储器用度的问题。 However, this causes a problem limiting usage of the memory. 考虑到这一点,为公共存储器提供称为判优器的判优电路,判优电路确定多个端口接收的存取要求的优先权。 With this in mind, providing arbiter called the arbiter of public memory, the arbiter circuit to determine priority of the plurality of access requests received by the port. 构造存储器阵列的控制器,以优先权的次序执行与存取要求对应的操作。 A memory array controller is configured to perform priority order corresponding to the operation and access requirements. 例如,以到达的次序即以将存取要求加到各端口的次序处理存取要求。 For example, in order to reach the access requirement, i.e., added to the processing order of the port access requirements.

[0312] 在这个情形中,存储器阵列最终随机地从多个端口被存取。 [0312] In this case, the memory array is accessed at random from the final plurality of ports. 因此,不能提供在同一个行地址连续地存取相继的列地址的列存取操作,而这样的列存取操作典型地可以在DRAM 中得到。 Therefore, can not provide the same column access operation that successively accesses consecutive row address column address, and this can be a column access operation is typically in the DRAM. 即,选择,为读/写操作存取和复位存储单元,响应单个存取实施所有这些操作。 That is, the options for read / write operations access and reset storage unit, in response to a single access to the implementation of all these operations.

[0313] 当制成一个共用存储器时,一般地,按常规将SRAM用作存储器阵列。 [0313] When a shared memory is made, in general, according to the conventional SRAM is used as a memory array. 这是因为SRAM能够进行高速随机存取操作,并且因为不需要刷新操作所以能够容易地使用SRAM。 This is because the SRAM capable of high-speed random access operations, and a refresh operation is not required because it is possible to easily use SRAM. 然而,单块芯片的多端口存储器常规地具有以字线和位线对的复制组,在具有通常的SRAM配置的存储器阵列的基础上的单块芯片的多端口存储器还没有在实践中使用。 However, a single block of multi-port memory chips conventionally having word lines and bit lines of the replication group, on the basis of multi-port memory array having an ordinary SRAM configuration memory on a single chip has not been used in practice.

[0314] 总结一下,多端口存储器和共用存储器是用SRAM制成的,而不用需要刷新操作的DRAM。 [0314] In summary, multi-port memories and shared memories are made with the SRAM, but without the need to refresh the DRAM operation.

[0315] 当系统不断地提供高性能时要被处理的数据量增加,并且多端口存储器也需要具有大的容量。 [0315] When the system to continue to provide high performance to increase the amount of data to be processed, and multi-port memory needs to have a large capacity. 可以用动态型存储单元(DRAM)阵列制成多端口存储器,DRAM阵列比SRAM具有较高的电路密度,从而以低的成本提供具有大存储容量的多端口存储器。 May be a dynamic type memory cell (DRAM) array made multi-port memory, DRAM array has a higher than SRAM circuit density so as to provide a low cost multi-port memory having a large memory capacity. 然而,存储单元的刷新操作成为一个问题。 However, memory cell refresh operation becomes a problem.

[0316] 在常规的DRAM中,需要从器件外部以琠w间隔在读/写指令之间提供刷新指令。 [0316] In the conventional DRAM, it is necessary from an external device with a constant interval between the read / write commands provide a refresh command. 为此,在以DRAM为基础的系统中的控制器器件具有用于刷新管理的定时器和/或控制电路。 For this reason, in order to DRAM-based system management controller device has a refresh timer and / or control circuit. 然而,在用以SRAM为基础的多端口存储器的系统中不提供这样的电路。 However, it does not provide such a circuit for SRAM-based multi-port memory system. 甚至在以DRAM 为基础制成存储器的情形中,在这些系统中需要能以与常规的多端口存储器相同的方式使用这种存储器。 Even with DRAM-based memory into the case, in these systems need to be able to conventional multi-port memory in the same manner using this memory. 即,具有由DRAM组成的存储器阵列的多端口存储器需要由它自己来进行刷新操作。 That is, the multi-port memory having a memory array composed of DRAM needs to be refreshed by its own operations.

[0317] 本发明的目的是提供具有由DRAM芯组成的存储器阵列,而且不需要考虑刷新操作就能使用的多端口存储器,从而以低的成本提供具有大存储容量并且容易使用的多端口存储器。 [0317] The object of the present invention is to provide a core having a memory array composed of DRAM, and no need to consider the multi-port memory refresh operations can be used so as to provide a low-cost multi-port memory having a large storage capacity and is easy to use.

[0318] 图38是用于解释本发明原理的图,表示当对于两个端口实施读操作时的情形。 [0318] FIG. 38 is a diagram to explain the principles of the present invention, means that when two ports for a read operation when the case.

[0319] 在能够实施3个内部操作周期的最小间隔上提供加到两个外部端口,A端口和B 端口的指令。 [0319] provided applied to two external ports, A port and the B port at the minimum interval instruction to implement three internal operation cycles. 即,将一个外部指令周期设置在比3个内部操作周期需要的持续时间长的长度上。 That is, an external command cycle is set longer than the duration of the three internal operation cycles required length. 分别将时钟信号CLKA和CLKB输入到A端口和B端口,与时钟信号同步地进行在器件的一个外部装置和各外部端口之间的地址和数据的交换。 Respectively, the clock signal CLKA and CLKB input to the A port and the B port, an external device performed switching devices and between each external port address and data synchronization with the clock signal. 使地址(图中未画出)与指令同时进入。 In the address (not shown) with instructions to proceed simultaneously. 当在最小外部指令周期上使读指令进入A端口和B端口时,判优电路通过将优先权给予首先到达的输入信号,控制芯的操作。 When the minimum external command cycle the read command into the A port and the B port, the arbiter by giving priority to the first to reach the input signal to control the operation of the core. 如上所述在一个外部指令周期中能够实施3个内部操作,在这个外部指令周期中在存储器阵列上执行2个读操作,接着将读数据输出到A端口和B端口。 As described above in an external command cycle to implement three internal operations, perform two read operations on the memory array in the external command cycle, and then the read data is output to the A port and the B port. A端口和B端口两者都保持检索的数据,并在下一个跟随的外部指令周期开始时,即与从输入读指令的第4个时钟信号同步地输出检索的数据。 A two-port and B ports maintain data retrieval, and when the next cycle begins to follow the external command, the output data is retrieved from the input commands and read the first four clock synchronization. 即,在这个情形中数据的等待时间是4。 That is, the wait time in this case the data is 4.

[0320] 提供刷新定时器作为内部电路,刷新定时器在它自己身上产生刷新指令。 [0320] the refresh timer as an internal circuit, the refresh timer generates a refresh command it himself. 因为如上所述在一个外部指令周期中能够实施3个内部操作,所以当产生刷新指令时在单个外部指令周期中能够执行指令A,指令B和刷新指令。 Because, as mentioned in an external command cycle to implement three internal operations, so when generating a refresh command in a single external command cycle can execute instruction A, instruction B and a refresh command. 在下一个跟随的外部指令周期开始时输出读数据。 In the next cycle begins to follow the external command output read data. 在这个方式中,可以从器件外部存取多端口存储器而与刷新操作没有任何关系。 In this mode, you can access the multi-port memory from external devices without any relationship with the refresh operation.

[0321] 在图38的例子中,响应一个读指令输出一项读数据。 [0321] In the example of FIG. 38, in response to an output of a read command to read data. 即,脉冲串长度为1。 That is, the burst length is 1. 所以, 在一个时钟脉冲周期中完成读数据的输出后,在外部指令周期的3个余下的时钟周期中外部端口不输出任何数据,这导致无效的数据传输。 So, after the completion of the output read data in one clock cycle, the three remaining clock cycles of the external command cycle external port does not output any data, which results in inefficient data transfer. 可以通过加长脉冲串长度来消除这个问题。 You can eliminate this problem by lengthening the burst length.

[0322] 图39是用于解释本发明原理的图,表示脉冲串长度为4的例子。 [0322] FIG. 39 is a diagram to explain the principles of the present invention, showing an example of the burst length of 4. 在这个例子中, 与上述情形相同,将2个外部端口的外部指令周期设置在能够供应3个内部操作周期的长度上。 In this example, the same as the above case, the two external external command cycle is set in the port capable of supplying three internal operation cycle length. 进一步,一个外部指令周期对应4个时钟周期。 Further, one external command cycle corresponds to four clock cycles. 与时钟信号同步地在单个外部指令周期中从一个外部端口4次输出数据。 With the clock signal to an external port 4 times in synchronization with the output data in a single cycle from the external command. 所以,如果根据一个外部指令周期的时钟周期的数目设置脉冲串长度,则在两个端口都能实现无间隙的读操作,从而非常大地增加了数据传输速率。 So, if the burst length is set according to the number of an external command cycle of clock cycles, then the two ports can achieve gapless read operation, thereby significantly increasing the data transfer rate. 在这个情形中,要求与脉冲串长度一样多的数据项响应单个存取内部地输入存储器阵列或内部地从存储器阵列输出。 In this case, the requirements and the burst length as many data items in response to a single access internal memory array input or output from the memory array internally. 例如,如果外部端口的数据输入/输出销的数目为4, 和脉冲串长度为4,则需要保证由单个存取操作从存储器阵列输出16位数据或将16位数据输入存储器阵列。 For example, if the number of the external port data input / output pin is 4, and the burst length is 4, the need to ensure access operation by a single 16-bit data output from the memory array or the 16-bit data input to the memory array.

[0323] 我们应该注意到A端口和B端口不一定同步操作,并且只要将最小周期设置得等于3个内部操作周期需要的持续时间,就可以将各外部指令周期相互独立地设置在任何定时。 [0323] We should note that the A port and the B port is not necessarily synchronous operation, and as long as the minimum period is set to be equal to the duration of three internal operation cycles needed, you can each independently of one another external command cycle is set at any timing.

[0324] 而且,外部端口的数目也可以是任何数目。 [0324] Moreover, the number of external ports can also be any number. 如果将外部端口的数目设置为n,则将每个端口的外部指令周期设置在能够进行n+1个内部操作周期的最小周期上。 If the number of external ports is set to n, then the external command cycle of each port is set at the minimum cycle time can be n + 1 internal operation cycles. 如果满足这个要求,则甚至当刷新操作被执行时在一个外部指令周期中也可以实施各端口要求的所有操作,从而允许使用多端口存储器而与刷新操作没有任何关系。 If you meet the requirements, even when all operations refresh operation is executed in an external command cycle can also be implemented for each port requirements, allowing the use of multi-port memory and does not have any relationship with the refresh operation.

[0325] 图40和图41是表示当有2个,3个和η个端口时在一个最小外部指令周期和各内部操作周期之间的关系的图。 [0325] FIG. 40 and FIG. 41 is when there are 2, Figure 3 and η a port between a minimum external command cycle and internal operation cycles in the relationship.

[0326] 如这些图所示,如果端口的数目为2,则最小外部指令周期具有能够供应3个内部操作的长度,并且如果端口的数目为3,则最小外部指令周期是可以进行4个内部操作的时间长度。 [0326] As shown in these maps, if the number of ports is 2, the minimum external command cycle has three internal operations can supply a length, and if the number of ports is 3, the minimum external command cycle is carried out 4 internal the length of time of the operation. 进一步,如果端口的数目为η,则最小外部指令周期等于可以执行n+1个内部操作的时间长度。 Further, if the number of ports is η, the minimum external command cycle is equal to n + 1 can perform internal operations of length of time.

[0327] 图42和图43A到43C是表示根据本发明的实施例的多端口存储器的配置的图。 [0327] FIGS. 42 and 43A to 43C is a multi-port memory according to the configuration of an embodiment of the present invention, FIG. 图42表示DRAM芯和它的相关电路,图43A表示A端口,图4¾表示B端口。 Figure 42 shows a DRAM core and its associated circuitry, Fig. 43A showing A port, diagram showing 4¾ B port. 进一步,图43C表示刷新电路。 Further, FIG. 43C shows a refresh circuit. 图43A到43C所示的电路与图42的各部分连接。 FIG. 43A to 43C each part of the circuit shown in FIG. 42 is connected.

[0328] 如这些图所示,这个实施例的多端口存储器包括DRAM芯2011,用于控制确定操作次序并保证以确定的次序实施操作的判优器20¾,多组暂时存储指令,地址和数据的寄存器,2个由A端口2030和B端口2040组成的外部端口,和刷新电路2050。 [0328] As shown in these maps, multi-port memory of this embodiment includes a DRAM core 2011, to control and determine the order of operations in order to ensure the determined implementation of the arbiter of 20¾, multiple sets of temporary storage instruction, address and data registers, two from the A port 2030 and the B port 2040 consisting of external ports, and refresh circuit 2050.

[0329] A端口2030和B端口2040分别包括模寄存器2031和2041,CLK缓冲器2032和2042,数据I/O电路2033和2043,地址输入电路20;34和2044,与指令输入装置20;35和2045,它们根据从器件外部提供的各分开的时钟频率进行操作。 [0329] A port 2030 and the B port 2040 include mode registers 2031 and 2041, CLK buffers 2032 and 2042, Data I / O circuits 2033 and 2043, the address input circuit 20; 34 and 2044, with the instruction input device 20; 35 and 2045, which operated from the exterior of the device according to the respective separate clock frequencies. 将数据等待时间和脉冲串长度存储在模寄存器2031和2041中,使它们能被分别地设置。 A data latency and a burst length is stored in the mode registers 2031 and 2041, so that they can be set separately. 数据I/O电路2033和2043 装备有根据脉冲串长度实施输出/输出数据的并行到串行变换和串行到并行变换的机构。 Data I / O circuits 2033 and 2043 are equipped with in accordance with the burst length parallel input / output data to serial conversion and serial-to-parallel conversion mechanism.

[0330] 刷新电路2050包括刷新定时器2051和刷新指令发生器2052。 [0330] refresh circuit 2050 includes a refresh timer 2051 and a refresh command generator 1033. 刷新定时器2051 在预定间隔上产生刷新开始信号,刷新指令发生器2052对应地产生刷新指令。 Refresh timer 2051 generates a refresh start signal at predetermined intervals, corresponding to the refresh command generator 2052 generates a refresh command.

[0331 ] 分别将加到A端口和B端口的指令,地址和写数据存储在寄存器中。 [0331] will be added to the A port and the B port, respectively, of the instructions, addresses, and write data stored in the register. 也将刷新指令存储在刷新指令寄存器2027中,并将刷新地址存储在刷新地址计数器/寄存器2018中。 Will refresh command is stored in the refresh command register 2027, and the refresh address is stored in the refresh address counter / register 2018.

[0332] 判优器20¾根据指令到达的次序确定执行指令的次序,并以确定的次序将指令传输给DRAM芯2011的控制电路2014。 [0332] arbiter 20¾ determine the order of execution of instructions in accordance with the order of command arrivals, and in the order determined by the command is transmitted to the DRAM core control circuit 2011 of 2014. 进一步,判优器20¾将传输信号传输给对应的地址寄存器和对应的数据寄存器(在写操作情形)。 Further, the arbiter 20¾ transmission signal to a corresponding address register and the corresponding data register (in the case of a write operation). 在DRAM芯2011中,控制电路2014响应提供的指令,控制译码器2013,写放大器(WriteAmp) 2015,和读出缓冲器2016,从而实施对于存储器阵列2012的存取操作。 In the DRAM core 2011, the control circuit 2014 in response to instructions provided by the control decoder 2013, a write amplifier (WriteAmp) 2015, and the read buffer 2016, so as to implement the access to the memory array 2012 operation. 在写操作的情形中,译码器2013为了进行写操作对存取的地址进行译码,以便激活在存储器阵列2012中的字线和列信号线,导致将存储在写数据寄存器A2022和B2023中的写数据通过WriteAmp 2015写入存储器阵列2012。 In the case of a write operation, the decoder 2013 in order to perform a write operation to address access decodes to activate the word line in the memory array 2012 and a column signal line, resulting in the write data stored in the register A2022 and B2023 The write data is written to the memory array 2012 by WriteAmp 2015. 在读操作的情形中,以类似的方式存取存储器阵列2012,导致通过传输门A20M和B 2025将读数据从读出缓冲器2016传输到各端口的数据输出电路。 In the case of a read operation in a similar manner to access the memory array 2012, resulting in transfer to the data output circuit of each port through the transfer gate A20M and B 2025 will read data from the read buffer 2016. 根据DRAM芯2011的操作周期控制传输门的传输定时,并由控制电路2014确定传输定时。 DRAM core 2011 according to the operating cycle control transmission timing of the transmission gate by the control circuit 2014 determines transmission timing. 与对应的外部时钟信号同步地从每个端口的数据输出电路输出输出数据。 Data synchronization with the corresponding external clock signal from the data output circuit output of each port.

[0333] 下面,我们描述与指令处理,地址处理和数据处理中的每一个有关的详细情形。 [0333] In the following, we describe the command processing, address processing and data processing in each case the relevant details.

[0334] 图44和图45是表示根据第1实施例与指令处理有关的装置配置的图。 [0334] FIG. 44 and FIG. 45 is a process diagram of the configuration of the device according to the first embodiment of instruction. 在与图42 和图43A-43C中相同的部件上加上相同的参照数字。 In FIG. 42 and FIG. 43A-43C in the same components plus the same reference numbers. 这也同样应用于其它的图。 This also applies to other drawings.

[0335] 如图44所示,A端口的指令输入装置2035包括输入缓冲器2036,指令译码器2037 和(n-1)时钟延迟电路2038,B端口的指令输入装置2045包括输入缓冲器2046,指令译码器2047和(m-Ι)时钟延迟电路2048。 [0335] shown in Figure 44, the instruction input means 2035 of the A port includes an input buffer 2036, a command decoder 2037, and (n-1) -clock delay 2038, the instruction input means 2045 of the B port includes an input buffer 2046 , the instruction decoder 2047 and (m-Ι) clock delay circuit 2048. 这里,η和m是脉冲串长度。 Here, η and m are burst lengths. 而且,如图45所示,指令寄存器A 20¾包括Read指令寄存器AR 指令寄存器AW,指令寄存器B 20¾包括Read指令寄存器BR和feite指令寄存器BW。 Further, as shown in FIG. 45, the command register A 20¾ includes a Read command register AR command register AW, the command register B 20¾ includes a Read command register BR and feite command register BW.

[0336] 输入缓冲器2036和2046要求以与各时钟信号CLKAl和CLKBl同步地加上Read 指令,指令译码器2037和2047进行译码处理。 [0336] input buffers 2036 and 2046 demanded synchronization with each clock signal CLKAl and CLKBl Read instruction, instruction decoder for decoding processing 2037 and 2047. 指令译码器2037和2047在读指令情形中分别产生RAl和RBl,而在写指令情形分别产生WAl和WBl。 Instruction decoder 2037 and 2047, respectively, and produce RAl RBl instruction in reading situations, and in the case of writing instruction generate WAl and WBl. 分别将信号RAl和RBl传输给Read指令寄存器AR和BR,不需要任何定时操作,而信号WAl和WBl分别被(n_l)时钟延迟电路2038和(m-Ι)时钟延迟电路2048延迟,直到输入脉冲串数据的最后一个数据项为止, 接着被传输给feite指令寄存器AW和BW。 The signals are transmitted to the RAl and RBl Read command registers AR and BR, without any timing manipulation, and signal WAl and WBl respectively (n_l) clock delay circuit 2038 and (m-Ι) clock delay circuit 2048 delayed until the input pulse The last data item string data, followed by being transferred to feite command registers AW and BW. 而且,将由刷新电路2050产生的刷新指令REFl传输给刷新指令寄存器2027。 Moreover, 2050 will refresh circuit generating a refresh command REFl transmitted to the refresh command register 2027.

[0337] 判优器20¾检测将指令传输给这5个指令寄存器AR,AW, BR, Bff和2027的次序, 并以检测到的次序将这些指令一个接着一个地传输给DRAM控制电路2014。 [0337] arbiter 20¾ detection instruction are transferred to these five command registers AR, AW, BR, Bff and order 2027, and in order to detect these instructions one after the transfer to the DRAM control circuit 2014. DRAM控制电路2014执行接收的指令,产生信号RESETl,要求判优器20¾当指令执行结束或接近结束时发送下一个指令。 DRAM control circuit 2014 executes the received command, a signal RESETl, requires arbiter 20¾ end instruction when executed or sent towards the end of the next instruction. 响应RESETl信号,判优器使存储被执行指令的指令寄存器复位,并将下一个指令传输给DRAM控制电路2014。 RESETl response signal, the arbiter allows execution of instructions stored in instruction register is reset, and the transmission of the next instruction to the DRAM control circuit 2014.

[0338] 图46是判优器20¾的实施例。 [0338] FIG. 46 is the arbiter of Example 20¾. 指令到达图45的5个指令寄存器的次序由比较器2053检测出来如该图46所示。 Order instruction reaches 45 in five instruction register detected by the comparator 2053, as shown in FIG. 46. 每个比较器2053比较两个指令寄存器的定时,将它的输出在首先输入“H”的情形中改变成“H”。 Each comparator 2053 to compare two timed instruction register, its output is changed to "H" in first enter "H" in the case. AND门20M通过检查相关的比较器2053的所有相关输出是否是“H”来确定给定的指令是否在所有4个其它指令前输入。 AND gate 20M by checking the relevant output of the comparator 2053 all relevant whether the "H" to determine whether the instruction given input before all four other instructions. 如果一个响应的指令是最早的则响应各指令的信号RA3,WA3,RB3, WB3和REF变成“H”,并且将响应的指令的地址等被传输给DRAM芯2011,。 If the instruction is a response to the first signal in response to each command RA3, WA3, RB3, WB3, and REF becomes "H", and the address of the instruction in response to the like are transmitted to the DRAM core 2011 ,. 当DRAM芯2011执行该指令时,从DRAM芯2011产生信号RESET1,并产生用于使被执行指令的指令寄存器复位的信号(ReasetRA,ReasetWA等)。 When the DRAM core 2011 executes the instruction from the DRAM core 2011 generates a signal RESET1, and generates an instruction may be executed instruction register reset signal (ReasetRA, ReasetWA etc.). 当使被执行指令的指令寄存器复位时,接收这个被执行指令的比较器2053的输出改变,将在次序中的下一个指令传输给DRAM芯2011。 When the instruction is executed instruction register is reset when receiving the instruction to be executed in 2053 in the comparator output changes, the next instruction in the order of transmission to the DRAM core 2011. 在这个方式中,以指令输入的次序执行指令。 In this manner, the order of execution of the instruction to the instruction input.

[0339] 图47是表示根据第1实施例与地址处理有关的部分的配置的图。 [0339] FIG. 47 is a process-related portion of the configuration of a first embodiment in accordance with the address. 下文中,在它的信号名称的未端具有字母“P”的信号代表具有从对应的信号名称的信号的前沿产生的脉冲的信号。 Hereinafter, in the end it did not signal the name has the letter "P" signal represents a pulse signal from the leading edge signal corresponds to the name of the generated signal. 如图所示,地址输入电路2034和2044分别包括输入缓冲器2057A和2057B与传输门2058A和2058B。 As illustrated, address input circuits 2034 and 2044, respectively, include input buffers 2057A and 2057B and transfer gates 2058A and 2058B. 进一步,地址寄存器A 2019和地址寄存器B 2020分别包括地址锁存器Al和Bi,传输门2060A和2060B,地址锁存器A2和B2,传输门2062A和2062B,与传输门2063A和2063B。 Further, the address register A 2019 and the address register B 2020 include address latches are Al and Bi, transfer gates 2060A and 2060B, address latches A2 and B2, transfer gates 2062A and 2062B, and transfer gates 2063A and 2063B. 通过地址总线2017将从传输门2062A,2062B, 2063A和206!3B提供的地址传输给DRAM芯2011。 Through the address bus 2017 from the transfer gates 2062A, 2062B, 2063A and 206! Address 3B provide transport to the DRAM core 2011. 进一步,通过传输门2064和地址总线17将从刷新地址计数器/寄存器2018提供的刷新地址传输给DRAM芯2011。 Further, through the transfer gate 2064 and the address bus 17 from the refresh address counter / refresh address register 2018 to provide transport to the DRAM core 2011.

[0340] 当从器件外部输入Read指令或feite指令时,分别通过传输门2058A或2058B 将加到输入缓冲器2057A或5027B的地址和输入指令同时传输给地址锁存器Al或Bl。 [0340] When the input feite Read instruction or instruction from an external device, respectively applied to the input buffer address and enter the command 2057A or 5027B through the transfer gate 2058A or 2058B simultaneously transmitted to the address latch Al or Bl. 在Read指令的情形中,通过传输门2063A或206¾与到DRAM芯的指令传输同步地将地址传送给DRAM芯2011。 In the case of a Read command, transferred through the transfer gate 2063A or 206¾ and to command transmission DRAM core in synchronization address to the DRAM core 2011. 在Write指令的情形中,进一步在上次数据采集的定时将地址传输给地址锁存器A2或B2,然后,与到DRAM芯的指令传输同步地通过传输门2062A或2062B传输给DRAM芯。 In the case of a Write instruction, the further the timing of data acquisition in the last address transmitted to the address latch A2 or B2, then, and to command transmission DRAM core in synchronization with the transfer gate 2062A or 2062B transfer to the DRAM core. 进一步,刷新地址计数器/寄存器2018产生并在其中保存刷新地址,然后与到DRAM芯的刷新指令传输同步地通过传输门2064将该地址传输给DRAM芯2011。 Further, the refresh address counter / register 2018 generates and refresh address in which you saved, and then with the refresh command transmission synchronous DRAM core transmitted to the DRAM core 2011 through the transfer gate 2064 and the address.

[0341] 图48是表示根据第1实施例与数据输出有关的部分的配置的图。 [0341] FIG. 48 is based on configuration and data output portion related to the first embodiment of FIG. 图49是表示图48的传输信号发生电路的图。 FIG 49 is a diagram showing a transmission signal generating circuit of Figure 48. A端口2030和B端口2040的各数据I/O电路2033和2043 分别包括为了输出数据的电路2065A和2065B与为了输入数据的电路2074A和2074B,我们将在后面描述它们。 A port 2030 and the B port 2040 of each data I / O circuits 2033 and 2043 include data for output circuit 2065A and 2065B and 2074A for data input circuit and 2074B, which will be described later, respectively. 如图所示,将通过读出缓冲器2016从存储器阵列2012读出的数据通过数据总线2021和传输门20M或2025分别传输给为了输出数据的电路2065A或2065B。 As shown, the data buffer 2016 is read out from the memory array 2012 by reading through the data bus and the transfer gate 20M 2021 or 2025 for transmission to the output data circuit 2065A or 2065B, respectively.

[0342] 为了输出数据的电路2065A和2065B分别包括数据锁存器Al或Bl,传输信号发生电路2067A和2067B,传输门2069A或2069B,数据锁存器A2或B2,并行到串行变换器2070A 和2070B,以及输出缓冲器2071A和2071B。 [0342] In order to output data circuits 2065A and 2065B include data latches are Al or Bl, the transmission signal generating circuit 2067A and 2067B, transfer gates 2069A or 2069B, data latches A2 and B2, parallel-to-serial converters 2070A and 2070B, and output buffers 2071A and 2071B.

[0343] 由DRAM芯2011的控制电路2014根据内部操作对传输门20¾和2025进行控制。 [0343] DRAM core 2011 by the control circuit 2014 in accordance with the internal operation of the transfer gate 20¾ and 2025 control. 如果被执行的指令是Read-A (即,对于A端口的读操作),则传输门20M将打开。 If the instruction to be executed is Read-A (ie, A port for a read operation), the transfer gate 20M will open. 如果被执行的指令是Read-B,则传输门2025将打开。 If the instruction to be executed is Read-B, the transfer gate 2025 will be open. 数据锁存器Al和Bl在其中存储数据,然后在各端口中接收Read指令后的一个确定的等待时间,在这些端口通过传输门2068A或2068B 弓丨入这个等待时间,将数据传输给各数据锁存器A2或B2。 Al and Bl data latches data stored therein, and then wait for a certain time Read command is received in the port after these ports into this latency through the transfer gate 2068A and 2068B 丨 bow, transfer data to each data latch A2 or B2. 然后,由并行到串行变换器2070A 和2070B对数据进行变换,接着分别传输给输出缓冲器2071A和2071B,并从那里输出。 Then, the parallel-to-serial converters 2070A and 2070B transform the data, and then were transferred to the output buffers 2071A and 2071B, and output from there.

[0344] 如图49所示,传输信号发生电路2067A和2067B采用一系列的触发器2072使各Read指令RAl和RBl延迟由等待时间设定确定的许多时间周期,从而产生数据传输信号2002。 As shown in [0344] FIG. 49, the transmission signal generating circuit 2067A and 2067B using a series of flip-flops 2072 and enable the Read instruction RAl RBl delayed by the wait time is set to determine the number of time periods, resulting in data transfer signal 2002. 因为来自传输门2068A或2068B的读数据传输响应数据传输信号2002,所以读数据从读操作的定时开始被延迟与等待时间相当的许多周期后结束。 Since data transmission from the transmission gate 2068A and 2068B read the response data transmission signal 2002, so read data is delayed from the start timing of the read operation and quite a lot of time to wait after the end of the period.

[0345] 图50是表示根据第1实施例与数据输入有关的部分的配置的图。 [0345] FIG. 50 is input according to the first embodiment of the data configuration of a relevant portion. 为了输入数据的电路2074A和2074B分别包括数据输入(Din)缓冲器2075A和2075B,串行到并行变换器2076A和2076B,以及数据传输装置2077A和2077B。 To input circuit 2074A and 2074B, respectively, the data include data input (Din) buffers 2075A and 2075B, 2076A and serial-to-parallel converter 2076B, 2077A, and data transmission means and 2077B. 分别通过Write数据寄存器2022和2023,数据传输装置2078A和2078B,以及数据总线21将来自数据传输装置2077A和2077B 的写数据传送给^^丨㊀々!^ 2015,并被写入存储器阵列2012。 Write data registers respectively by 2022 and 2023, the data transmission device 2078A and 2078B, and the data bus 21 from the data transmission device 2077A and 2077B write data transmitted to Shu ㊀々 ^^! ^ 2015, 2012 and written into the memory array.

[0346] 根据脉冲串长度将串行输入数据从串行变换到并行,然后在输入最后一个数据项的定时传输给Write寄存器2022和2023。 [0346] According to the burst length serial input data from the serial-to-parallel conversion, and then enter the timing for transmitting the last data item to the Write registers 2022 and 2023. 当从判优器20¾将feite指令传输给DRAM芯2011时,通过数据传输门2078A和2078B也将对应的数据传输给DRAM芯2011。 When the arbiter 20¾ will feite command is transmitted to the DRAM core 2011 when, through the data transfer gate 2078A and 2078B will also correspond to the data transmitted to the DRAM core 2011.

[0347] 图51到图58是表示第1实施例的多端口存储器操作的时间图。 [0347] FIG. 51 to FIG. 58 is a timing chart showing the multi-port memory of the first embodiment of the operation. 图51和图52, 图M和图55与图57和图58是为了便于说明将单个时间图分成两部分的图,一个表示时间图的第一个一半,另一个表示时间图的第二个一半,它们之间存在一些重叠。 51 and FIG. 52, and FIG. 55 and FIG M 57 and FIG. 58 is a diagram for convenience of explanation a single time chart of FIG divided into two parts, one showing the first half of the time chart and the other showing a time chart of a second half, with some overlaps therebetween.

[0348] 图51和图52表示当将Read指令相继地输入两个端口时实施的操作。 [0348] FIG. 51 and 52 shows the Read instruction when the operation successively enter two port implementation. A端口和B 端口,它们分别具有有相互不同频率的时钟信号CLKA和CLKB,与接收的时钟信号同步地取得指令,地址和写数据,并与时钟信号同步地输出检索的数据。 A port and the B port, which have respectively have mutually different frequency clock signal CLKA and CLKB, get instructions, addresses and write data in synchronization with the received clock signal, and outputs the data retrieved in synchronization with the clock signal. 在这个例子中,A端口操作在最大时钟频率,而B端口操作在稍低的时钟频率。 In this example, A port operates at a maximum clock frequency, and the B port operate at lower clock frequency. 对于A端口,Read指令周期=4 (CLKA), 数据等待时间=4,和脉冲串长度=4。 For A port, Read command cycle = 4 (CLKA), data latency = 4, and burst length = 4. 对于B端口,Read指令周期=2 (CLKB),数据等待时间=2,和脉冲串长度=2。 For the B port, Read command cycle = 2 (CLKB), data latency = 2, and burst length = 2. 在各端口的模寄存器2031和2041中分别设置数据等待时间和脉冲串长度。 Setting data latency and a burst length of each port mode registers 2031 and 2041, respectively. 在这个例子中,响应一个指令与时钟信号同步地实施数据的输入/输出4次, 在输入读指令后的4个时钟信号中输出检索的数据。 In this example, in response to a command in synchronism with the clock signal embodiment data input / output 4, the output data retrieved in four clock signal input after the read command.

[0349] 分别将加到A端口和B端口的指令存储在指令寄存器20¾和20¾中。 [0349] will be added to each instruction memory A port and the B port in the instruction register 20¾ and 20¾ in. 当刷新定时器2051产生信号时,刷新指令寄存器2027将刷新指令存储在它的里面。 When the refresh timer 2051 generates a signal, the refresh command register 2027 will refresh command is stored in its inside. 判优器20¾监视这些指令寄存器,并以发出指令的次序将这些指令传输给DRAM芯2011。 20¾ arbiter monitors these command registers, and in order to give instructions to transmit these commands to the DRAM core 2011. 当完成上一个指令的处理后传输下一个指令。 When the processing is done on the transmission of an instruction to the next instruction. 将从DRAM芯2011读出的数据从读出缓冲器2016传输到各端口的数据锁存器2069A和2069B,然后将数据从并行数据变换成串行数据,接着作为脉冲串数据与各外部时钟信号同步地输出。 Data read out from the DRAM core 2011 from the read buffer 2016 transmitted to the respective ports of the data latches 2069A and 2069B, and then the data is converted from parallel data to serial data, followed by a burst of data with the external clock signal synchronization output.

[0350] 如图所示,将指令Read_A2输入Read指令寄存器AR和将指令Read_B2输入Read 指令寄存器BR。 [0350] As shown, the input command Read_A2 Read command register AR and the instruction Read_B2 input Read command register BR. 在此之前,发生一次刷新,并将刷新指令输入刷新指令寄存器。 Before this, a refresh occurs once, and a refresh command input refresh command register. 根据发出指令的次序,判优器20¾以Read-A2 — Ref — Read-B2的次序将这些指令传输给DRAM芯2011,然后由芯执行这些指令。 According to the order issued instructions arbiter 20¾ to Read-A2 - Ref - Read-B2 of the order to transfer these commands to the DRAM core 2011, and the implementation of these instructions by the core. 甚至当在内部实施刷新操作时,从外部看来数据是在一个预定数据等待时间后输出的。 Even when the internal refresh operation, from the outside it seems the data is in a predetermined data output wait time. 这样,就不需要考虑任何刷新操作。 Thus, there is no need to consider any refresh operation. [0351] 图53表示在与上述相同的条件下接连地输入Write指令的一个例子。 [0351] FIG. 53 shows an example under the same conditions as above successively input Write command. 也以脉冲串输入的形式给出在Write操作时间从器件外部输入的数据。 Also in the form of a pulse train input is given in the Write operation time data from an external input device. 在输入最后一块数据的定时将^^切指令存储在feite指令寄存器AW中。 In the last piece of data input timing ^^ cut instruction stored in the instruction register AW in feite. 在这个情形中,甚至当在内部产生和执行刷新指令时也不需要考虑任何刷新操作。 In this case, even when a refresh command generated and executed internally and do not need any refresh operation.

[0352] 图M和图55表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作。 [0352] FIG. 55 shows M and when both the A port and the B port operate operation performs Read operations at the maximum clock frequency of implementation. 图56是表示当A端口和B端口两者操作在最大时钟频率上进Rfeite 写操作时实施的操作的图。 Figure 56 shows when operating at maximum clock frequency motivated Rfeite write operation is performed on both the A port and the B port operation in FIG. 在这个情形中,在两个端口的时钟信号中可能存在相位差。 In this case, the clock signal may have a phase difference of the two ports. 对于两个端口,Read指令周期=4,指令周期=4,数据等待时间=4,和脉冲串长度= 4。 For both ports, Read command cycle = 4, the instruction cycle = 4, data latency = 4, and burst length = 4. 从图可见,在这个情形中也能够适当地实施操作。 Seen from FIG., In this case it is possible to implement the operation properly.

[0353] 图57和图58是表示当两个端口都操作在最高频率,并用内部产生的刷新指令从Write指令改变到Read指令时实施的操作的时间图。 [0353] FIG. 57 and FIG. 58 is a diagram when both ports operate at the highest frequency, and with internally generated refresh command from the command is changed to Read Write Directive timing chart operation. 这是指令最拥挤的情形。 This is the instruction of the most crowded situation.

[0354]如图所示,DRAM 芯2011 以Ref — Write-Al — Write-Bl — Read_A2 — Read_B2 的次序进行操作,在它们之间没有任何间隙。 [0354] As shown in FIG, DRAM core 2011 with Ref - Write-Al - Write-Bl - Read_A2 - Read_B2 order to operate, without any gaps between them. 在这个例子中,在输入Write指令后的6个时钟脉冲输入Read-A2和Read-B2。 In this example, at 6 clock input Write command input after Read-A2 and Read-B2. 即便这些定时超前2个时钟信号,也不可能超前DRAM芯的内部操作。 Even if these timings are advanced by 2 clock signals, it is impossible to advance the internal operations of the DRAM core. 由从输入Read指令开始的数据等待时间对读数据的输出定时进行控制。 Read the instruction to start from the input of data latency of read data output timing control. 如果Read-A2和Read-B2的输入定时是超前的,则也需要将数据输出定时向前移动。 If Read-A2 and Read-B2 is input timing is advanced, the data output timings also need to move forward. 在这个情形中响应Read-B2的数据输出定时太接近DRAM芯操作的开始时间,使得不能适当地执行Read-B20因为这个原因,需要将Write — Read变迁的公共间隔设置得相当长如本例中的6个时钟脉冲。 In response to Read-B2 in this case the data output timing is too close to the DRAM core operation start time, making it impossible to properly perform Read-B20 For this reason, you need to Write - Read Change Public spaced quite long as in this example The six clock pulses.

[0355] 关于Read —feite的公共间隔,因为除非完成了Read数据的输出,不能将feite 数据输入DQ端子中,所以公共间隔不可避免地变长。 [0355] Read -feite on public space, because unless the output Read data is completed, the data can not be input into DQ terminals feite, so common interval inevitably becomes long.

[0356] 图59A和59B是表示DRAM芯2011操作的图。 [0356] FIG. 59A and 59B is a diagram showing the operation of the DRAM core 2011 in FIG. 图59A表示Read操作,图59B表示Write操作。 FIG. 59A represents Read operation Write operation Figure 59B represents. 如这些图所示,响应单个指令以字线选择一数据放大一写回一预充电的次序实施一系列操作,从而完成整个操作。 As shown in these figures, in response to a single instruction word line selecting a data write-back amplifying a sequence of one embodiment of a series of pre-charging operation, thereby completing the whole operation.

[0357] 如上所述,在第1实施例中从Write指令到Read指令的指令变迁的时间中指令间隔被加长。 [0357] As described above, in the first embodiment, the Write command to Read command command command transition time interval is lengthened. 在第2实施例中对此进行了改进。 In the second embodiment, this has been improved. 当在第1实施例中一个相关的指令间隔是6 个时钟脉冲周期时,第2实施例能将它缩短为5个时钟脉冲周期。 As in the first embodiment is a relevant command interval six clock cycles, the second embodiment can shorten it to five clock cycles.

[0358] 本发明的第2实施例的多端口存储器具有与第1实施例的多端口存储器类似的配置,不同之处只是刷新电路具有图60所示的配置。 [0358] the second multi-port memory embodiment of the present invention has a multi-port memory of the first embodiment of a similar configuration, the difference is just a refresh circuit 60 has the configuration shown in FIG. 图61是表示第2刷新电路2083的配置的电路图。 FIG 61 is a circuit diagram of a second configuration of the refresh circuit 2083.

[0359] 如图60所示,第2实施例的刷新电路包括将图43C的刷新定时器2051和刷新指令发生器2052组合起来的定时器/刷新指令发生器2081,第2刷新指令寄存器2082和第2 判优器2083,并将从第2判优器2083输出的刷新指令输入到刷新指令寄存器2027。 [0359] As shown in Figure 60, the refresh circuit of the second embodiment includes a refresh timer 2051 of FIG. 43C and the refresh command generator 2052 combining timer / refresh command generator 2081, the second refresh command register 2082, and the second arbiter 2083, and the refresh command input from the second arbiter 2083 outputs to the refresh command register 2027. 与第1 实施例相同将刷新指令寄存器2027的刷新指令REF2输入到判优器2(^6。在这个配置中, 也将在完成刷新操作后从判优器20¾输出到刷新指令寄存器2027的复位信号ResetREF 加到第2刷新指令寄存器2082。 After the same as the first embodiment of the refresh command register 2027 is input to the refresh command REF2 arbiter 2 (^ 6. In this configuration, the operation will also be refreshed from arbiter 20¾ output to reset the refresh command register 2027 ResetREF signal is applied to the second refresh command register 2082.

[0360] 在第2实施例的刷新电路中,沿着刷新指令的路径提供第2判优器2083。 [0360] In the refresh circuit of the embodiment 2, along the path of a refresh command provides a second arbiter 2083. 如果我们预期如在Write指令一Read指令的指令变迁的情形中一样指令很拥挤,则第2判优器2083延迟刷新指令到刷新指令寄存器2027的传输。 If we expect such as in the case of a Write command Read command transition instruction in the same instruction is crowded, the second arbiter 2083 delayed refresh command to refresh command register transfer 2027. 第2判优器2083检查是否用图61所示的电路配置发生从Write指令到Read指令的改变,并且如果检查出这样一个改变就延迟刷新指令从第2刷新指令寄存器2082到刷新指令寄存器2027的传输。 The second arbiter 2083 checks whether the circuit configuration shown in FIG. 61 occurs from a Write command to Read command change, and if you check out such a change would delay a refresh command from the second refresh command register 2082 to the refresh command register 2027 transmission.

[0361] 如图61所示,当各端口接到从器件外部转装置提供的feite指令时,使禁止REF 传输的信号A和B去激活,在一个时钟脉冲周期后再被激活,接着在接到最后一个数据项后的若干个时钟脉冲周期(即,在本例中3个时钟脉冲)再被去激活。 [0361] As shown in Figure 61, when each port feite received instructions from the exterior of the device transfer device provides when making REF transfer prohibition signals A and B to activate, in one clock cycle after being activated, then in the next After the last data item to a number of clock cycles (i.e., in the present example three clock pulses) and then it is deactivated. 图61的3个CLK延迟装置2084A和2084B包括触发器等,并分别被WAl和WBl复位,这导致当通过延迟装置时WAlD和WBlD被复位。 Figure 3 CLK 61 delay means 2084A and 2084B include triggers, and were reset WAl and WBl, which led to the delay through the device when WAlD and WBlD is reset. 得到禁止REF传输的信号A和B的逻辑AND以便产生一个禁止REF 传输的信号。 Get banned REF signal transmission logic AND A and B in order to generate a signal REF transfer prohibition. 因为只有当两个端口都经受从Write指令到Read指令的改变时在这个例子中才会出现问题,而当只有一个端口经受这种改变时不存在问题,所以得到这个逻辑AND。 Because only when two ports are subjected to change from Write commands to Read commands only problem in this case, and when only one port is subjected to such a change is not a problem, so get this logic AND. 进一步,禁止REF传输的信号A和B在接到feite指令后只对一个时钟周期去激活的原因是这给出一个额外的时间以便完成在接收最后一个数据项前的刷新操作。 Further, the REF transfer prohibition signals A and B after receiving feite instruction only one clock cycle to activate this because it gives an extra time to complete the refresh operation before receiving the last data item. 进一步,提供延迟装置2086为了相对于时钟信号稍微延迟定时,以便增大在禁止REF指令传输的信号和从器件外部提供的指令之间的相关定时中的差别。 Further, the delay means 2086 for providing a clock signal slightly delayed with respect to the timing, in order to increase the difference in timing related ban REF command signal transmitted from an external device and the instructions provided in between.

[0362] 图62到图69是表示第2判优器的操作的定时图。 [0362] FIG. 62 to FIG. 69 is a timing diagram of a second arbiter of operation. 图70到图72是表示第2实施例的多端口存储器操作的定时图。 FIG 70 to FIG. 72 is a timing chart showing a second embodiment of the multi-port memory operation. 图62和图63,图64和图65,图66和图67,图68和图69,图70和图71是为了便于说明起见将单个时间图分成两半的图,一个表示时间图的第1 个一半,另一个表示时间图的第2个一半,它们之间存在一些重叠。 62 and FIG. 63, FIG. 64 and FIG. 65, FIG. 66 and FIG. 67, FIG. 68 and FIG. 69, FIG. 70 and FIG. 71 for convenience of illustration the two halves of a single time chart diagram showing a timing chart of the first one half, the other showing the second half of the time chart, there is some overlap between them.

[0363] 图62和图63表示两个端口经受Write — Read指令改变,并当REF传输禁止期间发生刷新定时器事件的情形。 [0363] FIG. 62 and 63 shows two ports subjected to Write - Read command change, and when the situation occurred during a REF transfer prohibition refresh timer event. 在这个情形中,在完成Read-A2和Read-B2后实施刷新操作Ref。 In this case, after the completion of Read-A2 and Read-B2 refresh operation Ref.

[0364] 图64和图65表示与上述情形相同两个端口经受Write — Read指令改变,但是在REF传输禁止期间前发生刷新定时器的情形。 [0364] FIG. 64 and 65 shows the same as the above case two ports subjected Write - Read command change, but in the case occurred before the REF transfer prohibition period refresh timer. 在这个情形中,在实施刷新操作Ref后实施Read操作。 In this case, after the implementation of a refresh operation Ref Read operation.

[0365] 图66和图67说明只有A端口经受Write — Read指令变迁,并在REF传输禁止期间中发生刷新定时器事件的情形。 [0365] FIG. 66 and FIG. 67 illustrate only the A port is subjected to Write - Read command transition, and a refresh timer event happens during a REF transfer prohibition in. 在这个情形中,在完成Write指令后实施刷新操作Ref, 然后实施Read操作。 In this case, after the completion of a Write command in a refresh operation Ref, Read operation is then performed.

[0366] 图68和图69显示在两个端口继续Write的情形。 [0366] FIG. 68 and 69 shows in the case of two ports continue Write. 在这个情形中,一当在接着最后一个数据输入,输入feite指令后,就使3个CLK延迟装置2084A和2084B去激活。 In this case, the last one when the next data input, enter feite instruction, make three CLK delay means 2084A and 2084B deactivated.

[0367] 图70和图71是表示与图57和图58所示的第1实施例的操作对应的第2实施例的操作的时间图。 [0367] FIG. 70 and FIG. 71 is a timing chart showing a first embodiment of FIG. 57 and shown in FIG. 58 corresponding to the operation of the second embodiment of the operation. 与第1实施例比较使Write — Read指令变迁的指令间隔从6个时钟脉冲缩短到5个时钟脉冲。 Comparison with the first embodiment, so that Write - Read command transition command interval shortened from six to five clock pulses clock.

[0368] 图72是表示与图56所示的第1实施例的操作对应的第2实施例的操作的时间图。 [0368] FIG. 72 is a timing chart showing a first embodiment shown in Fig. 56 corresponding to the operation of the second embodiment of the operation. 虽然与第1实施例比较改变了关于刷新操作的指令执行次序,但是保持有次序的操作。 Although the comparison with the first embodiment changes the refresh operation on the instruction execution order, but to maintain orderly operation.

[0369] 如上所述,第2实施例可以在任何条件下适当地实施操作,并能够将Write指令—Read指令变迁的指令间隔缩短到5个时钟脉冲周期。 [0369] As described above, the second embodiment can be implemented operate properly under any conditions, and the ability to Write instruction -Read command transition command interval shortened to five clock cycles.

[0370] 如上所述,本发明允许当以DRAM芯为基础制成存储阵列时使用多端口存储器而不需要考虑任何刷新操作,从而以低成本提供具有大容量和容易使用的多端口存储器。 [0370] As described above, the present invention allows the use of multi-port memory without any regard to refresh operations when the DRAM core to be made based on the storage array, thereby providing a large-capacity and low-cost multi-port memory having easy to use.

[0371][本发明的第3方面] [0371] [third aspect of the invention]

[0372] 下面我们描述本发明的第3方面。 [0372] Here we describe a third aspect of the present invention. [0373] 存在若干种多端口存储器。 [0373] There are several kinds of multi-port memory. 下文中,涉及具有多个端口的存储器,并允许从各端口相互独立地存取一个公共存储器阵列。 Hereinafter, it relates to a memory having a plurality of ports, and allows access independently of each other from a common memory array for each port. 例如,两个端口型的多端口存储器装备有A端口和B 端口,并允许从与A端口链接的CPU-A和从与B端口链接的CPU-B独立地进行到公共存储器的读/写存取。 For example, two-port multi-port memory is equipped with A port and the B port, and allows the link from the A port and read from CPU-A and B ports were independently linked to the common memory CPU-B / write memory take.

[0374] 作为这类多端口存储器,具有SRAM存储器阵列的存储器是已知的,其中在复制组中提供各字线和各位线对,每个存储单元都与2组字线和位线对连接。 [0374] As such a multi-port memory, the memory having SRAM memory array is known, which provides word lines and bit lines of the replication group, and each memory cell has two sets of word lines and bit lines connected . 然而,这个多端口存储器具有电路密度低的问题,其中需要提供字线和位线对的复制组。 However, the multi-port memory having a low circuit density problems, the need to provide word lines and bit lines of the replication group.

[0375] 为了消除这个问题,可以用与具有多个处理器配置的计算机所用的共用存储器相同的机构。 [0375] In order to eliminate this problem, you can use the same mechanism with a shared memory computer with multiple processor configuration used. 一个共用存储器具有提供给公共存储器的多个端口。 A common memory having a plurality of ports provided for a common memory. 典型地,将SRAM用作存储器,并用离散的IC制成多个端口。 Typically, an SRAM is used as a memory, and discrete IC made with multiple ports. 当从多个端口同时进行存取时,因为存储器阵列是共用的,所以不能同时进行与多个端口对应的操作。 When accessed from multiple ports, because the memory array is shared, it can not be operated with a corresponding plurality of ports simultaneously. 防止这种问题发生的最简单的方法是对每个端口产生一个BUSY信号以便防止当从一个端口作出存取时到另一个端口的存取。 The easiest way to prevent this problem occurs when making access from one port to another port access for each port generates a BUSY signal to prevent. 然而, 这引起限制存储器用度的问题。 However, this causes a problem limiting usage of the memory. 考虑到这一点,为一个公共存储器提供一个称为判优器的判优电路,判优电路确定多个端口接收的存取要求的优先权。 With this in mind, to provide a common memory arbitration circuit called arbiter, the arbiter determines a plurality of access requests received by the port priority. 构造存储器阵列的控制器,以优先权的次序执行与存取要求相应的操作。 The controller memory array is configured to execute the order of priority of access requests in the appropriate action. 例如,以到达的次序即以将存取要求加到各端口的次序处理存取要求。 For example, in order to reach the access requirement, i.e., added to the processing order of the port access requirements. 然而,这并不改变当另一个端口的指令正在被处理时不能执行新指令的情况。 However, this does not change the current situation can not implement the new directive to another command port is being processed. 在这种情形中需要传输BUSY信号,存取存储器的器件需要具有处理BUSY信号的机构。 In this case, the BUSY signal to be transmitted, the device needs to access memory having a BUSY signal processing means.

[0376] 随机地从多个接口存取存储器阵列。 [0376] random access memory arrays from multiple interfaces. 因此,不提供在同一个行地址上连续地存取相继的列地址的列存取操作,但是在DRAM中典型地可以利用这种列存取操作。 Therefore, the operation does not provide access to a row in the same column address that successively accesses consecutive column addresses, but is typically in the DRAM column access operation that can be used. 即,选择一个存储单元,为了读/写操作存取该存储单元,使该存储单元复位,所有这些操作都是在响应单个存取时被执行的。 That is, selecting a storage unit for read / write operations to access the storage unit, so that the memory cell is reset, in response to all of these operations are to be performed when a single access.

[0377] 当完成一个共用存储器时,一般,常规地将SRAM用作存储器阵列。 [0377] Upon completion of a common memory, in general, the SRAM is conventionally used as a memory array. 这是因为SRAM 能够进行高速随机存取操作,又,因为不需要刷新操作,所以很容易使用SRAM。 This is because the SRAM capable of high-speed random access operations, but also because there is no refresh operation, so it is easy to use SRAM. 而且,单块芯片的多端口存储器通常具有字线和位线对的复制组,但是在具有通常的SRAM配置的存储器阵列的基础上的单块芯片的多端口存储器还没有在实践中使用。 Moreover, multi-port memory of a single chip typically has word lines and bit lines of the replication group, but in a multi-port memory of a single chip on the basis of the usual SRAM configuration memory array on yet used in practice.

[0378] 总结一下,多端口存储器和共用存储器是用SRAM制成的,而不用需要刷新操作的DRAM。 [0378] In summary, multi-port memories and shared memories are made with the SRAM, but without the need to refresh the DRAM operation.

[0379] 当系统不断地提供高性能时要被处理的数据量增加,并且多端口存储器也需要具有大的容量。 [0379] When the system to continue to provide high performance to increase the amount of data to be processed, and multi-port memory needs to have a large capacity. 可以用动态型存储单元(DRAM)阵列制成多端口存储器,DRAM比SRAM具有较高的电路密度,从而以低的成本提供具有大存储容量的多端口存储器。 It may be a dynamic type memory cell (DRAM) array made multi-port memory, DRAM than SRAM has a higher circuit density so as to provide a low cost multi-port memory having a large memory capacity. 然而,存储单元的刷新操作成为一个问题。 However, memory cell refresh operation becomes a problem.

[0380] 在常规的DRAM中,需要从器件外部以琠w间隔在读/写指令之间提供刷新指令。 [0380] In the conventional DRAM, it is necessary from an external device with a constant interval between the read / write commands provide a refresh command. 为此,在以DRAM为基础的系统中的控制器器件具有用于刷新管理的定时器和/或控制电路。 For this reason, in order to DRAM-based system management controller device has a refresh timer and / or control circuit. 然而,在用以SRAM为基础的多端口存储器的系统中不提供这样一个电路。 However, it does not provide such a circuit for SRAM-based multi-port memory system. 甚至在以DRAM为基础制成存储器的情形中,在这些系统中需要能以与常规的多端口存储器相同的方式使用这种存储器。 Even with DRAM-based memory into the case, in these systems need to be able to conventional multi-port memory in the same manner using this memory. 即,具有由DRAM组成的存储器阵列的多端口存储器需要由它自己来进行刷新操作。 That is, the multi-port memory having a memory array composed of DRAM needs to be refreshed by its own operations.

[0381] 当判优器输出忙碌信号时,存在着如上所述使用存储器相当麻烦的问题。 [0381] When an arbiter outputs a busy signal, there is a rather cumbersome as described above using a memory problem. [0382] 本发明的目的是提供具有由DRAM芯组成的存储器阵列,而且不需要考虑刷新任何刷新操作就能使用的多端口存储器,从而以低的成本提供具有大存储容量并且容易使用的多端口存储器。 [0382] The object of the present invention is to provide a core having a memory array formed by a DRAM, refresh and need not be considered in any multi-port memory refresh operations can be used so as to provide a low-cost multi-port memory having a large capacity and is easy to use memory.

[0383] 为了消除上述的问题,配置本发明的多端口半导体存储器件使它能够在长度为每个外部端口的最小输入周期2)倍的时间周期中执行η个内部操作,其中满足mN< η < m(N+l)。 [0383] In order to solve the above problems, a multi-port configuration of the semiconductor memory device of the present invention makes it possible for each external port in the length of the minimum input cycle 2) times the period of execution η internal operations, which satisfies mN <η <m (N + l).

[0384] 上述条件要求将N个端口的每一个的最小指令周期设置在允许N个内部操作周期的时间周期加比单个内部操作周期短的时间周期α上。 [0384] N above conditions requires a minimum instruction cycle of each port is set in the permit N internal operation cycles plus a time period shorter than a single internal operation cycle time period α. 例如当N = 2时,将每个端口的最小外部指令周期设置在允许2个内部操作周期的时间周期加时间周期α上。 For example, when N = 2, the minimum external command cycle of each port is set in the permit two internal operation cycles plus a time period time period α. 这里,时间周期α比一个内部操作周期短。 Here, the time period α is shorter than one internal operation cycle.

[0385] 本发明利用允许2个内部操作周期的时间周期以便消除由于判优器输出忙碌信号引起的存储器使用麻烦的问题,并利用时间周期α解决刷新操作问题。 [0385] The present invention allows the use of two internal operation cycles of the time period in order to eliminate the memory arbiter outputs a busy signal caused by the use of troublesome issues, and use the time period α solve problems refresh operation.

[0386] 图73是用于解释本发明(第3方面)原理的图,表示对于两个端口实施读操作的情形。 [0386] FIG. 73 is used to illustrate the present invention (third aspect) the principle of showing respect to the case of two ports a read operation.

[0387] 使到两个外部端口,A端口和B端口的指令在最小间隔进入,在该间隔中可以实施内部操作周期2. 2次。 [0387] Shidao two external ports, A port and the B port at the minimum interval to enter instructions, may be implemented in the interval 2.2 times the internal operation cycle. S卩,内部操作周期的2. 2倍等于最小外部指令周期,并将外部指令周期设置得比允许实施内部操作周期2. 2次的时间周期长。 S Jie, 2.2 times the internal operation cycles equal to the minimum external command cycle, and the cycle is set to be longer than the external command allows the implementation of internal operation cycle 2.2 times a period of time. 分别将时钟脉冲CLKA和CLKB输入A端口和B端口,与对应的时钟脉冲同步地实施指令,地址和数据到外部端口的输入和从外部端口的输出。 Respectively, the input clock CLKA and CLKB A port and the B port, perform command and the corresponding clock synchronization, the address and data to the external input port and an output port from the outside. 虽然未加说明,但是与指令同时输入地址。 Although not illustrated, but with instructions simultaneously enter the address. 当在最小外部指令周期中将读指令加到A端口和B端口时,如图所示,判优电路对当实施芯操作时将优先权给予首先到达的指令进行控制。 When the read command is applied to the A port and the B port in the minimum external command cycle, as shown, arbiter of when implementing core operations giving priority to the first to reach the command control.

[0388] DRAM芯实施两个读操作,在一个外部指令周期中从存储器阵列读出数据,并将数据输出到A端口和B端口。 [0388] DRAM core implementation of two read operations, in an external command cycle output of the memory array read data and the data from the A port and the B port. A端口和B端口分别保存检索的数据,并与各时钟脉冲信号的特定的时钟定时同步地输出检索的数据,这些时钟脉冲信号是从输入读指令开始的第6个时钟脉冲。 A port and the B port are stored data retrieval, and the timing of the output data retrieval with a specific clock synchronization each clock pulse signal, these clock signals are input 6 clock pulses from a read command to start. 即,在这个情形中数据等待时间是6。 That is, the data latency in this case is 6.

[0389] 提供刷新定时器作为内部电路,并在它自身上产生刷新指令。 [0389] the refresh timer as an internal circuit, and generates a refresh command on its own. 当不发生刷新操作时,器件的内部电路以例行程序的方式操作以便在一个外部指令周期中实施与指令A和B 对应的两个操作。 When the refresh operation does not occur, the internal circuitry of the device by way of routine operation to implement the directive two operations A and B corresponding to an external command cycle. 因为在一个外部指令周期中能够执行内部操作2. 2次,所以DRAM芯将具有在完成两个内部操作后留下的一个额外时间tα。 Because an external command cycle can be performed 2.2 times the internal operation, so the DRAM core will have an extra time after the completion of the internal operation of the two left tα.

[0390] 当内部产生刷新指令时,器件的内部电路快速操作。 [0390] When the internally generated refresh command, the internal circuitry of the device fast operation. 这里,快速意味着执行操作而不产生额外时间ta。 Here, rapid means to perform operations without generating extra time ta. 当产生刷新指令时,器件实施刷新操作。 When generating a refresh command, the device refresh operation. 因为同时将指令输入A端口和B端口,所以要被处理的指令将积累起来。 Because while the command input ports A and B ports, so the instruction to be processed will accumulate. 器件快速地一个接一个地执行指令而不提供额外时间ta。 Devices quickly one after another without additional instruction execution time ta. 虽然将指令一个接一个地输入A端口和B端口,但是只有在比外部指令周期长的间隔发生刷新指令,只有指令A和指令B必须被执行直到产生下一个刷新指令。 Although the instruction one by one input port A and B ports, but only at long intervals than the external command cycle refresh command occurs, only the instruction A and instruction B must be executed until the next refresh command. 因为内部指令的处理速度较快,所以在结束时将不会有积累的指令。 Because processing speed internal instruction is faster, so at the end there will be no accumulation of instruction. 换句话说,内部处理将赶上外部指令的输入。 In other words, the internal processing will catch up with the input of external commands. 此后,器件回到它的例行程序操作。 Thereafter, the device returns to its routine operations. 通过考虑到外部端口的数目,内部操作周期的数目,刷新间隔等确定额外时间a。 Given the number of external ports by the number of internal operation cycle, the refresh interval, etc. to determine the extra time a.

[0391] 因为当内部刷新指令和输入到另一个端口的指令立即在Read指令前发生时定时变得最坏,所以需要将与Read指令(RD)对应的数据输出的延迟时间(数据等待时间)设置在内部操作的3个周期中(在两个端口的情形中)。 [0391] When the internal refresh command as input to the command of another port becomes worst when the timing immediately before the Read instruction occurs, so it is necessary to delay the Read instruction (RD) corresponding data output (data latency) Set in three cycles of internal operations (in both cases the port). 然而,因为稍长于两个内部操作周期的外部指令周期就是器件适当操作所需要的一切,所以数据传输速率是相当高的。 However, since the external command cycle slightly longer than two internal operation cycles is required for proper operation of the device of all, the data transfer rate is quite high.

[0392] 如上所述,本发明能够取消来自器件外部的刷新操作,并将外部指令周期设置得稍长于两个内部操作周期。 [0392] As described above, the present invention is able to cancel the refresh operation from an external device, and to set external command cycle slightly longer than two internal operation cycles. 不需要刷新来自外部装置的控制,甚至当在内部执行刷新操作时,这对外部装置是完全看不见的,并且不影响从外部装置看的器件操作的方式。 No need to refresh control from an external device, even when the refresh operation is performed in-house, which is completely invisible to the external device, and does not affect the way from an external device to see the operation of the device. 因此,可以从每个外部端口进行到存储器的存取而不用考虑其它端口。 Therefore, it can be from each external port to access memory without regard to other ports.

[0393] 在这个方式中,本发明能够提供用DRAM存储单元的多端口存储器,它有大容量和快的数据传输速率,同时允许使用存储器而不用考虑任何刷新操作就像它在SRAM的基础上完成一样。 [0393] In this manner, the present invention can provide a multi-port memory using DRAM memory cells, it has a large capacity and fast data transfer rates, while allowing the use of memory without any regard to refresh operations as if it's on the basis of SRAM completion of the same.

[0394] 在图73的例子中,响应一个读指令与外部时钟脉冲同步地输出一项读数据。 [0394] In the example of FIG. 73, in response to a read command in synchronization with the external clock pulses output a read data. 艮口, 脉冲串长度为1。 Gen mouth, burst length is 1. 所以,在一个时钟脉冲周期中完成读数据的输出后,在外部指令周期的3 个留下的时钟脉冲周期中外部端口不输出任何数据,这导致无效的数据传输。 So, after the completion of reading the data output in one clock cycle, the three remaining clock cycles of the external command cycle external port does not output any data, which results in inefficient data transfer. 这个问题能够通过加长脉冲串长度来消除。 This problem can be eliminated by lengthening the burst length.

[0395] 图74是用于解释本发明原理的图,表示脉冲串长度为4的例子。 [0395] FIG. 74 is a diagram to explain the principles of the present invention, showing an example of the burst length of 4. 在这个例子中, 如以前的情形那样,将两个外部端口的外部指令周期设置在能够提供2. 2个内部操作周期的长度上。 In this example, such as the previous case, the external command cycles of the two external ports are disposed on can provide 2.2 internal operation cycle length. 进一步,一个外部指令周期对应于4个时钟脉冲周期。 Further, one external command cycle corresponds to four clock cycles. 与时钟脉冲同步地以提供数据等待时间为6的方式在单个外部指令周期中从一个外部端口输出数据4次。 With the clock pulses to provide synchronization data latency mode from an external port 6 output data in a single external command cycle 4 times. 所以, 如果根据一个外部指令周期的时钟脉冲周期的数目设置脉冲串长度,则在两个端口中都能够达到无间隙的读操作,从而非常大地促进了数据传输速率的提高。 So, if the burst length is set according to the number of clock cycles of one external command cycle in the two ports are able to achieve gapless read operation, thereby significantly contributed to improve data transfer rates. 在这个情形中,需要响应单个存取将与脉冲串长度一样多的数据项内部地输入存储器阵列或从存储器阵列输出。 In this case, the need to respond to a single access and the burst length will be as much internal memory array to the data item input or output from the memory array. 例如,如果一个外部端口的数据输入/输出销数目为4和脉冲串长度为4,则需要保证通过单个存取操作将16位数据从存储器阵列输出或输入存储器阵列。 For example, if an external port data input / output pin number 4 and a burst length of 4, you need to ensure access operation by a single 16-bit data output from the memory array or the input of the memory array.

[0396] 我们应该注意到A端口和B端口不一定同步地操作,只要设置最小周期等于对于N个内部操作周期加上比单个内部操作周期短的持续时间α需要的持续时间,就能够相互独立地将各外部指令周期设置在任何定时。 [0396] We should note that the A port and the B port do not necessarily operate in synchronization, as long as the set a minimum period equal to N internal operation cycles plus shorter than a single internal operation cycle The duration of the α need to be able to independently to respective external command cycles provided in any timing.

[0397] 图75和图76是表示在2,3和N个端口的情形中在一个最小外部指令周期和各内部操作周期之间的关系的图。 [0397] FIG. 75 and FIG. 76 illustrates a case in 2,3 N and ports in between a minimum external command cycle and internal operation cycles in the relationship of FIG. 如图所示,如果端口数为2,则最小外部指令周期是允许2个内部操作的时间长度加上α,如果端口数为3,则最小外部指令周期是允许3个内部操作的时间长度加上α。 As shown, if the port number is 2, the minimum external command cycle is the length of time allowed two internal operations plus α, the length of time if the number of ports is 3, the minimum external command cycle is allowed three internal operations plus on α. 进一步,如果端口数为N,则最小外部指令周期等于其间能执行Ν+1个内部操作的时间长度加上时间长度α。 Further, if the number of ports is N, the minimum external command cycles can be performed therebetween equal to the length of time Ν + 1 internal operations plus the time length α.

[0398] 图77和图78Α到图78C是表示根据本发明的一个实施例的多端口存储器的配置的图。 [0398] FIG. 77 and FIG 78Α multi-port memory according to one embodiment of the present invention configured to FIG. 78C is a diagram showing. 图77表示DRAM芯及其相关电路,图78Α表示A端口,图78Β表示B端口。 FIG. 77 shows a DRAM core and its associated circuitry diagram showing 78Α A port, Fig 78Β represents B port. 进一步, 图78C表示刷新电路。 Further, FIG. 78C indicates a refresh circuit. 图78Α到图78C所示的电路与图77的各部分连接。 FIG 78Α to FIG. 78C and FIG respective circuit portion 77 is connected.

[0399] 如这些图所示,本实施例的多端口存储器包括DRAM芯3011,用于控制确定操作次序并保证以确定的次序实施操作的判优器30¾,指令寄存器3025,它暂时存储从判优器3026提供的指令,并将这些指令以接到它们的次序传输给DRAM芯3011的控制电路3014, 暂时存储各端口的指令,地址和数据的多组寄存器,2个由A端口3030和B端口3040组成的外部端口,和刷新电路3050。 [0399] As shown in these maps, multi-port memory of the present embodiment includes a DRAM core 3011, to control and determine the order of operations in order to ensure the determined implementation of the arbiter of 30¾, instruction register 3025, which temporarily stores from sentence 3026 directive provides excellent control, and these instructions to receive their order is transmitted to the DRAM core control circuit 3014 3011, multiple sets of registers for temporarily storing instruction each port, the address and data, two by the A and B ports 3030 External ports in 3040 composed and refresh circuit 3050.

[0400] A端口3030和B端口3040分别包括模寄存器3031和3041,CLK缓冲器3032和3042,数据I/O电路3033和3043,地址输入电路30;34和3044,与指令输入装置30;35和3045,它们根据从器件外部提供的各分开的时钟频率进行操作。 [0400] A port 3030 and the B port 3040 include mode registers 3031 and 3041, CLK buffers 3032 and 3042, Data I / O circuits 3033 and 3043, the address input circuit 30; 34 and 3044, and the command input device 30; 35 and 3045, which operated from the exterior of the device according to the respective separate clock frequencies. 将数据等待时间和脉冲串长度存储在模寄存器3031和3041中,使它们能被分别地设置。 A data latency and a burst length is stored in the mode registers 3031 and 3041, so that they can be set separately. 数据I/O电路3033和3043 装备有根据脉冲串长度实施输出/输出数据的并行到串行变换和串行到并行变换的机构。 Data I / O circuits 3033 and 3043 are equipped with in accordance with the burst length parallel input / output data to serial conversion and serial-to-parallel conversion mechanism.

[0401] 刷新电路3050包括刷新定时器3051和刷新指令发生器3052。 [0401] refresh circuit 3050 includes a refresh timer 3051 and a refresh command generator 3052. 刷新定时器3051 在预定间隔上产生刷新开始信号,和刷新指令发生器3052对应地产生刷新指令。 Refresh timer 3051 generates a refresh start signal, and at predetermined intervals a refresh command generator 3052 generates a refresh command corresponds.

[0402] 分别将加到A端口和B端口的指令存储在指令寄存器A 28A和指令寄存器B 28B 中。 [0402] will be added to each instruction memory A port and the B port in the instruction register A 28A and B 28B in the instruction register. 分别将地址存储在地址寄存器A 19A和地址寄存器B 19B中,分别将写入的数据存储在Write数据寄存器A 数据寄存器B 22B中。 The addresses are stored in address register A 19A and an address register B 19B, and respectively writes the data stored in the Write data registers A data in register B 22B. 进一步,将刷新指令存储在刷新指令寄存器3027中,并将刷新地址存储在刷新地址计数器/寄存器3018中。 Further, the refresh command is stored in the refresh command register 3027, and the refresh address is stored in the refresh address counter / register 3018.

[0403] 判优器30¾根据指令到达的次序确定执行指令的次序,并以确定的次序将指令传输给指令寄存器3025。 [0403] arbiter 30¾ determine the order of execution of instructions in accordance with the order of command arrivals, and in the order determined by the command is transmitted to the command register 3025. 指令寄存器3025以从判优器30¾接到指令的次序将这些指令传送给DRAM芯3011的控制电路3014。 Instruction register 3025 from the arbiter 30¾ instructed the order to transfer these commands to the DRAM core control circuit 3011 of 3014. 当DRAM芯处理给定指令时,使控制电路3014处于能够接收下一个指令的状态。 When the DRAM core handle a given instruction, the control circuit 3014 can receive the next instruction in the state. 对应地,指令寄存器3025下一个指令传送给控制电路3014。 Correspondingly, the command register 3025 of the next instruction to the control circuit 3014. 同时将从判优器30¾提供的指令暂时存储在指令寄存器3025中。 At the same time from the instruction provided by the arbiter 30¾ temporarily stored in the instruction register 3025. 进一步,指令寄存器3025 除了将指令传输给DRAM芯3011的控制电路3014外也将传输信号传输给对应的地址寄存器和对应的数据寄存器(在写操作情形)。 Further, the command register 3025 in addition to the transfer order to the DRAM core control circuit 3014 3011 will also be transmitted outside the signal to a corresponding address register and the corresponding data register (in the case of a write operation). 在DRAM芯3011中,控制电路3014响应提供的指令,控制译码器3013,写放大器(WriteAmp) 3015,和读出缓冲器3016,从而对于存储器阵列3012实施存取操作。 In the DRAM core 3011, the control circuit 3014 in response to instructions provided by the control decoder 3013, a write amplifier (WriteAmp) 3015, and a sense buffer 3016, and thus access to the memory array 3012 implemented operations. 在写操作的情形中,译码器3013为了进行写操作对存取的地址进行译码,以便激活在存储器阵列3012中的字线和列信号线,导致将存储在Write数据寄存器A和B中的写数据通afeiteAmp 3015写入存储器阵列3012。 In the case of a write operation, the decoder 3013 in order to perform the write operation access address decoding, in order to activate the word lines in the memory array 3012 and the column signal line, resulting in stored in the Write data registers A and B write data into the memory array afeiteAmp 3015 through 3012. 在读操作的情形中,以类似的方式存取存储器阵列3012,导致分别通过标记为3024A和3024B的传输门A和B,将读数据从读出缓冲器3016传输到各端口的数据输出电路。 In the case of a read operation, in a similar manner to access the memory array 3012, resulting in marked respectively by transfer gates 3024A and 3024B of A and B, the read data is read out from the buffer 3016 is transmitted to the data output circuit of each port. 根据DRAM芯3011的操作周期,控制传输门的传输定时,并由控制电路3014确定传输定时。 DRAM core 3011 based on the operation cycle, the transfer gate controlling transmission timing by the control circuit 3014 determines the transmission timing. 与对应的外部时钟同步地从每个端口的数据输出电路输出输出数据。 And corresponding external clock synchronization data output from the data output circuit for each port.

[0404] 下面,我们描述与每个指令处理,地址处理和数据处理有关的详细情形。 [0404] Next, we describe each of command processing, address processing, and data processing details relating to the case.

[0405] 图79和图80是表示根据第1实施例与指令处理有关的装置的配置的图。 [0405] FIG. 79 and FIG. 80 is a processing configuration of the relevant device of FIG. 1 according to the first embodiment of instruction. 在与图77和图78A-78C相同的部件上加上相同的参照数字。 In FIG. 77 and FIG. 78A-78C of the same components plus the same reference numbers. 这也同样应用于其它的图。 This also applies to other drawings.

[0406] 如图79所示,A端口的指令输入装置30;35包括输入缓冲器3036,指令译码器3037 和(n-1)时钟延迟电路3038,B端口的指令输入装置3045包括输入缓冲器3046,指令译码器3047和(m-Ι)时钟延迟电路3048。 [0406], the command of the A port of the input device 30 in FIG. 79; 35 includes an input buffer 3036, a command decoder 3037, and (n-1) -clock delay 3038, the instruction input means 3045 of the B port includes an input buffer unit 3046, the instruction decoder 3047 and (m-Ι) clock delay circuit 3048. 这里,η和m是脉冲串长度。 Here, η and m are burst lengths. 而且,如图80所示,指令寄存器A包括Read指令寄存器AR和feite指令寄存器AW,指令寄存器B包括Read指令寄存器BR和feite指令寄存器BW。 Further, as shown in FIG. 80, the command register A includes a Read command register AR and feite command register AW, the command register B includes a Read command register BR and feite command register BW.

[0407] 输入缓冲器3036和3046要求以与各时钟脉冲CLKAl和CLKBl同步地加上Read 指令,指令译码器3037和3047进行译码处理。 [0407] input buffers 3036 and 3046 demanded synchronization with each clock pulse CLKAl and CLKBl Read instruction, the instruction decoder 3037 and 3047 is decoded. 指令译码器3037和3047在Read指令情形分别产生RAl和RBl,而在feite指令情形分别产生WAl和WBl。 Instruction decoder 3037 and 3047, respectively, and produce RAl RBl Read instructions in the case, and in the case of feite instruction generate WAl and WBl. 分别将信号RAl和RBl传输给Read指令寄存器AR和BR,不需要任何定时操作,而信号WAl和WBl被(n_l)时钟延迟电路3038和(m-Ι)时钟延迟电路3048延迟,直到输入脉冲串数据的最后一个数据项为止, 接着分别被传输给Write指令寄存器AW和BW。 The signals are transmitted to the RAl and RBl Read command registers AR and BR, without any timing manipulation, and signal WAl and WBl are (n_l) clock delay circuit 3038 and (m-Ι) clock delay circuit 3048 delayed until the input pulse train The last data item of data, followed by being transmitted to the Write command registers AW respectively and BW. 而且,将由刷新电路3050产生的刷新指令REFl传输给刷新指令寄存器3027。 Moreover, 3050 will refresh circuit generating a refresh command REFl transmitted to the refresh command register 3027.

[0408] 判优器30¾检测将指令传输给这5个指令寄存器AR,AW, BR, Bff和3027的次序, 并以检测到的次序一个接着一个地将这些指令传输给指令寄存器3025。 [0408] arbiter 30¾ detection instruction are transferred to these five command registers AR, AW, BR, Bff 3027 and order, and the order of the detected one by one, these instructions will be transmitted to the command register 3025. 在接到从判优器2026发出的指令时,指令寄存器3025将指令接收确认传输给判优器3(^6。响应指令接收确认,判优器30¾将下一个指令发送给指令寄存器。 Upon receipt of instructions from the arbiter 2026 issue, the instruction register 3025 receives the instruction to confirm the transmission arbiter 3 (^ 6. In response to a command reception acknowledgment, the arbiter 30¾ the next command is sent to the command register.

[0409] 指令寄存器3025以从判优器30¾接到指令的次序将指令一个接着一个地传输给DRAM芯3011的控制电路3014。 [0409] instruction register 3025 from the arbiter 30¾ instructed the order will command one after transmission to the control circuit 3011 of the DRAM core 3014. DRAM芯的控制电路3014执行接到的指令,并当指令执行结束或接近结束时将准备好接收指令的信号传输给指令寄存器3025。 DRAM core control circuit 3014 receives the instruction execution and when executed near the end of the end of the instruction or instruction will be ready to receive a signal transmitted to the command register 3025. 响应准备好接收指令的信号,指令寄存器3025将下一个指令传输给控制电路3014。 Response is ready to receive instruction signal, the instruction register 3025 will next command is transmitted to the control circuit 3014. 同时,将从判优器30¾提供的指令暂时存储在指令寄存器3025中。 Meanwhile, excellent instruction from the judge is temporarily stored 30¾ provided in the instruction register 3025.

[0410] 图81是判优器30¾的实施例。 [0410] FIG. 81 is the arbiter of Example 30¾. 指令到达图80的5个指令寄存器(Read指令寄存器AR,Write指令寄存器AW,Read指令寄存器BR,Write指令寄存器BW和刷新指令寄存器3027)的次序由比较器3053检测出来如该图所示。 Figure 80 instruction reaches the instruction register 5 (Read command register AR, Write command register AW, Read command register BR, Write command register BW, and the refresh command register 3027) in the order detected by the comparator 3053 as shown in the figure. 每个比较器3053比较两个指令寄存器的定时,并首先输入“H”时将它的输出改变成“H”。 Each comparator 3053 to compare two timed instruction register, and the first input "H" to its output changed to "H". AND门30M通过检测相关比较器3053的所有相关输出是否是“H”来确定一个给定的指令是否在所有4个其它的指令前输入。 AND gate 30M by detecting the correlation comparator 3053 whether all the relevant outputs "H" to determine whether a given instruction input before all four other directives. 如果一个对应的指令是最早的并且被传输给指令寄存器3025,则响应各指令,信号RA31,WA31, RB31,WB31和REF31变成“H”。 If a corresponding command is the earliest and is transferred to the command register 3025, the response of each instruction, signal RA31, WA31, RB31, WB31, and REF31 become "H". 如果RA2是RA2到REF2中最早的,则与RA2连接的比较器具有在与RA2连接的一边上为“H”的输出。 If RA2 is the earliest of RA2 to REF2, the comparator and RA2 connected on one side and RA2 have connections to "H" output. 在这个特定的瞬间,指令接收确认还没有产生(=“L”),使得Nl = “H”,导致RA3为“H”。 In this particular moment, a command reception acknowledgment has not produced (= "L"), so that Nl = "H", resulting in RA3 is "H". 于是将指令发送给指令寄存器3025。 So the command to the command register 3025.

[0411] 指令寄存器3025当接收指令时产生指令接收确认。 [0411] The command register 3025 generates a command reception acknowledgment when receiving instruction. 当发生这种情况时,在节点m 产生“L”脉冲,导致RA3到REF3都为“L”。 When this occurs, the node m generate "L" pulse, resulting in RA3 to REF3 are "L". 同时,将产生ResetRA到ResetREF中的一个。 At the same time, it will produce ResetRA to ResetREF one. 如果RA31为“H”,则产生ResetRA,从而使Read指令寄存器AR复位。 If RA31 is "H", is generated ResetRA, thereby resetting the Read command register AR. 对应地,RA2变成“L”, 于是RA31到REF31中的一个变成“H”,指示中下一个在线的指令。 Correspondingly, RA2 becomes "L", then RA31 to REF31 one becomes "H", indicating the next line of command. 当在“L”脉冲未端m变成“H”时,将下一个在线的指令传输给指令寄存器3025。 When the "L" pulse-terminal m becomes "H" when the next line of command is transmitted to the command register 3025. 此后重复上述的操作。 After repeating the above operation.

[0412] 图82和图83是表示指令寄存器3025的配置的图。 [0412] FIG. 82 and FIG. 83 is a diagram showing the configuration of the command register 3025 in FIG. 将指令寄存器3025分成两半并表示在两个图中。 The command register 3025 in half and said that both figures.

[0413] 指令寄存器3025主要包括移位寄存器3092,移位寄存器3092在其中存储指令, 将这些指令连续地输出到DRAM芯3011,并包括将从判优器30¾接收的指令传输到移位寄存器3092的开关(SWl-SWiB) 3082-3084。 [0413] The command register 3025 mainly includes a shift register 3092, a shift register 3092 stores therein instruction, these instructions are continuously output to the DRAM core 3011, and includes an arbiter from 30¾ received instruction is transmitted to the shift register 3092 switch (SWl-SWiB) 3082-3084. 在这个例子中,移位寄存器3092具有三级配置,并包括用于存储指令的寄存器3085-3087,指示寄存器3085-3087的存储状态的标志3088-3090,和使寄存器3085-3087的状态复位的复位数据装置3091。 In this example, the shift register 3092 has three configuration, and includes registers 3085-3087 for storing instructions, indicating the status of the flag storage registers 3085-3087 3088-3090, 3085-3087, and so the reset status register reset data unit 3091. 在没有指令存储在寄存器3085-3087的状态中,标志3088-3090都处于低的状态(FL1-FL3 =“L”),使得开关3082(SW1)接上。 In the absence of instructions stored in the register state in 3085-3087, 3088-3090 signs are in a low state (FL1-FL3 = "L"), so that the switch 3082 (SW1) connected. 通过SWl将第1指令存储在寄存器3085中,使得FLl变成“H”。 By SWl the first command stored in the register 3085, making FLl becomes "H". 当FLl 变成“H”时,“H”边沿脉冲电路3093产生脉冲,将指令接收确认传输给判优器3(^6。 When FLl becomes "H" when, "H" edge pulse circuit 3093 generates a pulse, the command reception acknowledgment is transmitted to the arbiter 3 (^ 6.

[0414] 如果在这个特定的瞬间DRAM芯3011认定准备好接收指令的信号,则门3097打开将寄存器3085的指令传输给锁存器3098,然后将指令发送给DRAM芯3011的控制电路3014。 [0414] 3011 identified if the signal is ready to receive instruction in this particular moment DRAM core, the door opened to transfer 3097 3085 instruction register to latch 3098, and then sends a command to the DRAM core control circuit 3011 of 3014. 同时,将对应于该指令的地址等传输给DRAM芯3011。 Meanwhile, the correspondence address of the instruction to transfer to the DRAM core 3011. DRAM芯3011当根据接到的指令开始操作时取消准备好接收指令的信号。 DRAM core 3011 is ready to receive command signals canceled when starting operation in accordance with instructions received. 于是门3097关闭。 3097 and then the door closed. 寄存器控制电路3096产生促使寄存器3086的数据移到寄存器3085和寄存器3087的数据移到寄存器3086的移位信号。 Register control circuit 3096 generates the data to the cause register 3086 and register data register 3085 3087 moved to register shift signal 3086. 如果在移位信号产生前寄存器3086中没有存储指令,则移位操作导致使寄存器3085复位和使FLl变成“L”。 If produced before 3086 is not stored in the instruction register, the shift operation in the shift register 3085 so that the reset signal causes and make FLl becomes "L". 寄存器控制电路3096在产生移位信号同时产生禁止传输信号以便断开SW1-SW3,从而当移位操作时禁止将数据传送到移位寄存器3092。 Register control circuit 3096 generates a shift signal at the same time generating a transmission signal to prohibit off SW1-SW3, thereby prohibiting the transfer of data to the shift register 3092 when the shift operation. 当通过SWl将第1指令(指令1)加到寄存器3085时,如果DRAM芯3011正在执行前一个指令则将指令存储在寄存器3085中。 By SWl when the first command (command 1) is added to register 3085, if the DRAM core 3011 is executing the preceding instruction stored in the instruction register 3085 will be in. FLl变成“H”,它断开SW1,并进一步在一个预定延迟后断开SW2。 FLl become "H", it disconnects SW1, and further at a predetermined delay after disconnecting SW2. 这里,预定延迟与从产生指令接收确认到使判优器输出复位的时间周期对应。 Here, the predetermined delay and received confirmation from the generation instruction to make arbiter outputs a reset time period corresponds. 如果在DRAM芯3011 准备好接收指令前加上来自判优器30¾的下一个指令(指令2、,则通过SW2将指令存储在寄存器3086中。FL2变成“H”,它产生指令接收确认并断开SW2,接着在一个预定延迟时间后进一步断开SW3。当DRAM芯处在能接收指令的状态时,产生准备接收指令信号,打开门3097,使得将寄存器3085的指令1传输给锁存器3098,然后传输给DRAM芯3011。DRAM芯3011当根据指令1开始操作时取消准备接收指令信号。相应地,门3097关闭。寄存器控制电路3096产生移位信号,该移位信号将寄存器3086的指令2移到寄存器3085,和将寄存器3087的内容(复位状态)移到寄存器3086。寄存器3085结束指令2的存储,寄存器3086 和3087终止在复位状态。因为FLl为“H”,FL2和FL3为“L”,所以接上SW2而断开Sffl和SW3。 If before 3011 ready to receive instruction from the arbiter coupled in DRAM core 30¾ next instruction (the instruction 2 ,, the instructions stored by SW2 will become "H" register in .FL2 in 3086, and it generates a command reception acknowledgment OFF SW2, then after a predetermined delay time for further disconnect SW3. When the DRAM core can receive instruction in the state, generating ready to receive a command signal to open the door 3097, making 3085 the instruction register 1 is transmitted to the latch 3098, then transferred to the DRAM core 3011 core 3011.DRAM 1 starts when the operation is canceled according to the instructions ready to receive command signals. Accordingly, the gate 3097 is closed. shift register control signal generating circuit 3096, the signal will shift instruction register 3086 2 Move to register 3085, and the contents of the register 3087 (reset state) to the register 3086. Register 3085 ends up storing the command 2, registers 3086 and 3087 in a reset state is terminated because FLl as "H", FL2 and FL3 to " L ", so connected and disconnected Sffl SW2 and SW3.

[0415] 复位数据装置3091与在它左边的移位寄存器3092的寄存器连接。 [0415] reset data unit 3091 and in its left shift register 3092 of register connections. 提供这个配置的目的是当在直到寄存器3087的整条路径上指令都被存储时,用接着的移位信号将寄存器3087的指令移到寄存器3086。 The purpose is to provide this configuration until the time when the entire path of the command register 3087 are stored, by the next shift signal will move register instruction register 3087 3086. 在这个方式中,指令寄存器3025暂时积累从判优器30¾ 发送的指令,检测DRAM芯3011的状态,接着一个又一个地传输指令。 In this manner, the command register 3025 temporarily accumulates commands sent from the arbiter 30¾, testing DRAM core 3011 state, and then one after another transfer order.

[0416] 将指令产生检测信号输入寄存器控制电路3096。 [0416] The command generates a detection signal input register control circuit 3096. 当从判优器30¾传输指令时产生指令产生检测信号。 Generated when the arbiter 30¾ transfer instruction from the instruction detection signal. 图84A和图84B表示寄存器控制电路3096的操作。 FIG. 84A and 84B showing the operation of the register control circuit 3096. 当到寄存器控制电路3096的准备接收指令信号去激活时产生移位信号和禁止传输信号。 Generating a shift signal and a transfer inhibiting signal when the register control circuit 3096. ready to receive a command signal to activate. 然而,当就在准备接收指令信号去激活前立即从判优器30¾传输指令时,优先的是只在将较早接收的指令传输给移位寄存器3092后才实施移位操作。 However, when the front in preparation for receiving a command signal to activate immediately arbiter 30¾ transfer instruction from the priority only in the transmission of orders received earlier to the shift register 3092 after the implementation of shift operations. 因此,进行比较以便确定准备接收指令信号的后沿和指令产生检测信号的前沿中哪一个较早。 Thus, compared to determine the trailing edge of the command reception ready signal is generated and instructions leading edge detection signal which earlier. 如果前者较早,则响应前者的后沿产生移位信号和禁止传输信号,如果后者较早,则响应后者的后沿产生移位信号和禁止传输信号。 If the former is earlier, the response generated after the former along the shift signal and a transfer inhibiting signal, if the latter is earlier, the response generated after the latter along the shift signal and a transfer inhibiting signal.

[0417] 图85和图86是表示指令寄存器3025操作的图。 [0417] FIG. 85 and FIG. 86 is a diagram showing the operation of the instruction register 3025. 这里对关于在表示输入指令最拥挤的定时条件的Write — Read指令传输的时间产生刷新指令的情形进行说明。 Here representing the input commands on the timing of the most crowded conditions Write - Read the instruction transmission time generates a refresh command situations described. 图中所示的SWl到SW3的数目指出连接的SW,并说明了连接SW的持续时间。 The number shown in the figure SWl pointed to SW3 connected SW, and illustrates the connection SW duration. 进一步,电阻1到3 分别对应于寄存器3085到3087。 Further, the resistor 1-3 correspond to the register 3085-3087.

[0418] 图87是表示根据第1实施例与地址处理有关的部分的配置的图。 [0418] FIG. 87 is a process-related portion of the configuration of a first embodiment in accordance with the address. 下文中,在它的信号名称的未端具有字母“P”的信号代表具有从对应的信号名称的信号的前沿产生的脉冲的信号。 Hereinafter, in the end it did not signal the name has the letter "P" signal represents a pulse signal from the leading edge signal corresponds to the name of the generated signal. 如图所示,地址输入电路3034和3044分别包括输入缓冲器3057A和3057B,传输门3058A和3058B。 As illustrated, address input circuits 3034 and 3044, respectively, include input buffers 3057A and 3057B, transfer gates 3058A and 3058B. 进一步,地址寄存器3019A和地址寄存器3019B分别包括地址锁存器Al 到A4和Bl到B4,传输门3059A到3063A和3059B到3063B。 Further, the address register address register 3019A and 3019B include address latches respectively Al to A4 and Bl to B4, the transfer gate 3059A to 3063A and 3059B to 3063B. 通过地址总线3017将从传输门3062A,3062B,3063A,306;3B提供的地址传输到DRAM芯3011。 3017 through the address bus from the transfer gate 3062A, 3062B, 3063A, 306; 3B provides the address transmitted to the DRAM core 3011. 进一步,通过传输门3064 和地址总线3017将从刷新地址计数器/寄存器3018提供的刷新地址传输到DRAM芯3011。 Further, through the transfer gate 3064 and the address bus 3017 from the refresh address counter / refresh address register 3018 to provide transport to the DRAM core 3011.

[0419] 当从器件外部输入Read指令或feite指令时,分别通过传输门3058A或3058B 将加到输入缓冲器3057A或3057B的地址和输入指令同时传输给地址锁存器Al或Bl。 [0419] When the input feite Read instruction or instruction from an external device, respectively applied to the input buffer address and enter the command 3057A or 3057B through the transfer gate 3058A or 3058B simultaneously transmitted to the address latch Al or Bl. 在Read指令的情形中,通过传输门306IA和3063A或3061B和306¾和地址锁存器A4或B4 与到DRAM芯的指令传输同步地将地址传送给DRAM芯3011。 In the case of a Read command, transferred through the transfer gate 3063A or 3061B and 306IA and 306¾ and address latch A4 or B4 to a DRAM core and transmission of orders in synchronization address to the DRAM core 3011. 在feite指令的情形中,进一步在上次数据采集的定时将地址传输给地址锁存器A2或B2,然后,与到DRAM芯的指令传输同步地通过传输门3062A或3062B传输给DRAM芯3011。 In the case of feite instruction, the further the timing of the last data collection will address transmitted to the address latch A2 or B2, then, and to command transmission DRAM core in synchronization with the transfer gate 3062A or 3062B transfer to the DRAM core 3011. 进一步,刷新地址计数器/寄存器3018产生并在其中保存刷新地址,然后与刷新指令到DRAM芯的传输同步地通过传输门3064将该地址传输给DRAM芯3011。 Further, the refresh address counter / register 3018 generates and refresh address in which to save, then the refresh command to the DRAM core synchronous transmission transmitted to the DRAM core 3011 through the transfer gate 3064 and the address.

[0420] 图88是表示根据第1实施例与数据输出有关的部分的配置的图。 [0420] FIG. 88 is a diagram showing a configuration of the data output portion related to the first embodiment of FIG. 图89是表示图88的传输信号发生电路的图。 FIG. 89 is a diagram showing a transmission signal generating Figure 88 circuit. A端3030和B端口3040的各数据I/O电路3033和3043分别包括为了输出数据的电路3065A和3065B及为了输入数据的电路3074A和3074B。 A terminal 3030 and the B port each data I / O circuit 3033 and 3040 respectively for 3043 include the output data circuit 3065A and 3065B and 3074A for data input circuit and 3074B. 如图所示,将通过读出缓冲器3016从存储器阵列3012读出的数据通过数据总线3021和传输门3024A或3024B分别传输给为了输出数据的电路3065A或3065B。 As shown, the buffer 3016 is read out by reading the data from the memory array 3012 through the data bus 3021 and the transfer gate 3024A or 3024B is transmitted to the output data of the circuit for 3065A or 3065B, respectively.

[0421 ] 为了输出数据的电路3065A和3065B分别包括数据锁存器Al或Bl,传输信号发生电路3067A和3067B,传输门3068A或3068B,数据锁存器A2或B2,并行到串行变换器3070A 和3070B,以及输出缓冲器3071A和3071B。 [0421] In order to output data circuits 3065A and 3065B include data latches are Al or Bl, the transmission signal generating circuit 3067A and 3067B, transfer gates 3068A or 3068B, data latches A2 and B2, parallel-to-serial converters 3070A and 3070B, and output buffers 3071A and 3071B.

[0422] 传输门3024A和3024B由DRAM芯3011的控制电路3014根据内部操作进行控制。 [0422] transfer gates 3024A and 3024B DRAM core 3011 by the control circuit 3014 is controlled according to internal operations. 如果执行的指令是Read-A(即,对于A端口的读操作),则传输门3024A将打开。 If the instruction execution is Read-A (ie, A port for a read operation), the transfer gate 3024A will open. 如果执行的指令是Read-B,则传输门3024B将打开。 If the instruction executed is Read-B, the transfer gate 3024B will be open. 数据锁存器Al或Bl在其中存储数据,然后在通过传输门3068A和3068B引入等待时间的各端口中接收Read指令后的一个预定等待时间,将数据传输给各数据锁存器A2或B2。 Al or Bl data latch storing data therein, then wait for a predetermined time to receive instruction in the waiting time Read through the transfer gate 3068A and 3068B after the introduction of each port, transfer data to each data latch A2 or B2. 然后,由并行到串行变换器3070A和3070B对数据进行变换,接着分别传输给输出缓冲器3071A和3071B,并从那里输出。 Then, the parallel-to-serial converters 3070A and 3070B transform the data, and then were transferred to the output buffers 3071A and 3071B, and output from there.

[0423] 如图89所示,传输信号发生电路3067(即3067A或2067B)采用一系列的触发器3072使各Read指令RAl或RBl延迟由等待时间设定确定的许多时钟脉冲周期,从而产生数据传输信号3002。 [0423] As shown in Figure 89, the transmission signal generating circuit 3067 (ie 3067A or 2067B) using a series of flip-flops 3072 enable the Read instruction RAl or RBl delay setting many clock cycles determined by the wait time, resulting in data transmission signal 3002. 因为响应数据传输信号3002,通过传输门3068A和3068B传输读数据, 所以读数据从读操作的定时开始被延迟与等待时间设置相同的许多时钟脉冲周期后结束。 Because the response data transmission signal 3002, through the transfer gate 3068A and 3068B transmit read data, the read data is delayed from the timing of the read operation and the wait time set many of the same clock cycle after the end.

[0424] 图90和图91是表示根据本实施例与数据输入有关的部分的配置的图。 [0424] FIG. 90 and FIG. 91 is a diagram showing the configuration of the data input portion according to the embodiment of FIG. 为了输入数据的电路3074A和3074B分别包括数据输入(Din)缓冲器3075A和3075B,串行到并行变换器3076A和3076B,以及数据传输装置3077A和3077B。 To input circuit 3074A and 3074B, respectively, include data input (Din) buffers 3075A and 3075B, 3076A and serial-to-parallel converter 3076B, 3077A, and data transmission means and 3077B. 分别通过第1个Write数据寄存器3078A和3078B,数据传输门3079A和3079B,第2个Write数据寄存器3080A和3080B, 数据传输门3081A和3081B,以及数据总线3021将来自数据传输装置3077A和3077B的Write数据WDA和WDB传送给feiteAmp 3015,然后被写入存储器阵列3012。 Respectively, through the first one Write data registers 3078A and 3078B, data transfer gates 3079A and 3079B, the first 2 Write data registers 3080A and 3080B, data transfer gates 3081A and 3081B, and 3021 data bus from the data transmission device 3077A and 3077B of Write WDA and WDB data transmitted to feiteAmp 3015, then 3012 is written to the memory array.

[0425] 根据脉冲串长度将串行输入数据从串行变换到并行,然后在输入最后一个数据项的定时传输给第1个Write寄存器3078A和3078B。 [0425] According to the burst length serial input data from the serial-to-parallel conversion, and then enter the timing for transmitting the last data item to the first one Write registers 3078A and 3078B. 当从指令寄存器3025将feite指令传输给DRAM芯3011时,也将对应数据传输给DRAM芯3011。 When the command register 3025 will feite command is transmitted to the DRAM core from 3011, the corresponding data will also be transmitted to the DRAM core 3011.

[0426] 图92到图99是表示第1实施例的多端口存储器的操作的定时图。 [0426] FIG. 92 to FIG. 99 is a timing chart showing the multi-port memory of the first embodiment of the operation. 图92和图93, 图95和图96,图98和图99是为了便于说明起见将单个时间图分成两半的图,一个表示时间图的第1个一半,另一个表示时间图的第2个一半,它们之间存在一些重叠。 Figure 92 and Figure 93, Figure 95 and Figure 96, Figure 98 and Figure 99 for ease of illustration a single time chart in half of the diagram, one showing the first half of a time chart and the other showing a time chart of a second half, with some overlaps therebetween.

[0427] 图92和图93表示当将Read指令相继输入两个端口时实施的操作。 [0427] FIG. 92 and 93 represent the Read instruction when the operation have been implemented enter two ports. A端口和B端口,它们分别具有有相互不同频率的时钟信号CLKA和CLKB,与接收的时钟信号同步地取得指令,地址和写数据,并与时钟信号同步地输出检索的数据。 A port and the B port, which have respectively have mutually different frequency clock signal CLKA and CLKB, get instructions, addresses and write data in synchronization with the received clock signal, and outputs the data retrieved in synchronization with the clock signal. 在这个例子中,A端口操作在最大时钟频率,而B端口操作在稍低的时钟频率。 In this example, A port operates at a maximum clock frequency, and the B port operate at lower clock frequency. 对于A端口,Read指令周期=4 (CLKA), 数据等待时间=6(CLKA),和脉冲串长度=4。 For A port, Read command cycle = 4 (CLKA), a data latency = 6 (CLKA), and a burst length = 4. 对于B端口,Read指令周期=2 (CLKB),数据等待时间=3(CLKB),和脉冲串长度=2。 For the B port, Read command cycle = 2 (CLKB), data latency = 3 (CLKB), and a burst length = 2. 在各端口的模寄存器3031和3041中分别设置数据等待时间和脉冲串长度。 Setting data latency and a burst length of each port in the mode registers 3031 and 3041, respectively. 对于A端口,响应一个指令与时钟信号同步地实施数据的输入/输出4次,在输入读指令后的6个时钟脉冲周期输出检索的数据。 For A port, in response to a command in synchronism with the clock signal to implement data input / output four times, the data read instruction after entering the 6 clock cycles output retrieved. 对于B端口,响应一个指令与时钟信号同步地实施数据的输入/输出2次,在输入读指令后的3个时钟脉冲周期输出检索的数据。 For the B port, in response to a command in synchronism with the clock signal to implement data input / output twice data input read command after three clock cycles output retrieved.

[0428] 分别将加到A端口和B端口的指令存储在指令寄存器3028A和3(^8B中。当刷新定时器3051产生信号时,刷新指令寄存器3027在其中存储刷新指令。判优器30¾监视这些指令寄存器,并以发出指令的次序将这些指令传输给指令寄存器3025。指令寄存器3025 暂时存储接收的指令,并以接到它们的次序将它们连续地传输给DRAM芯3011。S卩,在完成上一个传输指令的处理后传输下一个指令。 [0428] will be added to each instruction memory A port and the B port in the instruction register 3028A 3 (^ 8B and when the refresh timer 3051 generates a signal, the refresh command register 3027 stores therein a refresh command. Arbiter 30¾ monitoring The instruction register, and the order issued instructions to transfer the instruction to the instruction register register 3025 temporarily stores the received command 3025. instruction, and received the order in which they were continuously transmitted to the DRAM core 3011.S Jie, in complete After processing and transmission on a transmission instruction of the next instruction.

[0429] 如图所示,将指令Read_A2输入Read指令寄存器AR和将指令Read_B2输入Read 指令寄存器BR。 [0429] As shown, the input command Read_A2 Read command register AR and the instruction Read_B2 input Read command register BR. 在此之前,发生一次刷新,并将刷新指令输入刷新指令寄存器。 Before this, a refresh occurs once, and a refresh command input refresh command register. 根据发出指令的次序,判优器30¾以Read-A2 — Ref — Read-B2的次序将这些指令传输给DRAM芯3011,然后由芯执行这些指令。 According to the order issued instructions arbiter 30¾ to Read-A2 - Ref - Read-B2 of the order to transfer these commands to the DRAM core 3011, and the implementation of these instructions by the core.

[0430] 由于芯的操作在Read-Bl和Read-A2之间存在额外时间,并直到这个点都实施正常的和例行程序操作。 [0430] Since the core of the operation in the presence of extra time between Read-Bl, and Read-A2, and until this point have implemented the normal and routine operations. 当发生刷新时,在Read-A2后立即实施刷新而在其间没有任何时间间隙。 When a refresh occurs, Read-A2 immediately after a refresh and in the meantime there is no time gap. 此后,相继实施Read-B2,Read-A3等而没有任何时间间隙直到执行Read-A5。 Since then, the successive implementation of Read-B2, Read-A3, etc. without any time gap until execution Read-A5. 与正常的和例行程序操作相反,直到这个点都执行快速操作。 And contrary to normal and routine operations until this point have to perform a quick operation.

[0431] 由于刷新指令的执行,内部操作相对于来自器件外部的指令输入显示出一些延迟。 [0431] Since the refresh command execution, internal operations with respect to the command input from an external device showed some delay. 快速操作补偿该延迟,在执行指令Read-A5前赶上。 Access to compensate for the delay, before executing the command Read-A5 catch up. 在Read-A5和Read-B5之间再次存在额外时间,指出回到正常的和例行程序操作。 Again in the presence of extra time between Read-A5 and Read-B5, pointed back to normal and routine operations. 将通过读出缓冲器3016从DRAM芯3011 读出的数据通过传输门传输给接收对应的Read指令的端口的数据锁存器(数据锁存器Al 或Bi)。 The 3016 data by reading out buffer DRAM core 3011 read out from the transmission through the transfer gate to receive the corresponding instructions Read port data latch (data latch Al or Bi). 数据锁存器Al或Bl为数据提供时间调整,然后将数据传输给数据锁存器A2或B2, 并与对应端口的时钟信号同步地输出数据。 Data latch Al or Bl provides time adjustment for the data, and then transfer data to the data latch A2 or B2, and the output data corresponding to a clock signal in synchronization port.

[0432] 甚至当在内部实施刷新操作时,从外部看来数据是在一个预定数据等待时间后输出的。 [0432] Even when the internal refresh operation, from the outside it seems the data is in a predetermined data output wait time. 这样,就不需要考虑任何刷新操作。 Thus, there is no need to consider any refresh operation.

[0433] 图94表示当在与上述相同的条件下接连地输入Write指令时的例子。 [0433] FIG. 94 means that when under the same conditions as described above successively input Write command examples. 也以脉冲串输入的形式给出在Write操作时从器件外部输入的数据。 Also in the form of a pulse train input given externally input data from the device when the Write operation. 在输入最后一个数据块的定时将^^切指令存储在feite指令寄存器AW中。 Enter the last block of timing ^^ cut instruction stored in the instruction register AW in feite. 在这个情形中,甚至当在内部产生和执行刷新操作时也不需要考虑任何刷新操作。 In this case, even when a refresh operation is performed internally generated and do not need to consider any refresh operation.

[0434] 图95和图96表示当A端口和B端口两者都操作在最大时钟频率上进行Read操作时实施的操作。 [0434] FIG. 95 and 96 indicates that when both the A port and the B port operate operation performs Read operations at the maximum clock frequency of implementation. 图97是表示当A端口和B端口两者都操作在最大时钟频率上进行Write 操作时实施的操作的图。 Figure 97 shows when both the A port and the B port operate diagram When Write operations at the maximum clock frequency of the implementation of the operation. 在这个情形中,在这两个端口的时钟脉冲信号中可能存在相位差。 In this case, there may be a phase difference in the two ports of the clock pulse signal. 对于两个端口,Read指令周期=4,指令周期=4,数据等待时间=6,和脉冲串长度=4。 For both ports, Read command cycle = 4, the instruction cycle = 4, data latency = 6, and a burst length = 4. 如从图可见的那样,在这个情形中也可以适当地实施操作。 As seen in the figure, as in this case may be appropriately implemented operations.

[0435] 图98和图99是表示当两个端口都操作在最高频率,并用内部产生的刷新指令经受从feite写指令到Read读指令的改变时实施的操作的时间图。 [0435] FIG. 98 and FIG. 99 is a timing chart showing an operation when both ports operate at the highest frequency, using internally generated refresh command and is subjected to the write instruction from feite Read read command to change implementation. 这是指令最拥挤的情形。 This is the instruction of the most crowded situation.

3[0436]如所说明的那样,DRAM芯 3011 以Ref — Write-Al — Write-Bl — Read_A2 — Read-B2的次序进行操作,在它们之间没有任何间隙。 3 [0436] As described, DRAM core 3011 with Ref - Write-Al - Write-Bl - Read_A2 - Read-B2 in order to operate, without any gaps between them. 在这个例子中,在输入Write指令后6个时钟脉冲输入Read-A2和Read_B2。 In this case, after entering the Write command six clock pulse input Read-A2 and Read_B2. 即便这些定时超前2个时钟脉冲,也不可能超前DRAM 芯的内部操作。 Even if these timings are advanced by 2 clocks, it is impossible to advance the internal operations of the DRAM core. 由从输入Read指令的数据等待时间对读数据的输出定时进行控制。 Read the instruction by the input data from the latency of read data output timing control. 如果Read-A2和Read-B2的输入定时是超前的,则也需要使数据输出定时是超前的。 If Read-A2 and Read-B2 is input timing is advanced, it is also required to make data output timing is advanced. 例如,如果 For example, if

后4个时钟脉冲输入Read-B2,则响应Read_B2的数据输出定时太接近DRAM芯操作的开始时间,使得不能适当地执行Read-B2。 After four clock pulse input Read-B2, the data output timing in response Read_B2 DRAM core operation is too close to the start time, making it impossible to properly perform Read-B2. 因为这个原因,需要将Write — Read变迁的指令间隔设置得相当长如本例中的6个时钟脉冲。 For this reason, we need to Write - Read the instruction changes fairly long intervals, such as in this case six clock pulses.

[0437] 关于Read —feite的指令间隔,因为除非完成了Read数据的输出,不能将feite 数据输入DQ端子中,所以指令间隔不可避免地变得很长。 [0437] For Read -feite instruction interval, because unless the output Read data is completed, the data can not be input into DQ terminals feite, so the command interval inevitably becomes long.

[0438] 图100A和100B是表示DRAM芯3011操作的定时图。 [0438] FIG. 100A and 100B are timing charts showing the operation of the DRAM core 3011. 图100A表示Read操作,图100B表示feite操作。 Figure 100A represents Read operation Figure 100B represents feite operation. 如这些图所示,响应单个指令以字线选择一数据放大一写回一预充电的次序实施一系列操作,从而完成整个操作。 As shown in these figures, in response to a single instruction word line selecting a data write-back amplifying a sequence of one embodiment of a series of pre-charging operation, thereby completing the whole operation. 当接到指令时DRAM芯3011使准备接收指令信号去激活,并当完成或接近结束指令的执行时产生准备接收指令信号。 When instructed to make DRAM core 3011 is ready to receive a command signal to activate, and when complete or near the end of the instruction execution signal generation is ready to receive instruction.

[0439] 如上所述,本发明允许当以DRAM芯为基础制成存储器阵列时使用多端口存储器而不需要考虑任何刷新操作,从而以低成本提供有大容量和容易使用的多端口存储器。 [0439] As described above, the present invention allows the use of multi-port memory without any regard to refresh operations when made with DRAM memory array based core, which has a large capacity at low cost and easy to use multi-port memory.

[0440][本发明的第4方面] [0440] [Fourth aspect of the present invention]

[0441] 下面我们描述本发明的第4方面。 [0441] Here we describe a fourth aspect of the present invention.

[0442] 多端口存储器,它们是装备有多个端口的半导体存储器,可以分成不同的类型。 [0442] Multi-port memories, which are semiconductor memory devices equipped plurality of ports can be divided into different types. 当下文中使用术语“多端口存储器”时,它指的是具有多端口的存储器,该存储器允许从任何一个端口独立地存取公共存储器阵列。 When the next used herein the term "multi-port memory," which refers to a multi-port memory, which is memory allows access to a common memory array independently from any port. 这样一个存储器可以具有A端口和B端口,并允许对于公共存储器阵列从与A端口链接的CPU和从与B端口链接的CPU独立地进行读/写操作。 Such a memory may have an A port and the B port, and allows the public memory array from the A port links the CPU and read from the CPU and the B port link independent / write operations.

[0443] —个多端口存储器装备有称为判优器的判优电路。 [0443] - a multi-port memory is equipped with an arbitration circuit called arbiter. 判优器确定从多个端口接收的存取要求的优先权,存储器阵列的控制电路根据确定的优先权一个接一个的进行存取操作。 Arbiter determined from the plurality of ports of access requests received priority control circuit of the memory array is accessed one after the operation according to the determined priority. 例如,存取要求越早到达端口,就会给予该存取要求越高的优先权。 For example, the earlier arrival port access requirements, the access is given higher priority requirements.

[0444] 在这种情形中,因为随机地从多个接口存取存储器阵列,所以在执行了读或写的存取操作后需要立即使存储器阵列复位,从而保证存储器阵列为下一次存取作好了准备。 [0444] In this case, you need to reset the memory array immediately because random access memory arrays from multiple interfaces, so the execution of the read or write access operations, thus ensuring the memory array for the first access for Well prepared. 即,如果响应来自给定端口的存取要求使一条字线保持在选择状态,和如一般在DRAM中使用的列存取操作中那样连续地动移各列地址以便读出连续的数据,则当该操作期间来自另一个端口的存取要求将一直等待着。 That is, if the response to requests for access from a given port of a word line is kept in the selected state, and is as generally used in the DRAM access operations are successively shifted to read out each column addresses continuous data, During this operation when requests for access from another port will be kept waiting. 因此,在每次读或写操作后需要立即使存储器阵列复位。 Therefore, after each read or write operation needs to reset the memory array immediately.

[0445] 常规地,已经典型地将SRAM用作多端口存储器的存储器阵列。 [0445] Conventionally, it has been typically used as a memory array of the multi-port SRAM memory. 这是因为SRAM允许高速随机存取,而且可以进行非破坏性读操作。 This is because the SRAM allows high-speed random access, and can be non-destructive read operation.

[0446] 在具有两个端口的多端口存储器中,例如,一个SRAM存储单元具有两组字线和位线对。 [0446] In the multi-port memory having two ports, for example, a SRAM memory cell has two sets of word lines and bit line pairs. 一个端口用一组字线和位线对实施读/写操作,另一个端口用另一组字线和位线对实施读/写操作。 A port with a set of word lines and bit lines for a read / write operation, the other port with another set of word lines and bit lines for a read / write operations. 在这种方式中,能够从两个不同的端口独立地实施读/写操作。 In this way, it is possible to implement read from two different ports independently / write operations. 然而,因为当两个端口企图在同一时间将数据写入同一存储单元时不可能同时进行两个写操作,所以给予一个端口进行写操作的优先权,而给予另一个端口BUSY(忙碌)信号。 However, it is impossible at the same time as when the two ports attempt to write data at the same time in the same cell when two writes, so give a write port priority accorded to another port BUSY (busy) signal. 这称为BUSY状态。 This is called a BUSY state.

[0447] 当开发系统使它有改善的性能时,由该系统处理的数据量也增加了。 [0447] When developing a system to have improved performance, the amount of data processed by the system also increases. 结果,多端口存储器需要很大的容量。 As a result, multi-port memory needs a large capacity. 然而,SRAM型多端口存储器具有存储单元的尺寸大的缺点。 However, SRAM-type multi-port memory having a large memory cell size disadvantage.

[0448] 为了消除这个缺点,在多端口存储器中采用DRAM阵列是可以理解的。 [0448] In order to eliminate this disadvantage, the use of DRAM array in a multi-port memory is understandable. 为了得到比多端口SRAM高得非常多的电路密度,需要用于多端口存储器中一个DRAM存储单元以与典型的DRAM单元相同的方式只与一条字线和一条位线连接。 In order to obtain a very high number of circuit density than multi-port SRAM, a need for a multi-port memory DRAM memory cell with the typical DRAM cell is only connected to the same manner as a word line and a bit line. 如果以这样一种方式用DRAM元件制成存储块,如果一个端口正在对给定存储块执行读或写操作,则另一个端口不能存取该存储块。 If in such a manner DRAM memory block element is made, if a port is being given a read or write operation block, the other port can not access the memory block. 这是因为在DRAM存储单元中只可以有破坏性读操作。 This is because the DRAM memory cell can only destructive read operation. 即,当读取信息时,不能选择在同一个存储块中的另一条字线直到这个信息被放大和存储在存储单元中,字线和位线被预先充电为止。 That is, when reading the information, you can not select another word line in the same memory block until this information is amplified and stored in the storage unit, the word lines and bit lines are pre-charged so far.

[0449] 只有当多个端口同时对同一个存储单元提出写要求时,在常规的SRAM型多端口存储器中才会出现BUSY状态。 [0449] Only when multiple ports simultaneously on the same storage unit when the write requests made, in the conventional SRAM-type multi-port memory appears BUSY state. 因此,DRAM型多端口存储器需要具有一个独特的与常规的SRAM型多端口存储器不同的BUSY状态控制功能。 Therefore, DRAM-type multi-port memory needs to have a unique conventional SRAM-type multi-port memory BUSY state control different functions.

[0450] 进一步,与SRAM型多端口存储器不同,DRAM型多端口存储器需要周期地实施刷新操作以便保持存储的信息,从而必须采取某种措施保证适当的刷新定时。 [0450] Further, the SRAM-type multi-port memory different, DRAM-type multi-port memory needs a refresh operation periodically to keep the information storage, so you must take some measures to ensure the proper refresh timing.

[0451] 因此,本发明的目的是提供能够消除特别与DRAM有关的问题的DRAM型多端口存储器。 [0451] Accordingly, the object of the present invention is to provide a DRAM can be eliminated especially with DRAM-type multi-port memory-related problems.

[0452] 根据本发明,半导体存储器件包括多个N个外部端口,它们中的每一个都接收指令,多个与各外部端口对应的N条总线,多个与N条总线连接的存储块,比较由输入到N个各外部端口的指令存取的地址的地址比较器,和判优电路,它确定当地址比较电路根据地址比较检测出到同一个存储块的存取时,存取同一个存储块的各指令中的哪一个或哪几个要被执行,和存取同一个存储块的各指令中的哪一个或哪几个不被执行。 [0452] According to the present invention, the semiconductor memory device includes a plurality of N external ports, each of which receives commands, a plurality of N respective external ports corresponding buses, a plurality of memory blocks connected to the N buses, Compare the input to the address comparator of the N respective external instruction address port access, and arbiter that determines when the address comparator circuit compares the detected address to access the same memory block, access to the same Each instruction in the block which one or a few is to be executed, and access the same memory block of each instruction in which one or a few is not executed.

[0453] 在上面描述的本发明中,如果从器件外部输入端口的指令企图存取同一个存储块时,判优电路确定各指令中的哪一个要被执行,和各指令中的哪一个不被执行。 [0453] In the present invention described above, if the attempt to access the same memory block from the external device instruction input port, an arbitration circuit determines which one of the commands to be executed, and each instruction which does not is performed. 例如,比较指令定时,执行较早的指令,而不执行其它的一个或多个指令。 For example, command timings are compared, the earlier executed instruction without performing one or more other instructions. 当存在不被执行的指令时, 产生BUSY信号等并输出到器件外部。 When there is no instruction to be executed when a BUSY signals and output to external devices. 这使得甚至当在以DRAM芯为基础的多端口存储器中指令存取相互发生冲突时也可以实施适当的存取操作并实现适当的BUSY控制。 This makes it even when the DRAM-core-based multi-port memory access instructions can also perform a proper access operation is in conflict with each other and achieve proper BUSY control.

[0454] 根据本发明的一个方面,存储块包括在动态型存储单元的基础上制成的存储单元阵列,而半导体存储器件包括定义刷新存储单元的定时的刷新电路。 [0454] In accordance with one aspect of the invention, a memory cell array including memory blocks on the basis of the dynamic type memory cell formed, and the semiconductor memory device includes a memory cell refresh timing defined refresh circuit. 在第一模式中,响应输入到N个外部端口中的至少一个端口的刷新指令刷新存储单元,在第二模式中,在刷新电路指出的定时刷新存储单元。 In a first mode in response to input N external ports refresh command to refresh the memory of at least one port means in the second mode, memory cells are refreshed at the timing indicated refresh circuit.

[0455] 上面描述的本发明具有一个操作模式,其中响应来自器件外部的指令执行刷新操作的操作模式,和响应来自内部刷新电路的指令执行刷新操作的操作模式。 The present invention is [0455] described above have a mode of operation, wherein in response to an instruction from the operation mode of the external device perform the refresh operation, and in response to an instruction from the internal refresh circuit operating mode of execution of the refresh operation. 这使在这样一种方式,即将预定外部端口指定作为一个用于在琠w的间隔接收刷新指令进行刷新管理的端口中用多端口存储器成为可能,或者使在这样一种方式,即当所有的外部环部端口都处于去激活状态时内部刷新电路开始刷新操作中用多端口存储器成为可能。 This makes in such a way that a predetermined external port designated as a constant interval for receiving the refresh command port with multi-port memory refresh management becomes possible, or in such a way so that when all the external When the ring portion ports are in the deactivated state of the internal refresh circuit starts a refresh operation with multi-port memory as possible. 因此,本发明为遵从系统要求的灵活的刷新管理提供了基础。 Accordingly, the present invention is to comply with the system requirements for flexible refresh management provides a basis.

[0456] 下面我们将参照所附各图描述本发明(第4方面)的实施例。 [0456] In the following description with reference to the figures of the present invention (fourth aspect) of Example attached.

[0457] 图101是表示根据本发明的多端口存储器的实施例的方框图。 [0457] FIG. 101 is a block diagram illustrating an embodiment of the multi-port memory according to the present invention. 在这个例子中,配置是这样的,即提供两个端口,A端口和B端口。 In this example, the configuration is such that provides two ports, A port and the B port.

[0458] 图101的多端口存储器4010包括A端口4011,B端口4012,自刷新电路4013,存储块4014-1到4014-n,判优器4015,刷新地址计数器4016,地址改变电路4017,地址改变电路4018,地址比较器4019,总线A 4020-1和总线B 4020-2。 [0458] multi-port memory 101 of 4010 includes A port 4011, B port 4012, the self-refresh circuit 4013, memory blocks 4014-1 through 4014-n, the arbiter 4015, the refresh address counter 4016, address change circuit 4017, address change circuit 4018, an address comparator 4019, the bus A 4020-1 and the bus B 4020-2.

[0459] A端口4011包括模寄存器4031,CLK缓冲器4032,数据I/O电路4033,指令译码寄存器40;34,地址缓冲器/寄存器4035和BUSY信号I/O装置4036。 [0459] A port 4011 includes a mode register 4031, CLK buffer 4032, data I / O circuit 4033, the instruction decode register 40; 34, an address buffer / register 4035 and BUSY signal I / O device 4036. 进一步,B端口4012包括模寄存器4041,CLK缓冲器4042,数据I/O电路4043,指令译码寄存器4044,地址缓冲器/寄存器4045和BUSY信号I/O装置4046。 Further, B port 4012 includes a mode register 4041, CLK buffer 4042, Data I / O circuit 4043, a command decoder register 4044, address buffer / register 4045 and BUSY signal I / O device 4046. 在A端口4011和B端口4012,与各时钟信号CLKA和CLKB同步地独立地建立到外部总线的存取和来自外部总线的存取。 In the A port 4011 and the B port 4012, with the clock signal CLKA and CLKB established independently in synchronization to access and access from external bus external bus. 模寄存器4031 和4041能够在其中存储对于各端口的模式设定如数据等待时间和脉冲串长度。 Mode registers 4031 and 4041 can store therein mode for each port settings such as data latency and a burst length. 在这个实施例中,A端口4011和B端口4012两者都具有各自的模寄存器,使每个端口都能进行模式设定。 In this embodiment, A port 4011 and the B port 4012 has its own mode register, so that each port can make mode settings. 然而,可以将模寄存器只安排在一个端口中,例如,使得对于2个端口的设置可以由对这一个端口的设置来实现。 However, we can arrange a mode register only in a port, for example, that for two-port settings can be made in these settings to achieve a port.

[0460] 自刷新电路4013包括刷新定时器4046和刷新指令发生器4047。 [0460] Self-refresh circuit 4013 includes a refresh timer 4046 and a refresh command generator 4047. 自刷新电路4013 在器件中产生刷新指令,分别从A端口4011和B端口4012接收信号CKEAl和CKEBl。 Self-refresh circuit 4013 generates a refresh command inside the device, respectively, from the A port 4011 and the B port 4012 received signal CKEAl and CKEBl. 信号CKEAl和CKEBl是分别用CLK缓冲器4032和4042对外部信号CKEA和CKEB进行缓冲得到的。 CKEAl and CKEBl signal CLK buffers are respectively 4032 and 4042 pairs external signal buffering CKEA and CKEB obtained. 用外部信号CKEA和CKEB暂停各端口的时钟缓冲器并使各端口去激活。 External signal CKEA and CKEB suspend clock buffers on each port and to activate each port. 如果使A端口4011和B端口4012两者都进入去激活状态,则自刷新电路4013开始它的操作。 If the A port 4011 and the B port 4012 are entering a deactivated state, the self-refresh circuit 4013 starts its operation.

[0461] 存储块4014-1到4014-n每个都与内部总线A 4020-1和内部总线B 4020-2连接。 [0461] memory blocks 4014-1 through 4014-n are each connected to the internal bus A 4020-1 and the internal bus B 4020-2. 存在多个外部端口(即,A端口和B端口),其中A端口4011通过总线A 4020-1与存储块4014-1到4014-n中每一个接口,和B端口4012通过总线A 4020-2与存储块4014-1 到4014-n中每一个接口。 There are a plurality of external ports (i.e., A port and the B port), wherein the A port 4011 through the bus A 4020-1 and the memory blocks 4014-1 through 4014-n each of the interface, and the B port 4012 through the bus A 4020-2 Each interface and memory blocks 4014-1 through 4014-n in.

[0462] 如果在同一个时间输入来自A端口4011的存取要求和来自B端口4012的存取要求,则假定这些存取要求是指向不同的存储块的,存取存储块就对应于这些存取要求独立地实施它们的操作。 [0462] If the input access from the A port 4011 and the B port access requests from 4012 at the same time, it is assumed that these access requests are directed to different memory blocks access memory block corresponds to these memory Take independence to implement their operations.

[0463] 如果来自A端口4011的存取要求和来自B端口4012的存取要求是指向同一个存储块的,则判优器(判优电路)4015确定指令到达的次序,并执行第1个到达的指令而删除第2个到达的指令。 [0463] If access from the A port 4011 and access from the B port 4012 is a pointer to the same memory block, the arbiter (arbitration circuit) 4015 determines the order of command arrivals, and implementation of a arrival instructions to delete paragraph 2 arrival instructions. 当删除指令时,判优器4015产生BUSY信号以便通知外部控制器已经被删除第2个到达的指令的存取要求。 When you delete command, the arbiter 4015 generates a BUSY signal to notify the external controller has been removed to reach the first two requests for access instructions.

[0464] 地址比较器4019确定进入两个端口的存取要求中是否指向同一个存储块。 [0464] address comparator 4019 into the two ports to determine whether access requests to the same memory block. 详细的说,地址比较器4019比较包含在进入两个端口的地址中的块选择地址。 In detail, the address comparator 4019 comparative containing block entering the addresses of the two ports select the address. 如果它们是相同的,则将匹配信号加到判优器4015。 If they are the same, then a match signal supplied to the arbiter 4015.

[0465] 当A端口4011或B端口4012处于激活状态时,从A端口4011和B端口4012输入刷新指令。 [0465] When the A or B port 4012 port 4011 is active, the refresh command input from the A port 4011 and the B port 4012.

[0466] 如果进入两个端口中的一个端口的刷新指令存取同一个存储块如输入到两个端口中的另一个端口的读指令或写指令所做的那样,则判优器4015确定指令到达的次序。 [0466] If you enter two ports refresh command a port access the same memory block as input to the read command two ports another port or write command has done, the arbiter 4015 to determine the command order of arrival. 如果刷新指令比其它指令晚,则取消刷新指令。 If the refresh command is later than the other instructions, the refresh command is canceled. 在这个情形中,判优器4015产生BUSY信号, 并将它加到器件外部。 In this case, the arbiter 4015 generates a BUSY signal, and supplies it to an external device. 当检测出BUSY信号时,外部控制器在切断BUSY信号后再次向多端口存储器4010提供刷新指令。 When the BUSY signal is detected, after removal of the external controller BUSY signal to the multi-port memory 4010 provides a refresh command again. [0467] 如果刷新指令比其它指令早,或者从自刷新电路4013提供自刷新指令,则判优器4015产生计数信号,并将它加到刷新地址计数器4016。 [0467] If the refresh command command earlier than others, or from the self-refresh circuit 4013 provides a self-refresh command, the arbiter 4015 generates a count signal, and supplies it to the refresh address counter 4016.

[0468] 刷新地址计数器4016响应计数信号对地址进行计数,从而产生刷新地址。 [0468] in response to the refresh address counter 4016 counts the count signal of the address, thereby generating refresh addresses. 需要从判优器4015提供计数信号的理由是因为如上所述刷新指令能够被取消,所以计数操作应该只响应从判优器4015实际发出的刷新指令进行。 Reason to provide count signals from the arbiter 4015 since a refresh command as described above can be canceled, so the count operation should be carried out only in response to a refresh command from the arbiter 4015 actually issued. 这里,在实施刷新操作后实施计数操作。 Here, after a refresh operation is carried count operation.

[0469] 如果输入到A端口4011的指令是Read指令(读出指令)或Write指令(写入指令),则地址改变电路4017将从外部输入到A端口4011的地址传输给总线A 4020-1。 [0469] If the input to the A port 4011 is a Read command (read-out command) or a Write command (write command), the address change circuit 4017 to address transmission from the external input A port 4011 to the bus A 4020-1 . 如果输入到A端口4011的指令是刷新指令,则将由刷新地址计数器4016产生的地址传输给总线A 4020-1。 If the input to the A port 4011 is a refresh command command, the address will be generated by the refresh address counter 4016 is transmitted to the bus A 4020-1.

[0470] 如果输入到B端口4012的指令是Read指令(读出指令)或Write指令(写入指令),则地址改变电路4018将从外部输入到B端口4012的地址传输给总线B 4020-2。 [0470] If the input to the B port 4012 is a Read command (read-out command) or a Write command (write command), the address change circuit 4018 from an external input to the address transmission B port 4012 to the bus B 4020-2 . 另一方面,如果输入到B端口4012的指令是刷新指令,则将由刷新地址计数器4016产生的地址传输给总线B 4020-2。 On the other hand, if the input to the B port 4012 is a refresh command command, address transmission will be generated by the refresh address counter 4016 to the bus B 4020-2.

[0471] 如上所述,如果A端口4011和B端口4012两者都处于去基活状态,则自刷新电路4013根据作为内部电路提供的刷新定时器4046的定时信号产生刷新指令。 [0471] As described above, if the A port 4011 and the B port 4012 are in the active state to the group, the self-refresh circuit 4013 generates a refresh command based on an internal refresh timer circuit provides a timing signal 4046. 在这个实施例中,通过总线A 4020-1将自刷新指令和刷新地址传输给存储块4014-1到4014-n。 In this embodiment, through the bus A 4020-1 self refresh command and refresh address transmission to the memory blocks 4014-1 to 4014-n. 因为自刷新不与A端口4011和B端口4012的指令冲突,所以不需要判优器4015确定优先权。 Since self-refresh does not conflict A port 4011 and the B port 4012 instruction, so no arbiter 4015 to determine priority. 然而,因为需要由判优器4015产生计数信号,所以也将自刷新指令提供给判优器4015。 However, because of the need by the arbiter 4015 generates a count signal, so it will self-refresh command to the arbiter 4015.

[0472] 图102是表示根据本发明的多端口存储器4010操作的一个例子的定时图。 [0472] FIG. 102 is a timing chart showing an example of a multi-port memory according to the present invention is 4010 operations.

[0473] 指令Read-x是指向存储块4014-(χ+1)的Read指令。 [0473] command Read-x is a pointer to the memory block 4014- (χ + 1) Read command. 首先将Read-Ο输入到A端口4011,然后将Read-3输入到B端口4012。 First Read-Ο input into the A port 4011, then the Read-3 is input to the B port 4012. 在这个情形中,存取的存储块是不同的,使得存储块4014-1和存储块4014-4并行地操作。 In this case, memory blocks accessed are different, so that the memory block 4014-1 and the memory block 4014-4 operate in parallel.

[0474] 此后,将Read-I输入到A端口4011,接着将Read-I输入到B端口4012。 [0474] Thereafter, the Read-I input into the A port 4011, followed by Read-I input to the B port 4012. 因为在这个情形中存取的存储块是相同的,所以产生匹配信号,取消输入到B端口4012的指令。 Because memory blocks accessed in this case is the same, so a match signal is input to the B port 4012 to cancel the command. 而且,从B端口4012的BUSY信号I/O装置4046输出BUSY-B (负逻辑值)。 Moreover, from the B port 4012 BUSY signal I / O unit 4046 output BUSY-B (negative logic value).

[0475] B端口4012的外部控制器检测BUSY-B,在切断这个信号后再次向多端口存储器4010 提供Read-I。 [0475] B port 4012 external controller detects BUSY-B, in cutting off the signal provided to the multi-port memory Read-I again 4010.

[0476] 图103是表示根据本发明的多端口存储器4010操作的另一个例子的定时图。 [0476] FIG. 103 shows another example of the multi-port memory according to the present invention, a timing diagram 4010 operation.

[0477] 图103所示的操作直到将第2个指令Read-I输入A端口4011和B端口4012,产生BUSY-B为止都与图102的相同。 Until the first two command Read-I Input A port 4011 and the B port 4012, generating 102 are the same as the operation until the BUSY-B [0477] 103 shown in FIG. 在这个例子中,在响应输入到B端口4012的Read-I发生BUSY-B后,为了在BUSY-B结束前存取另一个存储块进入读指令Read-2。 In this example, in response to an input to the B port 4012 Read-I after a BUSY-B, order before the end of BUSY-B access another memory block into the read command Read-2. 在这个方式中,只要下一个指令是指向另一个存储块的甚至在认定BUSY的周期中也能够输入下一个指令。 In this manner, as long as the next instruction is pointing to another memory block even identified BUSY cycle can enter the next command.

[0478] 图104是表示根据本发明的多端口存储器4010操作的又一个例子的定时图。 [0478] FIG. 104 is a diagram showing another example of the multi-port memory according to the present invention, a timing diagram 4010 operation.

[0479] 图104的例子表示输入Write指令的情形。 Examples [0479] Figure 104 shows the case of a Write command input. 将Read指令输入A端口4011,接着将Write指令输入B端口4012。 The Read command input A port 4011, followed by Write command input B port 4012.

[0480] 在这个实施例中,输入/输出数据是脉冲串型的。 [0480] In this embodiment, the input / output data is burst type. 即,通过从多个列地址读出并行数据,并当数据输出时在数据I/O电路4033和4043中将它变换成串行数据得到数据输出。 That is, by reading data from a plurality of parallel column address, and when the data output of the data I / O circuits 4033 and 4043 it will be converted into serial data output data obtained. 串行地输入数据输入,然后在数据I/O电路4033和4043中将它变换成并行数据,接着将并行数据写入相关存储块的多个列地址中。 Serial input data input and data I / O circuits 4033 and 4043 it will be converted into parallel data, and then the data is written to the relevant memory block parallel multiple column addresses. 使用这种脉冲串操作能够增加数据传输速率。 This burst operation using the data transfer rate can be increased. 在这个例子中,脉冲串长度为4,使连续地输出/输入4个数据项。 In this example, the burst length of 4, the continuous output / input four data items.

[0481] 在feite操作的情形,除非输入所有的4个数据项,否则不能开始Write操作。 [0481] In the case of feite operation, unless you enter all four data items, or can not start Write operation. 所以,判优器4015能够确定feite操作的优先权的定时是给出一系列串行数据输入的最后一项的定时。 Therefore, the arbiter 4015 can determine the timing of the operation feite priority is to give a series of timed serial data input of the last one.

[0482] 在图104中,A端口4011的第3个指令输入Read-3和B端口4012的第2个指令输 [0482] In Fig. 104, A port 4011 first three command input Read-3 and B-port 4012 The first two command input

企图存取同一个存储块。 Attempt to access the same memory block. 虽然B端口4012的Write_3依据指令到各端口的输入定时在其它的指令输入前面,但是在写数据最后一项进入前给出了A端口4011的Read-3。 Although the B port 4012 Write_3 based instruction to enter the ports of the timing input in front of the other instructions, but before the last one to write data into the A port 4011 is given the Read-3. 因此,判优器4015确定A端口4011的指令在其它指令的前面,并取消B端口4012的指令。 Therefore, the arbiter 4015 to determine if previous instruction A port 4011 other instructions, and cancel the B port 4012 directive.

[0483] 如图101所示,A端口4011和B端口4012分别具有CLK缓冲器4032和4042,并从器件外部接收不同的时钟信号。 [0483] As shown in Figure 101, A port 4011 and the B port 4012 respectively CLK buffers 4032 and 4042, and receive different clock signals from an external device. 各时钟信号可以具有相同或不同的相位和频率。 Each clock signal may have the same or a different phase and frequency.

[0484] 图105是表示指令译码器寄存器4034和4044的方框图。 [0484] FIG. 105 is a block diagram showing the instruction decoder registers 4034 and 4044 are.

[0485] 指令译码器寄存器40;34包括输入缓冲器4061,指令译码器4062和(n_l)时钟延迟电路4063。 [0485] command decoder register 40; 34 includes an input buffer 4061, a command decoder 4062, and (n_l) -clock delay 4063. 指令译码器寄存器4044包括输入缓冲器4071,指令译码器4072和(n_l)时钟延迟电路4073。 Command decoder register 4044 includes an input buffer 4071, a command decoder 4072, and (n_l) -clock delay 4073.

[0486] 如果输入到输入缓冲器4061或4071的指令是Read指令(RAl,RBl)或刷新指令(REFA,REFB),通过指令译码器4062或4072将输入指令传输给判优器4015而不需要任何定时操作。 [0486] If the input to the input buffer 4061 or 4071 is a Read command (RAl, RBl) or refresh command (REFA, REFB), by instruction decoder 4062 or 4072 input command is transmitted to the arbiter 4015 without require any timing manipulation. 在Write指令(WA1,WB1)的情形,输入指令被(n_l)时钟延迟电路4063或4073 延迟(n-1)个时钟周期,在给出一系列脉冲串写输入的最后的第η个数据项的定时传输给判优器4015。 In the Write command (WA1, WB1) of the case, the input command is delayed (n_l) clock delay circuit 4063 or 4073 (n-1) clock cycles, given a series of burst write input of the last data item first η timing transmitted to the arbiter 4015.

[0487] 图106是根据本发明的实施例的判优器4015的方框图。 [0487] FIG. 106 is a block diagram 4015 according to the arbiter embodiment of the present invention.

[0488] 判优器4015包括寄存器4081,延迟电路4082,传输门4083,寄存器4084,寄存器4085,延迟电路4086,传输门4087,寄存器4088,NOR电路4091和4092,NAND电路4093到4096,倒相器4097 到4101,与NOR 电路4102 和4103。 [0488] The arbiter 4015 includes a register 4081, a delay circuit 4082, a transfer gate 4083, register 4084, register 4085, a delay circuit 4086, a transfer gate 4087, register 4088, NOR circuit 4091 and 4092, NAND circuit 4093-4096, inverting It is 4097-4101, and NOR circuits 4102 and 4103.

[0489] 将从指令译码寄存器4034或4044传输过来的指令分别存储在寄存器4081或4085中。 [0489] from the instruction decoder register 4034 or 4044 respectively transmitted over the instruction stored in the register in 4081 or 4085. 当将指令输入给予A端口4011时,在是倒相器4097的输出端的节点附产生HIGH 信号。 When 4011 when the command input given to A port, in an inverted phase output node is attached 4097 HIGH signal is generated. 当将指令输入给予B端口4012时,在是倒相器4100的输出端的节点N2产生HIGH 信号。 When the command input given to the B port 4012, in an inverted phase output node N2 is 4100 HIGH signal is generated. 将W的信号或N2的信号中较早的一个锁存在节点N3或N4中。 A lock signal W signal or the presence of N2 earlier in the node N3 or N4.

[0490] 如果在A端口4011和B端口4012之间块选择地址不匹配,则地址比较器4019产生为LOW的匹配信号。 [0490] If between the A port 4011 and the B port 4012 block selection addresses do not match, the address comparator 4019 generates a match signal LOW. 所以,在这个情形中,将N5和N6设置在HIGH。 Therefore, in this case, the N5 and N6 is set in HIGH. 响应这些HIGH信号, 传输门A 4083和传输门B 4087两者都打开,无例外地将寄存器4081和4085的指令传输给寄存器4084和4088。 In response to these HIGH signals the transmission gate and a transfer gate B 4087 A 4083 both are open, without exception, will transfer registers 4081 and 4085 of 4084 and 4088 instructions to register.

[0491] 如果在A端口4011和B端口4012之间块选择地址匹配,则地址比较器4019产生为HIGH的匹配信号。 [0491] If between the A port 4011 and the B port 4012 block selection addresses match, the address comparator 4019 generates a match signal HIGH. 所以,在这个情形中,在节点N5和N6的信号电平受到在节点N3和N4 的信号电平的控制。 Therefore, in this case, the signal level at node N5 and N6 subject to the node N3 and N4 signal level control. 如果A端口4011较早,则将N5设置在HIGH,将N6设置在LOW。 If the A port 4011 earlier, N5 will be set up in HIGH, the N6 set in LOW. 响应N5的HIGH状态,传输门A 4083打开,将A端口4011的指令传输给寄存器4084。 In response to the HIGH state of N5, the transfer gate A 4083 opens, the transfer of command of the A port 4011 to register 4084. 进一步, N6的LOW状态关闭传输门B 4087,不将B端口4012的指令传输给寄存器4088。 Further, N6 the LOW state to close the transfer gate B 4087, B port 4012 not to transmit commands to the register 4088.

[0492] 而且,根据N5和N6的信号电平,产生复位信号BUSY1-A和BUSY1-B,使各寄存器4081和4085复位。 [0492] Furthermore, according to the signal level N5 and N6, and to generate a reset signal BUSY1-A and BUSY1-B, 4081 and 4085 so that all registers reset. 例如,如果选择A端口4011的指令,则产生BUSYl-B和使寄存器4085复位。 For example, if the A port 4011 instruction selection, the resulting BUSYl-B and 4085 in the register reset.

[0493] 不需要确定自刷新指令的优先权,在寄存器4084的输出级使自刷新指令与A端口4011的刷新指令REFA组合起来。 [0493] Self-refresh command does not need to determine the priority of the register output stage 4084 so that self-refresh command of the A port 4011 and the refresh command REFA combined. 在这个方式中对于A端口4011产生的刷新指令信号REFA2与B端口4012的刷新指令信号REFB2组合起来以便产生计数信号。 REFA2 refresh command signal and a refresh command signal REFB2 B port in this manner for the A port 4011 4012 generated combined signal to produce a count. 响应刷新指令的发生,从判优器4015将计数信号提供给刷新地址计数器4016。 In response to the occurrence of a refresh command from the arbiter 4015 will count signal to the refresh address counter 4016.

[0494] 图107是表示判优器4015操作的定时图。 [0494] FIG. 107 is a timing chart showing the operation of the arbiter 4015.

[0495] 图107表示在A端口4011和B端口4012之间块选择地址匹配,和A端口4011的Read指令RAl比B端口4012的Read指令RBl早的情形。 [0495] FIG. 107 shows between the A port 4011 and the B port 4012 block selection addresses match, and earlier than the B port 4012 Read instruction RBl scenario A port 4011 Read instruction RAl. 在与上述相同的方式中,节点N5 和N6的信号电平受到节点N3和N4的信号电平的控制,节点N3和N4的信号电平反应出节点附和N2的信号电平,并从判优器4015传输出Read指令RA2。 In the same manner as described above, the node N5 and N6 of the signal level by the node N3 and N4 signal level control nodes N3 and N4 of the signal level reflects the echo signal level N2 nodes, and from arbitration 4015 Transfer the Read command RA2. 取消B端口4012的Read 指令而不输出,并产生BUSYl-B信号。 Cancel B port 4012 Read command without output, and generate BUSYl-B signal.

[0496] 图108是地址缓冲器/寄存器和地址改变电路的方框图。 [0496] FIG. 108 is a block diagram of the address buffer / register and address change circuit.

[0497] 在图108中,具有在信号名称(例如RAl)的未端加上字母“P”的信号名称(例如RA1P)的信号是通过在具有后一个信号名称(例如RAl)的信号的前沿定时产生脉冲而产生的。 [0497] In Figure 108, a signal having a name (for example RAl) did not end with the letter "P" signal name (for example RA1P) of the signal is obtained by having the leading edge of the signal after a signal name (for example RAl) of the timing pulse generated.

[0498] A端口4011的地址缓冲器/寄存器40;35包括输入缓冲器40;35_1,传输门40;35_2 和OR电路4035-3。 [0498] A port 4011 of the address buffer / register 40; 35 includes an input buffer 40; 35_1, transfer gate 40; 35_2 and the OR circuit 4035-3. 对于从图105所示的指令译码器4062输出的读指令信号RA1,将前沿转变为脉冲,产生脉冲信号RA1P,然后将它加到OR电路4035-3的一个输入端。 For a read command signal RA1 output from the command decoder 4062 shown in Fig. 105, the leading edge into a pulse, generates a pulse signal RA1P, and then it is applied to an input terminal of the OR circuit 4035-3 a. 对于从图105 所示的指令译码器4062输出的写指令信号WAl,将前沿转变为脉冲,产生脉冲信号WA1P,然后将它加到OR电路4035-3的另一个输入端。 For WAl write instruction signal outputted from the instruction decoder 4062 shown in Fig. 105, the leading edge into a pulse, generates a pulse signal WA1P, and then add it to the other input terminal of the OR circuit 4035-3 a. 将OR电路4035-3的输出加到传输门4035-2 作为发出进行数据传输的指令的传输定向信号。 The output of the OR circuit 4035-3 is applied to the transfer gate 4035-2 as a data transfer instruction issued by the transmit directional signals.

[0499] B端口4012的地址缓冲器/寄存器4045包括输入缓冲器4045-1,传输门4045-2 和OR电路4045-3。 [0499] B port 4012 address buffer / register 4045 includes an input buffer 4045-1, 4045-2 and transfer gate OR circuit 4045-3. 对于B端口4012的地址缓冲器/寄存器4045的配置与对于A端口4011的地址缓冲器/寄存器4035的配置相同。 For the B port 4012 address buffer / register configuration 4045 and 4011 for the A port address buffer / 4035 of the same configuration registers.

[0500] 地址改变电路4017包括地址锁存器4017-1,传输门4017-2和4017-3,地址锁存器4017-4,与OR电路4017-5和4017-6。 [0500] address change circuit 4017 includes an address latch 4017-1, 4017-2 and 4017-3 transmission gates, the address latch 4017-4, 4017-5 and 4017-6 and OR circuit. OR电路4017-5接收信号RAlP和WAD1P,并将它的输出加到传输门4017-2作为传输指示信号。 OR circuit 4017-5 receives signals RAlP and WAD1P, 4017-2 as a transfer instructing signal and outputs it to the transmission gate. OR电路4017-6接收信号REFAP和SR-AP, 并将它的输出加到传输门4017-3作为传输指示信号。 OR circuit 4017-6 receives signals REFAP and SR-AP, and its output is applied to the transfer gate 4017-3 as a transfer instructing signal.

[0501] 地址改变电路4018包括地址锁存器4018-1,传输门4018-2和4018-3,地址锁存器4018-4,与OR电路4018-5。 [0501] address change circuit 4018 includes an address latch 4018-1, 4018-2 and 4018-3 transmission gate, the address latch 4018-4, and the OR circuit 4018-5. OR电路4018-5接收信号RBlP和WBD1P,并将它的输出加到传输门4018-3作为传输指示信号。 OR circuit 4018-5 receives signals RBlP and WBD1P, and its output is applied to the transfer gate 4018-3 as a transfer instructing signal. 又将信号RETOP加到传输门4018-2作为传输指示信号。 RETOP turn signal is applied to the transfer gate 4018-2 as a transfer instructing signal.

[0502] 当从器件外部输入Read指令或feite指令时,将与指令一起输入的地址传输给地址改变电路4017或4018。 [0502] When the input feite Read instruction or instruction from an external device, the address transmitted with the command input to the address change circuit 4017 or 4018. 在Read指令的情形中,将指令传输给地址锁存器4017-4或4018-4而不需要任何定时操作。 In the case of a Read command, the command is transmitted to the address latch 4017-4 or 4018-4 without any timing manipulation. 在Write指令的情形中,在取得一系列写数据输入的最后一项的定时将指令传输给地址锁存器4017-4或4018-4。 In the case of a Write instruction, the timing of the write data input in obtaining the last one of a series of instructions transmitted to the address latch 4017-4 or 4018-4.

[0503] 在刷新指令的情形中,在信号REFA,REFB或ER-A的定时将由刷新地址计数器4016 产生的刷新地址传输给地址锁存器4017-4或4018-4。 [0503] In the case of a refresh command, the signal REFA, REFB or timing of ER-A 4016 will be generated by the refresh address counter refresh address transmitted to the address latch 4017-4 or 4018-4.

[0504] 图109是存储块的方框图。 [0504] FIG. 109 is a block diagram of a memory block.

[0505] 图109表示存储块4014-1作为存储块4014-1到4014_n的一个例子。 [0505] FIG. 109 indicates the memory block 4014-1 as an example of the memory block to 4014_n of 4014-1. 存储块4014-1到4014-n具有相同的配置。 Memory blocks 4014-1 through 4014-n has the same configuration.

[0506] 存储块4014-1包括存储器阵列4111,控制电路4112,总线选择器4113和4114,读出放大器缓冲器4115和写放大器4116。 [0506] memory block 4014-1 includes a memory array 4111, the control circuit 4112, the bus selectors 4113 and 4114, the sense amplifier 4115 and a write buffer amplifier 4116. 存储器阵列4111包括DRAM存储单元,存储单元门晶体管,字线,位线,读出放大器,列线,列门等,并存储用于读操作和写操作的数据。 The memory array 4111 includes DRAM memory cell, the memory cell gate transistors, word lines, bit lines, sense amplifiers, column lines, columns, doors, etc., and stores the read and write operations of the data. 控制电路4112控制存储块4014-1的操作。 The control circuit 4112 controls the operation of the memory block 4014-1. 写放大器4116放大写入存储器阵列4111的数据。 Write amplifier 4116 4111 memory array write data amplifier. 读出缓冲器4115放大从存储器阵列4111读出的数据。 4115 enlarged the sense buffer 4111 is read from the memory array data.

[0507] 控制电路4112与总线A 4020-1和总线B 4020-2连接,并响应与它自己的存储块对应的相关的存储块选择地址被选出来。 [0507] The control circuit 4112 and the bus A 4020-1 and the bus B 4020-2 connection, and in response to the associated storage block with its own memory block selection address corresponding to be chosen. 当选出时,控制电路4112从已经发出相关的存储块选择地址的一条总线取得指令。 When selecting a control circuit 4112 has been issued from the relevant block selection address one bus acquisition instruction. 如果取得了总线A 4020-1指令,则控制总线选择器4113 使它向存储器阵列4111发送总线A 4020-1的地址信号。 If you made the bus A 4020-1 command, control bus selector 4113 sends it to the address signal bus A 4020-1 to the memory array 4111. 进一步,控制总线选择器4114使它将读出缓冲器4115或写放大器4116与总线A 4020-1的数据线连接起来。 Further, the control bus selector 4114 so that it will sense buffer 4115 or the write amplifier 4116 and the data lines of the bus A 4020-1 are connected. 如果取得了总线B 4020-2指令,则控制总线选择器4113使它向存储器阵列4111发送总线B 4020-2 的地址信号。 If you made the bus B 4020-2 command, control bus selector 4113 sends it to the address signal bus B 4020-2 to the memory array 4111. 进一步,控制总线选择器4114使它将读出缓冲器4115或写放大器4116与总线B 4020-2的数据线连接起来。 Further, the control bus selector 4114 so that it will sense buffer 4115 or the write amplifier 4116 and the data lines of the bus B 4020-2 are connected. 如果控制电路4112取得的指令是刷新指令,则总线选择器4114不需要操作。 If the command control circuit 4112 is a refresh command acquired, the bus selector 4114 is not required to operate.

[0508] 如上所述选择一条总线,然后,作为一系列的连续操作,连续地实施字线选择,存储单元数据放大,或者Read,Write或者Refresh (刷新),和预充电操作。 [0508] As described above select one bus, then, as a series of continuous operation, the word line selecting successively embodiment, memory cell data amplification, or Read, Write, or Refresh (refresh), and a precharge operation.

[0509] 图IlOA和IlOB是表示存储块操作的定时图。 [0509] FIG IlOA and IlOB is a timing chart showing the operation of the memory block.

[0510] 图IlOA表示读操作的情形,图IlOB表示写操作的情形。 [0510] FIG IlOA situation indicates a read operation, and FIG IlOB shows the case of a write operation. 在图IlOA和IlOB所示操作定时,响应单个指令实施字线选择,数据放大,或者读操作或者写操作,写回(数据恢复) 操作和预充电操作,从而完成要求的操作。 As shown in FIG. IlOA and IlOB operation timing, in response to a single instruction word line selection embodiment, data amplification, or read or write operation, write-back (data recovery) operation and precharge operation, thus completing the requested operation.

[0511] 在本发明(第4方面)中,如果从器件外部输入端口的指令企图存取同一个存储块,则判优电路确定各指令中的哪一个要被执行,和各指令中的哪一个不被执行。 [0511] In the present invention (fourth aspect), if an attempt to command the device from the external input port to access the same memory block, an arbitration circuit determines which one of the commands to be executed, and in which each instruction a is not executed. 例如,比较指令定时,执行较早的指令,而不执行(各)其它的指令。 For example, command timings are compared, the earlier executed instruction without performing (s) for further instructions. 当存在一个不被执行的指令时, 产生BUSY信号等并输出到器件外部。 When there is an instruction to be executed when a BUSY signals and output to external devices. 这使得甚至当在以DRAM芯为基础的多端口存储器中指令存取相互发生冲突时也可以实施适当的存取操作并实现适当的BUSY控制。 This makes it even when the DRAM-core-based multi-port memory access instructions can also perform a proper access operation is in conflict with each other and achieve proper BUSY control.

[0512] 进一步,本发明具有用于响应来自器件外部的指令实施刷新操作的操作模式,和用于响应来自内部刷新电路的指令实施刷新操作的操作模式。 [0512] Further, the present invention has a mode of operation in response to an instruction from an external device for embodiment modes of operation of the refresh operation, and a refresh circuit in response to an instruction from the internal refresh operation of the embodiment. 这使得在这样一种方式,即将预定外部端口指定作为用于在琠w的间隔接收刷新指令进行刷新管理的端口中用多端口存储器成为可能,或者使得在这样一种方式,即当所有的外部环部端口都处于去激活状态时内部刷新电路开始刷新操作中用多端口存储器成为可能。 This makes it in such a way that a predetermined external port designated as all the external constant intervals for receiving the refresh command port with multi-port memory refresh management becomes possible, or so in such a way that when When the unit ports are in the deactivated state of the internal refresh circuit starts a refresh operation with multi-port memory as possible. 因此,本发明为遵从系统要求的灵活的刷新管理提供了基础。 Accordingly, the present invention is to comply with the system requirements for flexible refresh management provides a basis.

[0513][本发明的第5方面] [0513] [Fifth aspect of the present invention]

[0514] 下面我们描述本发明的第5方面。 [0514] Here we describe a fifth aspect of the present invention.

[0515] 多端口存储器具有两组或多组输入/输出端子(即,多个输入/输出端口),并实施与接到的信号相应的存储操作。 [0515] multi-port memory having two or more sets of input / output terminals (ie, a plurality of input / output ports), and the implementation of the received signal corresponding to the store operation. 与普通的存储器不同,可以同时执行读操作和写操作。 Different from ordinary memory can perform read and write operations simultaneously. 例如,如果系统中存在多条总线,如果多个控制器(CPU等)需要用各条总线,则通过将多端口存储器的输入/输出端口与各条总线连接起来能够制成该系统。 For example, if there are multiple bus system, if a plurality of controllers (CPU, etc.) required by the various buses, the multi-port memory through the input / output port and the respective buses are connected to the system can be made. 这就消除了用特殊设计的控制逻辑电路(FIFO逻辑电路等)的需要。 This eliminates the special design of the control logic circuitry (FIFO logic circuits, etc.) needs. [0516] 而且,我们也将多个端口存储器开发成图象存储器(一般为双端口报告存储器)。 [0516] In addition, we will also develop into a multiple port memory image memory (typically dual-port report memories). 图象存储器具有随机存取端口,通过这些端口能够实现到任何存储单元的存取,和与显示装置交换数据的串行存取端口。 Video random access memory having a serial port, can be achieved through these ports to access any storage unit, and a display apparatus exchanging data with the access port.

[0517] 这类多个端口存储器在存储单元区域中采用SRAM存储芯或DRAM存储芯。 [0517] more of these port memory using DRAM or SRAM memory core memory core in the memory cell region.

[0518] 然而,我们还必须开发这样的多端口存储器,它们接收在各输入/输出端口的不同时钟信号并与时钟信号同步地随机地存取一个存储单元区域。 [0518] However, we have also developed such a multi-port memory, they receive different clock signals at respective input / output ports and with the clock signal of a random access memory cell area in synchronization. 即,我们还不知道如何制成电路的详细情况和如何控制这种时钟同步的多端口存储器。 That is, we do not know the details of how the circuit is made and how to control the multi-port memory of this clock synchronization.

[0519] 而且,常规的多端口存储器(具体地双端口存储器)具有分别对于各组输入/输出端口的位线和读出放大器。 [0519] Moreover, the conventional multi-port memory (in particular dual port memory) has the bit lines of the plurality of input / output ports and the sense amplifier, respectively. 因为这个原因,存在存储器芯的布局尺寸变大,从而不希望地增大多端口存储器的芯片尺寸的问题。 For this reason, there is a memory layout of the core size increases, thereby undesirably increasing the chip size of the multi-port memory problem.

[0520] 因此,本发明的目的是提供允许能够进行随机存取的时钟同步的多端口存储器。 [0520] Accordingly, the object of the present invention is to provide a multi-port memory capable of allowing random access of the clock synchronization.

[0521] 本发明的目的是进一步提供在各组输入/输出端口接收相互不同的时钟信号,并以可靠的方式进行操作的多端口存储器。 [0521] The present invention further provides a received clock signal different from one another in each set of input / output ports, and operate in a reliable manner of multi-port memory.

[0522] 而且本发明的目的是提供能够通过与其它的输入/输出端口的状态无关地接收在任何时间的指令信号驱动存储芯的多端口存储器。 [0522] Further object of the present invention is to provide a receiver capable of independently at any time in the multi-port memory command signal for driving the memory core via a state with other input / output ports.

[0523] 而且本发明的目的是提供具有减少的芯片尺寸的小的多端口存储器。 [0523] Further object of the present invention is to provide a small multi-port memory having a reduced chip size.

[0524] 根据本发明(第5方面),多个存储芯中的一些在加到多个输入/输出端口的时钟信号和地址信号的基础上进行操作。 [0524] According to the present invention (fifth aspect), some of the plurality of memory cores operate on the basis of the clock signal and the address signal applied to a plurality of input / output ports on. 每个输入/输出端口包括用于接收时钟信号的时钟端子,用于接收与时钟信号同步地提供的地址信号的地址端子,和用于输入/输出数据信号的数据输入/输出端口端子。 Each input / output port for receiving a clock signal, a clock terminal for receiving address synchronization clock signal supplied address signal terminals for data input and input / output data signal I / O port terminals. 为各存储芯提供控制电路。 Providing a control circuit for the memory core.

[0525] 如果地址信号指示将同一个存储芯加到两个或多个输入/输出端口,则控制电路使存储芯响应首先接到的地址信号进行操作。 [0525] If the address signals indicating the same memory core are supplied to two or more input / output ports, the control circuit of the memory core in response to address signals received first operation. 即,对于首先接收地址信号的输入/输出端口实施存储操作。 That is, the address signals received first input / output port memory operation. 可以如此定义存储芯,使它与各读出放大器区域相当,其中读出放大器区域是各读出放大器区域在其中一起操作的区域。 You can define storage core so that it and each sense amplifier area equivalent to the area in which the sense amplifier is read out each regional area in which the amplifier operating together. 由地址信号的上部分选择存储芯。 By the upper part of the address signals to select the memory core. 由地址信号的下部分选择存储芯的存储单元。 Memory core is selected by the part of the memory cell address signal. 通过与首先接到的地址信号上部分对应的输入/输出端口输入或输出到与首先接到的地址信号上部分对应的输入/输出端口,将由地址信号的下部分选择的存储单元的数据信号输入到器件外部或从器件外部输出。 Received through the first portion of the address signal corresponding to the input / output port to the input or output data signal received on the first portion of the address signal corresponding to the input / output ports, the lower portion of the address signal by a selected memory cell input to an external device or output from an external device.

[0526] 因为所要做的全部事情就是比较地址信号,所以能够将控制电路制成简单的电路。 [0526] For all that is necessary is to compare address signals, the control circuit can be made simple circuit. 这使芯片尺寸减少。 This makes the chip size reduction.

[0527] 因为每个输入/输出端口都具有时钟端子,所以对于每个输入/输出端口能够分别地控制时钟信号的频率。 [0527] For each input / output port has a clock terminal, so for each input / output port can be separately controlled frequency of the clock signal. 即,能够使具有不同操作频率的多个控制器与多端口存储器连接起来。 That is, it is possible to make a plurality of controllers having different operation frequencies and multi-port memory connected.

[0528] 在本发明的多端口存储器中,在用于取得地址信号的时钟信号的特定边沿前的预定设置时间安排地址信号。 [0528] In the multi-port memory of the present invention, in particular a predetermined set time for obtaining the address signal edge of the clock signal prior arrangement address signals. 控制电路用在时钟信号的这个特定边沿前安排的地址信号确定地址信号到达的次序。 The control circuit in order to arrange this before specific address signal edge of the clock signal to determine the address signals arrive. 因此,能够用首先接收的时钟信号的边沿确定地址信号到达的次序。 Therefore, it is possible to use the edge of the first clock signal to determine the received signal reaches the order of address. 这使在存储芯开始操作前可以识别具有优先权的输入/输出端口,从而实现高速存储操作。 This makes the memory core before starting the operation can recognize the input / output port has a priority in order to achieve high-speed storage operation. 因为在预定定时(即时钟信号的边沿)比较地址信号,所以能够防止与存储操作无关的地址信号的错误比较。 Because at a predetermined timing (i.e., the edge of the clock signal) comparing the address signals, it is possible to prevent the storage operation independent address signal miscompare.

[0529] 根据本发明,多个存储芯中的一些在加到多个输入/输出端口的时钟信号和地址信号的基础上进行操作。 [0529] According to the present invention, a plurality of memory cores operate on the basis of some of the clock signal and the address signal applied to a plurality of input / output ports on. 每个输入/输出端口包括用于接收时钟信号的时钟端子,用于接收与时钟信号同步地提供的地址信号的地址端子,和用于输入/输出数据信号的数据输入/输出端口端子。 Each input / output port for receiving a clock signal, a clock terminal for receiving address synchronization clock signal supplied address signal terminals for data input and input / output data signal I / O port terminals. 为各存储芯提供控制电路。 Providing a control circuit for the memory core.

[0530] 如果将指示同一个存储芯的地址信号加到两个或多个输入/输出端口,则控制电路使存储芯响应首先接到的地址信号进行操作。 [0530] If you would indicate the same memory address signal is applied to the core of two or more input / output ports, the control circuit of the memory core in response to address signals received first operation. 此后,控制电路使存储芯响应地址信号以接收地址信号的次序进行操作。 Thereafter, the control circuit makes the memory core in response to address signals received address signals in an order to operate. 由地址信号的上部分选择存储芯。 By the upper part of the address signals to select the memory core. 由地址信号的下部分选择存储芯的存储单元。 Memory core is selected by the part of the memory cell address signal. 通过与各地址信号对应的输入/输出端口,连续地从器件外部输入由地址信号下部分选择的存储单元的数据信号或将由地址信号下部分选择的存储单元的数据信号输出到器件外部。 By entering the address signals corresponding to each I / O port, continuously by a signal from an external input device outputs data in the data signal at the address signal portion of the selected memory cell or by the address signal portion of the selected memory cell to an external device. 因此,对于所有的接收存储操作要求的输入/输出端口没有例外地实施存储操作。 Therefore, the input / output ports for all the operational requirements of the receiving storage memory operation is no exception.

[0531] S卩,在所有时间中多端口存储器都处于备用状态。 [0531] S Jie, at all times in the multi-port memory is in a standby state. 与多端口存储器连接的控制器不一定要检测多端口存储器的忙碌状态。 The controller is connected with the multi-port memory does not have to detect a busy state of the multi-port memory. 这通过硬件和软件简化了控制器的操作。 This hardware and software simplifies the operation of the controller. 因为所要做的全部事情就是比较地址信号,所以能够将控制电路制成简单的电路。 Because all that is necessary is to compare address signals, control circuit can be made so simple circuit. 这使芯片尺寸减少。 This makes the chip size reduction.

[0532] 因为每个输入/输出端口都具有时钟端子,所以对于每个输入/输出端口能够分别地控制时钟信号的频率。 [0532] For each input / output port has a clock terminal, so for each input / output port can be separately controlled frequency of the clock signal. 即,能够使具有不同操作频率的多个控制器与多端口存储器连接起来。 That is, it is possible to make a plurality of controllers having different operation frequencies and multi-port memory connected.

[0533] 在本发明的多端口存储器中,每个输入/输出端口都具有指令端子,用于与控制存储芯操作的时钟信号同步地接收指令信号。 [0533] In the multi-port memory of the present invention, each input / output port has a command terminal for operation and control of memory core clock signal reception command signal synchronization. 在每个输入/输出端口中,在至少是读操作和写操作需要的存储芯的操作周期两倍长的间隔上,提供用于激活存储芯的指令信号。 In each of the input / output ports, at least on the operating cycle read and write operations of the memory core needs twice as long as the interval, providing a command signal for activating the memory core. 如果多端口存储器具有2个输入/输出端口或4个输入/输出端口,则可以分别将指令信号的间隔设置在操作周期的2倍或操作周期的4倍上。 If the multi-port memory having two input / output ports or four input / output ports, it can command signal interval twice or four times in the operating cycle of the operating cycle, respectively. 有了这些设置,多端口存储器处于响应外部控制器的备用状态。 With these settings, the multi-port memory is in a standby state in response to the external controller.

[0534] 如果在比预定间隔短的间隔上提供指令信号,则指令信号在防止故障方面是无效的。 [0534] If the instruction signal is provided at a predetermined interval shorter than the interval, the instruction signal in terms of preventing the malfunction is invalid. 如果将指令信号提供给不同的输入/输出端口,则即便间隔不比预定间隔短也接收这些指令信号。 If the command signal is supplied to different input / output port, even if the predetermined interval shorter than the interval also receives these command signals.

[0535] 根据本发明,进一步,从存储单元读出或写入存储单元的数据通过缓冲器在数据输入/输出端口和存储单元之间传输。 [0535] According to the present invention, further, read from the storage unit or data into the memory cell through the buffer transfer between the data input / output port and storage units. 缓冲器在其中存储具有预定在数量上等于两个或多个存储单元的位数的数据。 Buffer having stored therein a predetermined equal in number to two or more bits of the data storage units.

[0536] 在开始读操作和写操作时,例如,将具有预先确定数目的数据从存储单元传输到缓冲器。 [0536] at the beginning of the read and write operations, for example, it will have a pre-determined number of data transferred from the storage unit to the buffer. 在读操作中,从缓冲器读出与各地址信号对应的数据,并从数据输入/输出端口输出到外部装置。 In the read operation, data is read out from the buffer with the address signal corresponding to and from the data input / output to an external device. 在写操作中,将与各地址信号对应的数据存储在缓冲器中,并在写操作结束时立即将缓冲器的数据写入存储单元。 In a write operation, the signal corresponding to each address data stored in the buffer, and the data in the write buffer is written immediately to the memory cell at the end.

[0537] 在这种方式中,容易实施页面操作。 [0537] In this way, it is easy to implement page operation. 一般,当页面操作时存储芯(读出放大器等) 必须保持在激活状态。 In general, when the operation of the memory core page (readout amplifier, etc.) must be kept in an active state. 如果不提供本发明的缓冲器,则当对于输入/输出端口实施的页面操作时不可能对于另一个输入/输出端口实施存储操作。 If you do not provide a buffer of the present invention, it is impossible for another input / output port memory operation when the input / output ports page implementation operation. 在本发明中,在开始操作时将存储单元的数据传输给缓冲器,使得在这以后能够立即使存储芯去激活。 In the present invention, at the start of operation of the data transfer to the buffer storage unit, so that immediately after the memory core can be deactivated. 结果,甚至当页面操作时与多端口存储器连接的控制器也不一定要检测多端口存储器的忙碌状态。 As a result, even when the page operation with multi-port memory controller connection does not have to detect a busy state of the multi-port memory.

[0538] 下面我们参照所附各图描述本发明(第5方面)的实施例。 [0538] In the following description with reference to the accompanying figures embodiment of the present invention (fifth aspect) is. [0539] 图111表示根据本发明(第5方面)的多端口存储器的第1实施例。 [0539] FIG. 111 shows a first embodiment of the multi-port memory according to the present invention (fifth aspect) is. 用CMOS工艺在硅基片上形成多端口存储器M。 With a CMOS process for forming a multi-port memory on a silicon substrate M.

[0540] 多端口存储器M包括两个输入/输出端口PPRT-A和PORT-B,I/O电路5010,它向端口PPRT-A和PORT-B输出信号和从端口PPRT-A和PORT-B输入信号,和多个存储块MB。 [0540] multi-port memory M includes two input / output ports PPRT-A and PORT-B, I / O circuitry 5010, which the port PPRT-A and PORT-B output signals to and from the port PPRT-A and PORT-B input signal, and a plurality of memory blocks MB. 每个存储块MB都包括DRAM存储芯(包括存储单元,读出放大器线SA等),并进一步包括图中未画出的控制电路,译码器等。 Each memory block MB includes a DRAM memory core (including memory cells, sense amplifier lines SA, etc.), and further comprises a not shown control circuit, a decoder and the like. 每个存储单元包括存储与数据信号值相应的电荷的电容器。 Each memory cell includes a storage data signal value corresponding to the charge capacitor. 根据通过端口PPRT-A和PORT-B提供的行地址信号选择一个存储芯。 According to the row address signal supplied through the port PPRT-A and PORT-B select a storage core. 响应给定的存储芯的选择同时激活在给定的存储芯中的读出放大器线SA的所有读出放大器。 In response to a given memory core selection activated simultaneously read in a given memory core amplifier line in all the sense amplifier SA. 即,响应激活指令ACT激活存储芯,我们将在后面对此进行描述,并选择在这个存储芯中的所有的存储单元区域。 That is, in response to the activation command ACT activated memory core, we will be described later, and select all the memory cells in the storage area of the core. 根据读出放大器激活后提供的列地址信号在存储芯上读出读数据或写入写数据。 According to the readout column address signal amplifier activation provides readout data or writing data written in the storage core.

[0541] 图112表示多端口存储器M的I/O电路5010和存储块MB的详细情况。 [0541] FIG. 112 showing details of the multi-port memory M of the I / O circuit 5010 and the memory block MB. 在图中, 每条由粗线表示的信号线都由多条线组成。 In the drawings, each signal line represented by a thick line consists of a plurality of lines.

[0542] I/O电路5010包括模寄存器501¾和5012b,时钟缓冲器5014a和5014b, [0542] I / O circuit 5010 includes a mode register 501¾ and 5012b, 5014a and clock buffer 5014b,

[0543] 数据输入/输出缓冲器5016a和5016b,地址缓冲器/寄存器5018a和5018b,指令缓冲器5020a和5020b,与忙碌缓冲器502¾和5022b,分别与输入/输出端口PPRT-A和PORT-B对应。 [0543] data input / output buffer 5016a and 5016b, address buffer / register 5018a and 5018b, the instruction buffer 5020a and 5020b, and the busy buffer 502¾ and 5022b, respectively, and the input / output ports PPRT-A and PORT-B correspondence. 模寄存器501¾和5012b是用于从器件外部设置多端口存储器M的操作模式的寄存器。 Mode registers 501¾ and 5012b are used to set the multi-port memory M operating mode from an external device registers.

[0544] 时钟缓冲器5014a,地址缓冲器/寄存器5018a,和指令缓冲器5020a分别将时钟信号CLKA,地址信号ADDA和指令信号CMDA加到存储块MB上,就如从器件外部加上一样。 [0544] clock buffer 5014a, the address buffer / register 5018a, 5020a, respectively, and the instruction buffer clock signal CLKA, address signals ADDA, and command signals CMDA is applied to the memory block MB, plus the same as from external devices. 数据输入/输出缓冲器5016a用于从存储块MB输出数据信号DQA和将数据信号DQA输入存储块MB。 Data input / output buffer 5016a for output from the memory block MB data signal and the data signal DQA DQA input memory block MB. 忙碌缓冲器5022a向器件外部输出忙碌信号/BSYA。 Busy buffer 5022a outputs a busy signal to an external device / BSYA. 时钟缓冲器5014b,地址缓冲器/寄存器5018b,和指令缓冲器5020b分别将时钟信号CLKB,地址信号ADDB和指令信号CMDB加到存储块MB上,就如从器件外部加上一样。 Clock buffer 5014b, address buffer / register 5018b, 5020b, respectively, and the instruction buffer clock signal CLKB, address and command signals CMDB ADDB signal is applied to the memory block MB, as the same from the exterior of the device. 数据输入/输出缓冲器5016b用于从存储块MB输出数据信号DQB和将数据信号DQB输入存储块MB。 Data input / output buffer 5016b for output from the memory block MB data signals DQB and DQB data signal input memory block MB. 忙碌缓冲器5022b向器件外部输出忙碌信号/BSTO。 Busy buffer 5022b outputs a busy signal to an external device / BSTO. 时钟信号CLKA和CLKB,地址信号ADDA和ADDB和指令信号CMDA 和CMDB,数据信号DQA和DQB,与忙碌信号/BSYA和/BSTO分别通过时钟端子,地址端子,指令端子,数据输入/输出端子和忙碌端子进行传输。 Clock signals CLKA and CLKB, address signals ADDA and ADDB and command signals CMDA and CMDB, data signals DQA and DQB, and the busy signal / BSYA and / BSTO respectively by a clock terminal, address terminals, command terminals, data input / output terminals and busy transmission terminals. 提供激活指令ACT和操作指令(例如读指令RD,写指令WR)等作为用于控制存储芯操作的指令信号CMDA和CMDB。 Provides the activation command ACT and operating instructions (such as a read command RD, write command WR), etc., as command signals CMDA and CMDB for controlling memory core operations.

[0545] 提供每个地址信号ADDA和ADDB作为相互分开的行地址信号RA和列地址信号CL· 在输入/输出端口PPRT-A中,与时钟信号CLKA的前沿同步地提供行地址信号RA,列地址信号CA和指令信号CMDA。 [0545] providing each address signal ADDA and ADDB as mutually separated row address signals RA and column address signal CL · In the input / output ports PPRT-A, the row address signals RA in synchronization with the leading edge of the clock signal CLKA, the column address signals CA, and command signals CMDA. 在输入/输出端口PPRT-B中,与时钟信号CLKB的前沿同步地提供行地址信号RB,列地址信号CB和指令信号CMDB。 In the input / output ports PPRT-B, the leading edge of the clock signal CLKB to provide synchronization row address signals RB, CB column address signals and command signals CMDB. 在这个方式中,多端口存储器M分别接收专门在输入/输出端口PPRT-A和PORT-B使用的时钟信号CLKA和CLKB,并与时钟信号CLKA和CLKB同步地进行操作。 In this manner, the multi-port memory M are receiving specialized in the input / output ports PPRT-A and the clock signal CLKA and CLKB PORT-B use and operation of the clock signal CLKA and CLKB synchronization.

[0546] 存储块MB包括时钟缓冲器502½和50Mb,指令锁存器5026a和5(^6b,数据锁存器5(^8a和5(^8b,行地址锁存器5030a和5030b,列地址锁存器5031a和5031b,与列地址锁存器503¾和5032b,分别与输入/输出端口PPRT-A和PORT-B对应。存储块MB包括判优电路5034,控制信号锁存器5036,列地址计数器5038和存储芯5040,它们对于输入/ 输出端口PPRT-A和PORT-B是公用的。存储芯5040具有与时钟信号同步地取得指令信号RAS, CAS和TO,行地址信号RA和列地址信号CA的形式。 [0546] The memory block MB includes a clock buffer 502½ and 50Mb, the command latch 5026a and 5 (^ 6b, the data latch 5 (^ 8a and 5 (^ 8b, the row address latches 5030a and 5030b, the column address latches 5031a and 5031b, and the column address latch 503¾ and 5032b, respectively correspond to the input / output ports PPRT-A and PORT-B. The memory block MB includes an arbitration circuit 5034, a control signal latch 5036, a column address counter 5038 and the memory core 5040, which for the input / output ports PPRT-A and PORT-B is common. memory core 5040 having acquisition instruction signal in synchronism with the clock signal RAS, CAS, and TO, the row address signal RA and column address signals CA forms.

[0547] 当激活从判优电路5034提供的启动信号/ENA时,与输入/输出端口PPRT-A对应的模寄存器5012a,时钟缓冲器50Ma,指令锁存器5(^6a,数据锁存器5(^8a,行地址锁存器5031a,和列地址锁存器503¾进行操作。当激活从判优电路5034提供的启动信号/ENB时, 与输入/输出端口PPRT-B对应的模寄存器5012b,时钟缓冲器50Mb,指令锁存器5(^6b,数据锁存器5(^8b,行地址锁存器5031b,和列地址锁存器5032b进行操作。 [0547] When activated from the arbitration circuit 5034 provides a start signal / ENA, and input / output ports PPRT-A corresponding mode registers 5012a, clock buffer 50Ma, the command latch 5 (^ 6a, data latches 5 (^ 8a, the row address latch 5031a, and the column address latch 503¾ operation. When activated from the arbitration circuit 5034 provides an enable signal / ENB, and input / output ports PPRT-B corresponding mode register 5012b Clock buffers 50Mb, the command latch 5 (^ 6b, the data latch 5 (^ 8b, the row address latch 5031b, 5032b and the column address latch operation.

[0548] 即,在激活启动信号/ENA时,时钟缓冲器50Ma向存储芯5040的时钟端子CLK提供时钟信号CLKA。 [0548] That is, upon activation of the enable signal / ENA, the clock buffer 50Ma clock signal CLKA to a clock terminal of the memory core 5040 CLK. 进一步,指令锁存器5(^6a向控制信号锁存器5036提供锁存的指令信号CMDA,和行地址锁存器5031a向存储芯5040的行地址端子RA提供锁存的行地址信号RA (例如,与上地址位对应)。而且,列地址锁存器5032a向列地址计数器5038提供锁存的列地址信号CA (例如,与下地址位对应),和数据锁存器5028a与存储芯5040的数据输入/输出端子DQ和输入/输出缓冲器5016a交换数据信号。 Further, the command latch 5 (^ 6a to the control signal latch 5036 supplies the latched command signals CMDA, and the row address latch 5031a supplies the latched memory core 5040 to row address terminals RA row address signals RA ( For example, the upper address bits corresponding to). Further, the column address latch 5032a to the column address counter 5038 provides the latched column address signal CA (e.g., the address bits corresponding to the next), and the data latch 5028a and the memory core 5040 The data input / output terminals DQ and input / output buffer 5016a exchange data signals.

[0549] 类似地,在激活启动信号/ENB时,时钟缓冲器50¾½向存储芯5040的时钟端子CLK提供时钟信号CLKB。 [0549] Similarly, upon activation of the enable signal / ENB, the clock buffer 50¾½ the clock terminal CLK of the memory core 5040 to provide the clock signal CLKB. 进一步,指令锁存器5(^6b向控制信号锁存器5036提供锁存的指令信号CMDB,和行地址锁存器5031b向存储芯5040的行地址端子RA提供锁存的列信号RA。 而且,列地址锁存器5032b向列地址计数器5038提供锁存的列地址信号CA,和数据锁存器5028b与存储芯5040的数据输入/输出端子DQ和输入/输出缓冲器5016b交换数据信号。 Further, the command latch 5 (^ 6b to the control signal latch 5036 supplies the latched command signals CMDB, and the row address latch 5031b column signal RA of the memory core row address terminals RA 5040 provides latched Also , the column address latch 5032b supplies the latched column address counter 5038 to the column address signal CA, and the data input and the data latch 5028b of the memory core 5040 / output terminals DQ and the input / output buffer 5016b exchange data signals.

[0550] 控制信号锁存器5036根据接收的指令信号CMDA和CMDB产生用于使存储芯5040 操作的行地址选通信号RAS,列地址选通信号CAS,和写启动信号TO,并将产生的信号加到存储芯5040上。 [0550] control signal latch 5036 according to the received command signals CMDA and CMDB generation for the memory core 5040 operating row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal TO, and the resulting signal is applied to the memory core 5040. 而且,控制信号锁存器5036向判优电路5034提供指示读操作和写操作中的一个的读/写指令信号RWCMD。 Moreover, the control signal latch 5036 indicates that the read and write operations in a read / write command signal to the arbitration circuit RWCMD 5034.

[0551] 列地址计数器5038根据关于从模寄存器501¾和501¾提供的脉冲串长度的信息以及地址信号ADDA和ADDB产生列地址信号CA,并向存储芯5040输出列地址信号。 [0551] According to the column address counter 5038 generates the column address signal CA on from the mold and a burst length register 501¾ information and the address signals ADDA and ADDB 501¾ provided to the memory core 5040 outputs column address signals.

[0552] 判优电路5034包括地址比较电路5042和判优控制电路5044。 [0552] The arbitration circuit 5034 includes an address comparison circuit 5042 and the arbitration control circuit 5044. 地址比较电路5042 比较在从输入/输出端口PPRT-A和PORT-B提供的地址信号ADDA和ADDB之间的行地址信号RA,并决定它们中哪一个较早到达。 Address comparison row address signals RA address signals ADDA and compare ADDB circuit 5042 from the input / output ports PPRT-A and PORT-B provided between and decide which of them arrived earlier. 判优控制电路5044产生忙碌信号/BSYA和/BSTO与启动信号/ENA和/ENB,用于使内部电路根据地址比较电路5042的比较结果进行操作。 Arbitration control circuit 5044 generates the busy signal / BSYA and / BSTO and enable signal / ENA and / ENB, for the internal circuit operates according to the address comparison result of the comparison circuit 5042.

[0553] 图113表示地址比较电路5042的详细情况。 [0553] FIG. 113 showing details of the address comparison circuit 5042.

[0554] 地址比较电路5042包括两个地址匹配电路504¾和一个地址比较器5042b,地址比较器5042b检测地址到达的次序。 [0554] address comparison circuit 5042 includes two address matching circuits 504¾ and an address comparator 5042b, 5042b address comparator detection address arrival order. 地址匹配电路504¾包括多个EOR电路5042c,每个EOR电路5042c比较在地址信号ADDA和地址信号ADDB之间的行地址信号RA的对应位, 并进一步包括多个nMOS晶体管5042d,它们与各EOR电路5042c对应。 504¾ address matching circuit includes a plurality of EOR circuits 5042c, each of the EOR circuit 5042c compares the row address signals RA address signal ADDA and the address signal ADDB between corresponding bits, and further comprising a plurality of nMOS transistors 5042d, their respective EOR circuit 5042c correspondence. 每个nMOS晶体管5042d的栅极都与对应的EOR电路5042c的输出端连接,它们的源极接地和它们的漏极相互连接。 The gate of each nMOS transistors 5042d are connected to a corresponding output of the EOR circuit 5042c, the source thereof grounded and a drain connected to each other. 每个EOR电路5042c,当行地址信号RA的位值在输入/输出端口PPRT-A和PORT-B 之间相互匹配时输出低电平信号,当行地址信号RA的位值不匹配时输出高电平信号。 Each EOR circuit 5042c, outputs a low level signal when bit values of the row address signals RA match each other between the input / output ports PPRT-A and PORT-B, the output high when the bit values of the row address signals RA do not match signal. 响应来自EOR电路5042c的低电平信号切断nMOS晶体管5042d,响应来自EOR电路5042c的高电平信号接通nMOS晶体管5042d。 In response to the low level signal from the EOR circuit 5042c cut nMOS transistors 5042d, in response to high-level signal from the EOR circuit 5042c is turned nMOS transistors 5042d. 即,从地址匹配电路504¾输出的匹配信号/COim和/C0IN2当行地址信号RA的所有的位在对应的位之间匹配时变成浮动的,并当行地址信号的至少一个位在对应的位之间不同时变成低电平信号。 That is, from the address match signal output matching circuit 504¾ / COim and / C0IN2 when the row address signals RA of all the bits in a match between the corresponding bit becomes floating, and when the row address signal at least a bit in the corresponding bit of the Room is not the same becomes a low level signal. 将两个地址匹配电路504¾分别安排在存储块MB的上端和下端如图111所示(即,安排得接近输入/输出电路5010)。 The two address matching circuits 504¾ are arranged at the upper and lower ends of the memory block MB shown in FIG. 111 (ie, arranged close to the input / output circuit 5010). 地址匹配电路504¾接近输入/输出电路5010的安排可以缩短地址信号ADDA和ADDB到地址匹配电路504¾的整个路经上的传播延迟。 Arrange 504¾ address matching circuit close to the input / output circuit 5010 can be shortened address signal ADDA and ADDB to disseminate address matching circuit 504¾ on the entire path delay. 因此,可以在较早的定时比较地址信号ADDA和ADDB,从而得到高速操作。 Thus, at an earlier timing and comparing the address signals ADDA ADDB, thereby obtaining a high speed operation.

[0555] 比较器5042b接收匹配信号/COim和/C0IN2和时钟信号CLKA和CLKB,并输出首先到达信号/FSTA和/FSTB。 [0555] The comparator 5042b receives the match signal / COim and / C0IN2 and clock signals CLKA and CLKB, and outputs first-arrival signals / FSTA and / FSTB.

[0556] 图114表示比较器5042b的详细情况。 [0556] FIG. 114 showing the details of the comparator 5042b.

[0557] 比较器504¾包括脉冲发生器5042e,它们分别与时钟信号CLKA和CLKB的前沿同步地产生正脉冲PLSA和PLSB,并进一步包括触发器5042f,它在它的输入端子接收脉冲PLSA和PLSB。 [0557] Comparator 504¾ includes a pulse generator 5042e, they generate a positive pulse PLSA and PLSB respectively and leading edge of the clock signal CLKA CLKB in synchronization, and further including a trigger 5042f, which receives at its input terminals pulse PLSA and PLSB. 比较器5042b接收匹配信号/COim和/C0IN2并输入到分别输出脉冲PLSA 和PLSB的各倒相器。 The comparator 5042b receives the match signal / COim and / C0IN2 and input to output the pulse PLSA and PLSB of each inverter. 将在比较器5042b中产生各脉冲信号的NAND门制成小尺寸的电路元件,使得当从NAND门输出的信号具有与匹配信号/COmi和/C0IN2冲突的信号电平时将优先权给予匹配信号/COmi和/C0IN2。 Will produce NAND gate pulse signals in the comparator 5042b are made of small-sized circuit components, so that when the signal output from the NAND gate having a matching signal / COmi and / signal C0IN2 conflict usually gives priority to match the signal / COmi and / C0IN2. 触发器5042f当接收脉冲PLSA时使首先到达信号/ FSTA下降到低电平,当接收脉冲PLSB时使首先到达信号/FSTB下降到低电平。 5042f trigger the first-arrival signal / FSTA to a low level when it receives a pulse PLSA, the first-arrival signal / FSTB drops to a low level when the received pulse PLSB.

[0558] 图115表示当加到输入/输出端口PORT-A和PORT-B的行地址信号相互匹配时实施的比较器5042b的操作。 [0558] FIG. 115 indicates that when applied to the input / output ports PORT-A and the row address signal PORT-B match each other to implement the operation of the comparator 5042b. 在这个例子中,时钟信号CLKA和CLKB具有相同的周期。 In this example, the clock signals CLKA and CLKB have the same cycle.

[0559] 图113所示的地址匹配电路5042a当行地址信号RA匹配时使匹配信号/COim和/C0IN2处于浮动状态(Hi-z)。 Address shown in [0559] 113 matching circuits 5042a make matching signal when the row address signals RA match / COim and / C0IN2 in a floating state (Hi-z). 对应地,分别与时钟信号CLKA和CLKB的前沿同步地产生脉冲PLSA和PLSB(图115-(a))。 Correspondingly, a pulse PLSA and PLSB (Figure 115- (a)), respectively, and the leading edge of the clock signal CLKA CLKB in synchronization. 图114所示的触发器5042f响应在其它信号之前接收的脉冲PLSA使首先到达信号/FSTA激活(图115-(b))。 The flip-flop 5042f shown in Figure 114 in response to the received signal prior to the other so that the first-arrival signal pulses PLSA / FSTA activation (FIG. 115- (b)). 在使首先到达信号/FSTA去激活后使与以后接收的脉冲PLSB对应的首先到达信号/FSTB激活(图115-(c))。 After the first-arrival signal / FSTA deactivated so that later received pulse PLSB and the corresponding first-arrival signal / FSTB activation (FIG. 115- (c)).

[0560] 图116表示当行地址信号RA在输入/输出端口PORT-A和PORT-B之间不匹配时比较器5042b的操作。 [0560] FIG. 116 shows operations of the comparator 5042b when the row address signals RA do not match between the input / output ports PORT-A and PORT-B. 在这个例子中,时钟信号CLKA和CLKB具有相同的周期。 In this example, the clock signals CLKA and CLKB have the same cycle.

[0561] 地址匹配电路5042a当行地址信号RA甚至一个位都不匹配时使每个匹配信号/ COINl和/C0IN2降到低电平(图116-(a))。 [0561] address matching circuits 5042a address signals RA match each signal even when a bit does not match / COINl and / C0IN2 down low (Figure 116- (a)) when the line. 对应地,图114所示的脉冲发生器5042e迫使脉冲信号PLSA和PLSB降到低电平而与时钟信号CLKA和CLKB无关(图116_(b))。 Correspondingly, the pulse generator 5042e shown in FIG. 114 forces the pulse signals PLSA and PLSB reduced to low level and the clock signals CLKA and CLKB independent (FIG 116_ (b)). 因此, 首先到达信号/FSTA和/FSTB保持在高电平(图115-(c))。 Thus, the first-arrival signals / FSTA and / FSTB maintained at a high level (FIG. 115- (c)).

[0562] 图117表示当加到输入/输出端口PORT-A和PORT-B的行地址信号RA在时钟信号CLKA具有一个与时钟信号CLKB的周期不同的周期的条件下匹配时比较器5042b的操作。 Operation of the comparator 5042b match at [0562] FIG. 117, when applied to the input / output ports PORT-A and PORT-B of the row address signals RA of the clock signal CLKA having a cycle of the clock signal CLKB cycle different conditions . 在这个例子中,设置时钟信号CLKB的周期等于时钟信号CLKA的周期的两倍。 In this example, the period of the clock signal CLKB set equal to twice the period of the clock signal CLKA. 分别与时钟信号CLKA和CLKB的前沿同步地取得行地址信号RA。 Are the leading edge of the clock signal CLKA and CLKB are synchronized to the row address signal RA. 在图中,实线表示的行地址信号RA说明加到输入/输出端口PORT-A和PORT-B的信号,虚线表示的行地址信号RA说明由图112所示的各行地址锁存器5030a和5030b锁存的信号。 In the figure, the signal described the row address signals RA applied to a solid line indicates the input / output ports PORT-A and PORT-B, the row address signals RA instructions indicated by the dashed line 112 shown in FIG respective address latches 5030a and 5030b latched signal.

[0563] 当行地址信号RA匹配时,以与图115相同的方式使匹配信号/COim和/C0IN2处于浮动状态(Hi-Z)。 [0563] When the row address signals RA match, with the 115 the same way that matches the signal / COim and / C0IN2 in a floating state (Hi-Z). 当匹配信号/corni和/C0IN2处于浮动状态(Hi-Z)时,图114所示的脉冲发生器504¾发挥作用,使得分别与时钟信号CLKA和CLKB的前沿同步地产生脉冲信号PLSA和PLSB和首先到达信号/FSTA和/FSTB。 When a match signal / corni and / C0IN2 in a floating state (Hi-Z), the pulse generator 114 shown in FIG 504¾ play a role, so that each leading edge of the clock signal CLKA and CLKB pulse signal synchronization and PLSA and PLSB first arrival signals / FSTA and / FSTB.

[0564] 图118表示提供给图112所示的判优电路的判优控制电路5044。 [0564] FIG. 118 indicates to the arbiter 112 shown in arbitration control circuit 5044.

[0565] 判优控制电路5044包括控制电路504½和5044b,它们分别与输入/输出端口PPRT-A和PORT-B对应。 [0565] The arbitration control circuit 5044 includes a control circuit 504½ and 5044b, which correspond to the input / output ports PPRT-A and PORT-B, respectively. 控制电路504½接收复位信号RESETA,延迟时钟信号DCLKA,有效指令信号ACTA,首先到达信号/FSTA,忙碌信号/BSYA,并输出启动信号/ENA和忙碌信号/ BSTO。 The control circuit receives a reset signal 504½ RESETA, delayed clock signal DCLKA, an active command signal ACTA, the first-arrival signal / FSTA, the busy signal / BSYA, and output enable signal / ENA and the busy signal / BSTO. 控制电路5044b接收复位信号RESETB,延迟时钟信号DCLKB,有效指令信号ACTB,首先到达信号/FSTB,忙碌信号/BSTO,并输出启动信号/ENB和忙碌信号/BSYA。 The control circuit 5044b receives a reset signal RESETB, delayed clock signal DCLKB, an active command signal ACTB, the first-arrival signal / FSTB, the busy signal / BSTO, and output enable signal / ENB and a busy signal / BSYA.

[0566] 当完成与输入/输出端口PPRT-A和PORT-B对应的读或写操作时,在各预定周期中使复位信号RESETA和RESETB激活。 [0566] When a read or write operation is completed and the input / output ports PPRT-A and PORT-B corresponding to the respective predetermined period RESETA manipulation and RESETB reset signal activation. 延迟时钟信号DCLKA和DCLKB是分别通过使时钟信号CLKA和CLKB延迟得到的。 Delayed clock signal DCLKA and DCLKB respectively by the clock signal CLKA and CLKB delay obtained. 当将有效指令ACT加到输入/输出端口PPRT-A和PORT-B时使有效指令信号ACTA和ACTB激活。 When an active command ACT supplied to the input / output ports PPRT-A and PORT-B of the effective activation command signals ACTA and ACTB.

[0567] 图119表示当加到输入/输出端口PORT-A和P0RT-B的行地址信号匹配时实施的判优控制电路5044的操作。 [0567] FIG. 119 indicates that when applied to the input / output ports PORT-A and the row address signal P0RT-B matching the implementation of arbitration control circuit 5044 operation. 在这个例子中,时钟信号CLKA和CLKB的周期是相同的。 In this example, the clock signals CLKA and CLKB are the same cycle. 与时钟信号CLKA同步地提供有效指令ACT,立即接着与时钟信号CLKB同步地提供有效指令ACT。 Providing an active command ACT in synchronization with the clock signal CLKA, immediately followed by providing an active command ACT in synchronization with the clock signal CLKB.

[0568] 控制电路504½与延迟时钟信号DCLKA的前沿同步地取得低电平的首先到达信号/FSTA,并使忙碌信号/BSTO激活(图119- (a))。 [0568] Control and the leading edge of the delayed clock signal DCLKA synchronization circuit 504½ get low first-arrival signal / FSTA, and a busy signal / BSTO activation (Fig. 119- (a)). 响应有效指令信号ACTA的激活和忙碌信号/BSYA的去激活状态,控制电路504½激活启动信号ENA (图119_(b))。 In response to the activation of the active command signal ACTA and a busy signal / deactivated state BSYA, the control circuit 504½ activating signal ENA (Fig 119_ (b)). 因为控制电路5044b与延迟时钟信号DCLKB的前沿同步地取得高电平的首先到达信号/FSTB,所以不激活忙碌信号/BSYA(图119-(c))。 Since the control circuit 5044b and the leading edge of the delayed clock signal is synchronized to the high DCLKB first arrival signal / FSTB, so I do not activate the busy signal / BSYA (FIG. 119- (c)). 虽然控制电路5044b接受激活状态的有效指令信号ACTB, 但是因为激活了忙碌信号/BSTO,所以控制电路5044b不激活启动信号ENB(图119_(d))。 Although the control circuit 5044b receiving active command signal ACTB activated, but because the activation of the busy signal / BSTO, so the control circuit 5044b does not activate the enable signal ENB (Fig 119_ (d)).

[0569] 响应启动信号ENA的激活,将加到输入/输出端口PPRT-A的信号传输给存储芯5040。 [0569] in response to the activation signal ENA start, be added to the input / output port signal transmission PPRT-A to the memory core 5040. 激活存储芯5040,根据加到输入/输出端口PPRT-A的读指令RD实施读操作。 Activation memory core 5040 according to the input / output ports PPRT-A read command RD read operation. 在完成读操作,控制电路504½响应复位信号RESETA的激活使启动信号ENA和忙碌信号/BSTO 去激活(图119-(e))。 In a read operation, the control circuit 504½ RESETA reset signal in response to the activation enable signal ENA and the busy signal / BSTO deactivated (Figure 119- (e)).

[0570] 下面,关于其操作进一步描述上述多端口存储器M。 [0570] Hereinafter, further description regarding the operation of the multi-port memory M.

[0571] 图120表示当加到输入/输出PORT-A和PORT-B的行地址信号RA相互匹配时实施的操作。 [0571] 120 indicates when the operation is applied to the input / output PORT-A and PORT-B of the row address signals RA match each implementation. 在这个例子中,时钟信号CLKA和CLKB具有相同的周期,时钟信号CLKA的相位稍微超前时钟信号CLKB的相位。 In this example, the clock signals CLKA and CLKB have the same cycle, the phase of the clock signal CLKA is slightly ahead of the phase of the clock signal CLKB. 通过各模寄存器501¾和5012b将输入/输出端口PORT-A 和PORT-B的脉冲串长度两者都设置得等于4。 Through the mode registers 501¾ and 5012b input / output port burst length both PORT-A and PORT-B are set equal to 4. 这里,脉冲串长度是当写或读操作时输出和输入的数据项的数目。 Here, the burst length is the number of data items output and input when the write or read operation.

[0572] 与时钟信号CLKA的前沿同步地,输入/输出端口PORT-A接收有效指令ACT (指令信号CMDA)和行地址信号RA (地址信号ADDA)(图120-(a))。 [0572] and the leading edge of the clock signal CLKA in synchronization input / output ports PORT-A receives the active command ACT (command signal CMDA) and the row address signals RA (address signals ADDA) (FIG. 120- (a)). 在输入/输出端口PORT-A接收信号后立即与时钟信号CLKB的前沿同步地,输入/输出端口PORT-B接收有效指令ACT (指令信号CMDB)和行地址信号RA (地址信号ADDB)(图120- (b))。 After the input / output port PORT-A received signal and the leading edge of the clock signal CLKB immediate synchronization, the input / output port PORT-B receive active commands ACT (command signal CMDB) and the row address signals RA (address signal ADDB) (120 - (b)). 这里,指令信号CMDA和CDMB 与地址信号ADDA和ADDB在时钟信号CLKA和CLKB的各前沿前的一个预先设置时间ts (即按照定时说明)设置它们的信号电平。 Here, the command signals CMDA and CDMB address signal ADDA and ADDB set their signal level at a pre-set time ts (ie according to timing specifications) The leading edge of the clock signal CLKA and CLKB ago.

[0573] 因为加到端口PORT-B的行地址信号RA与加到端口PORT-A的行地址信号RA相同,所以一个接着一个地产生首先到达信号/FSTA和/FSTB如图115所示。 [0573] Because the port PORT-B is applied to the row address signals RA and applied to the port PORT-A row address signals RA are the same, so one by one to produce the first-arrival signal / FSTA and / FSTB 115 shown in FIG. 判优控制电路5044如结合图119所描述的响应首先到达信号/FSTA和/FSTB激活启动信号ENA和忙碌信号/BSTO (图120-(c)和(d))。 Arbitration control circuit 5044 as described in connection with FIG 119 response of first-arrival signals / FSTA and / FSTB activating signal ENA and the busy signal / BSTO (Figure 120- (c) and (d)). 在这个方式中,通过用当设置时间ts时提供的行地址信号RA和通过利用具有较早相位的时钟信号(在本例中为CLKA)的前沿,确定两个地址信号中首先到达的一个。 In this manner, by using the row address signals RA frontier when the setup time ts and provided through the use of having an earlier phase of the clock signal (in this case CLKA) to determine the two address signals first one to arrive. 此后,与行地址信号RA对应的存储芯5040响应启动信号ENA的激活进行操作(图120-(e))。 Thereafter, the row address signals RA of the memory core 5040 corresponding to the enable signal ENA in response to the activation of the operation (FIG. 120- (e)).

[0574] 响应忙碌信号/BSTO,控制器如与输入/输出端口PORT-B连接的CPU认定加到多端口存储器M的有效指令ACT是无效的。 [0574] in response to the busy signal / BSTO, controllers such as the input / output port PORT-B connected CPU identify multi-port memory M is added to the active command ACT is invalid.

[0575] 输入/输出端口PORT-A与时钟信号CLKA的下一个前沿同步地,接收读指令RD (即指令信号CMDA)和列地址信号CA (地址信号ADDA)(图120- (f))。 [0575] Input / output port next frontier PORT-A and the clock signal CLKA in synchronization, receives a read command RD (ie command signal CMDA) and column address signals CA (address signals ADDA) (Figure 120- (f)). 输入/输出端口PORT-B 与时钟信号CLKB的前沿同步地接收读指令RD(指令信号CMDB)和列地址信号CA(地址信号ADDB)(图120-(g))。 Input / output port PORT-B leading edge synchronized with the clock signal CLKB receives a read command RD (command signal CMDB) and column address signals CA (address signals ADDB) (FIG. 120- (g)). 与各时钟信号CLKA和CLKB(根据定时说明)的下一个前沿同步地,在有效指令ACT后提供读指令RD (或写指令WR)。 The next frontier with the clock signal CLKA and CLKB (according to timing specifications) in synchronization, ACT provided after a valid instruction read command RD (or write command WR). 与忙碌信号/BUSY有关,输入/输出端口PORT-B连接的控制器可以不提供读指令RD和列地址信号CA。 And the busy signal / BUSY related controller input / output port PORT-B connection may not provide a read command RD and column address signal CA.

[0576] 存储块MB连续地输出数据作为数据信号DQA (Q0-Q3)(图120-(h))如它们是从与加到输入/输出端口PORT-A的列地址信号CA对应的存储单元读出的那样。 [0576] The memory block MB successively outputs data as a data signal DQA (Q0-Q3) (FIG. 120- (h)) as they are added from the input / output port PORT-A column address signal CA corresponding to the storage unit read that. 在接收读指令RD后的2个时钟脉冲,输出数据信号DQA。 After receiving the read command RD of two clock pulses, the output data signal DQA. 在输出与脉冲串长度(=4) 一样多的数据信号DQA后,存储芯5040实施预充电操作(图120-(i)),从而完成一个存储周期。 After as much of the output of the burst length (= 4) data signals DQA, the memory core 5040 embodiment precharge operation (Fig. 120- (i)), thereby completing one memory cycle. 响应读操作的完成使启动信号ENA去激活(图120-(j))。 In response to the completion of the read operation enable signal ENA deactivated (FIG. 120- (j)). 这里,预充电操作使用于将数据传输到存储单元和从存储单元传输出来的位线充电到预定电位,使与行地址操作有关的电路去激活。 Here, the precharge operation will be used for data transfer to the storage unit from the storage unit and the bit lines are charged up to a predetermined potential, so that the row address operations associated with the deactivation circuit. 在每个存储操作中自动地实施预充电操作。 Precharge operation is automatically implemented in each memory operation. 根据存储在对应的模寄存器中的输入/输出端口PORT-A的脉冲串长度或输入/输出端口PORT-B的脉冲串长度中较长的一个确定预充电操作的定时。 The timing of the precharge operation according to the burst length burst length or type is stored in the corresponding input mode register / output port PORT-A / output port PORT-B in a longer OK. 在这个实施例中,如果脉冲串长度为4,则存储周期(即单个读或写操作需要的时间周期)被固定在4个时钟周期。 In this embodiment, if the burst length is 4, the storage period (ie, a single read or write operation required time period) is fixed at four clock cycles. 即,总是在接收到有效指令后的预定时间完成读操作和写操作。 That is, always read and write operations to complete at a predetermined time after receipt of a valid instruction.

[0577] 与用于输出数据Ql的时钟信号CLKA同步地,将下一个有效指令ACT加到输入/ 输出端口PORT-A (图120-(k))。 [0577] Ql and for outputting data in synchronism with the clock signal CLKA, the next active command ACT supplied to the input / output port PORT-A (FIG. 120- (k)). 因为在这个特定的瞬间不将指令信号CMDB加到输入/输出端口P0RT-B,所以用图113所示的地址比较电路5042比较行地址信号RA,产生指示不匹配的结果。 Because in this particular instant command signals CMDB is not supplied to the input / output port P0RT-B, so the address shown by the comparison circuit 113 5042 comparison row address signals RA, indicative of the results do not match. 因此,不激活忙碌信号/BSYA和/BSTO,只激活启动信号ENA (图120-(1))。 Thus, the busy signal is not activated / BSYA and / BSTO, only the activating signal ENA (Fig.120- (1)). 将首先到达信号/FSTA和/FSTB保存在高电平,如图116所示。 The first-arrival signals / FSTA and / FSTB save at a high level, as shown in Figure 116.

[0578] 存储芯5040根据加到输入/输出端口PORT-A的行地址信号RA进行操作,如前面描述的那样(图120-(m))。 [0578] memory core 5040 operates according to the input / output ports PORT-A row address signals RA as (FIG. 120- (m)) as previously described. 存储块MB根据与下面的时钟信号CLKA同步地提供的读指令RD和列地址信号CA —个接着一个地输出数据信号DQA(Q0-Q3)(图120-(n))。 The memory block MB according to the following clock signal CLKA supplied in synchronization with the read command RD and column address signals CA - one by one, the output data signal DQA (Q0-Q3) (FIG. 120- (n)).

[0579] 在与输入/输出端口PORT-A对应的存储芯5040的操作完成后,将有效指令ACT和读指令RD连续地加到输入/输出端口PORT-B (图120-(0))。 [0579] After the completion of the input / output port PORT-A corresponding to the operation of the memory core 5040, an active command ACT and read command RD is continuously supplied to the input / output port PORT-B (Fig.120- (0)). 因为在这个特定的瞬间不将指令信号CMDA加到输入/输出端口P0RT-A,所以存储芯5040对于输入/输出端口PORT-B 进行操作,从而输出数据信号DQB (图120-(ρ))。 Because in this particular moment the command signals CMDA is not supplied to the input / output ports P0RT-A, so that the memory core 5040 to the input / output port PORT-B operate, thereby outputting a data signal DQB (FIG. 120- (ρ)).

[0580] 虽然在图中未画出,但是响应与时钟信号的前沿同步地提供的行地址信号RA和刷新指令实施恢复在存储单元的电容器中电荷的刷新操作,其中行地址信号RA确定存储芯5040要被刷新。 [0580] Although not shown in the figure, but the row address RA and a refresh command signal in response to the leading edge of the clock signal to provide synchronization to implement recovery refresh charge in the capacitor storage unit, wherein the row address signals RA determines the storage core 5040 to be refreshed. 或者通过输入/输出端口PORT-A或者通过输入/输出端口PORT-B能够要求刷新操作。 Or through the input / output port PORT-A, or through the input / output port PORT-B to require refresh operations. 在这个方式中,由一个存储芯5040的装置根据从器件外部提供的地址信号实施刷新操作。 In this manner, by the means of a memory core 5040 according to the address signal supplied from an external device refresh operation.

[0581] 图121表示当时钟信号CLKA和CLKB相同,时钟信号CLKA的相位超前时钟信号CLKB的相位多于半个周期时实施的操作。 [0581] Figure 121 shows the same when the clock signals CLKA and CLKB, the phase of the clock signal CLKA advanced than the phase of the clock signal CLKB half cycle of operation of the embodiment. 加到多端口存储器M的指令信号CMDA和CMDB与地址信号ADDA和ADDB与图120情形中的相同。 The same applied to the multi-port memory M command signals CMDA and CMDB and the address signals ADDA and ADDB and 120 cases of.

[0582] 在这个例子中,当将有效指令ACT和行地址信号RA加到输入/输出端口PORT-A 时(图121-(a)),还没有将指令信号CMDB与地址信号ADDB加到输入/输出端口P0RT-B。 [0582] In this case, when the active command ACT and the row address signals RA supplied to the input / output ports PORT-A (FIG. 121- (a)), yet the command signal CMDB and address signals applied to the input ADDB / output port P0RT-B. 因此,激活启动信号/ENA (图121- (b)),存储芯5040对于输入/输出端口PORT-A进行操作(图121-(c))。 Thus, activation of the enable signal / ENA (FIG. 121- (b)), the memory core 5040 to the input / output port PORT-A is operated (FIG. 121- (c)). 此后,将有效指令ACT和与输入/输出端口PORT-A相同的行地址信号RA 加到输入/输出端口PORT-B (图121-⑷)。 Thereafter, the active command ACT and the input / output ports PORT-A the same row address signals RA supplied to the input / output port PORT-B (Fig. 121-⑷).

[0583] 图118所示的控制电路5044b根据首先到达信号/FSTA的激活和启动信号/ENA的激活,激活忙碌信号/BSTO (图121-(e))。 [0583] The control circuit 118 shown in FIG. 5044b based on the signal / FSTA and the activation of the enable signal / ENA first reaches activation, activate the busy signal / BSTO (FIG 121- (e)). 响应忙碌信号/BSTO,与输入/输出端口PORT-B 连接的控制器如CPU认定加到多端口存储器M的有效指令ACT是无效的。 In response to the busy signal / BSTO, controller and input / output port PORT-B connector, such as CPU identification applied to multi-port memory M of the active command ACT is invalid. 以后的操作与上述图120的相同。 After the same operation as described above in FIG. 120.

[0584] 图122表示当几乎同时加到输入/输出端口PORT-A和P0RT-B的行地址信号RA 相互不同时的操作。 [0584] FIG. 122 indicates when almost simultaneously supplied to the input / output ports PORT-A and P0RT-B of the row address signals RA differ from each other operation. 时钟信号CKLA和CLKB具有相同的时钟周期,时钟信号CLKA的相位稍微超前时钟信号CLKB的相位。 CKLA and CLKB clock signals having the same clock cycle, the phase of the clock signal CLKA is slightly ahead of the phase of the clock signal CLKB. 通过模寄存器5012对于输入/输出端口PORT-A和端口PORT-B两者都将脉冲串长度设置得等于4。 Modulo registers 5012 through the input / output ports PORT-A and PORT-B both ports are set equal to the burst length of 4.

[0585] 当行地址信号RA不同时,不同的存储芯5040进行操作。 [0585] When the row address signals RA differ, different memory cores 5040 operate. 于是图114所示的比较器5042b使首先到达信号/FSTA和/FSTB两者去激活。 So chart compares 114 5042b shown in the first-arrival signal / / FSTB both FSTA and deactivated. S卩,不进行地址判优。 S Jie, no address arbitration. 判优控制电路5044对应首先到达信号/FSTA和/FSTB的去激活状态和有效指令信号ACTA和ACTB的激活,使启动信号/ENA和/ENB激活(图121-(a)和(b))。 Arbitration control circuit 5044 corresponding to the first to reach a deactivated state signal / FSTA and / FSTB and activation signals ACTA and ACTB effective instruction, enable signal / ENA and / ENB activation (Fig. 121- (a) and (b)). 结果,相关的存储芯5040响应加到输入/输出端口PORT-A的有效指令ACT和行地址信号RA进行操作(图121- (c)),另一个存储芯5040响应加到输入/输出端口PORT-B的有效指令ACT和行地址信号RA进行操作(图121-(d))。 As a result, the associated memory core 5040 in response to the input / active command ACT and the row address signals RA output port PORT-A to operate (Figure 121- (c)), another memory core 5040 in response to the input / output port PORT -B active command ACT and the row address signals RA operations (Figure 121- (d)). S卩,输入/输出端口PORT-BA和PORT-B相互独立地进行操作。 S Jie, an input / output port PORT-BA and PORT-B operate independently of each other. 因为行地址信号RA相互不同,既不激活忙碌信号/BSYA也不激活忙碌信号/BSTO。 Since the row address signals RA differ from each other, neither the busy signal activation / BSYA is not activated busy signal / BSTO.

[0586] 在上述的实施例中,当输入/输出端口PORT-A和PORT-B接收两个指示同一个存储芯5040分别与时钟信号CLKA和CLKB同步的行地址信号RA时,存储芯5040对于在两个行地址信号RA中首先到达的一个进行操作。 [0586] In the above embodiment, when the input / output ports PORT-A and PORT-B receives two row address signals indicating the same memory core 5040 respectively with the clock signal CLKA and CLKB RA synchronization, the memory core 5040 for In the two row address signals RA first one to arrive in the operation. 即,这样我们就能够制成时钟同步型的多端口存储器M。 That is, so that we can made a clock synchronous multi-port memory M.

[0587] 判优电路5034通过比较行地址信号RA满足对它预期的所有要求,于是能够通过简单的配置制成。 [0587] The arbitration circuit 5034 satisfies all the requirements expected of it by comparing the row address signals RA, thus can be made by a simple configuration. 因此,能够使多端口存储器M的芯片尺寸减小。 Accordingly, the multi-port memory M of the chip size reduction.

[0588] 因为输入/输出端口PORT-A和PORT-B具有各自的时钟端子CLKA和CLKB,所以能够分别地对输入/输出端口PORT-A和PORT-B中的每一个设置时钟信号CLKA和CLKB的频率。 [0588] Since the input / output ports PORT-A and PORT-B have respective clock terminals CLKA and CLKB, respectively, it is possible to input / output ports PORT-A and PORT-B in each set the clock signal CLKA and CLKB frequency. 即,操作在不同操作频率上的多个控制器能够与多端口存储器M连接。 In other words, they operate at different operating frequencies of a plurality of controllers can be connected to a multi-port memory M.

[0589] 进一步,用设置在时钟信号CLKA和CLKB的相关前沿前的行地址信号RA决定两个地址中首先到达的一个。 [0589] Further, by setting determines two addresses in the first arriving in the row address signals RA a relevant cutting-edge of the clock signal CLKA and CLKB ago. 即,利用地址信号的设置时间识别首先到达的一个。 That is, set the time of the address signal identifying first one to arrive. 因此,在存储芯5040开始它的操作前能够识别将给予优先权的输入/输出端口,从而实现高速存储操作。 Thus, before the memory core 5040 starts its operation will be given priority can be identified input / output port, enabling high-speed memory operation. 进一步,因为根据具有较前相位的时钟信号CLKA(或CLKB)的前沿确定首先到达的一个,所以能够进一步提高存储操作速度。 Further, since the first arrival is determined based on the leading edge of a clock signal having the previous phase CLKA (or CLKB), it is possible to further improve the storage operation speed.

[0590] 在判优电路5034中,地址比较电路5042比较行地址信号RA,判优控制电路5044 与用于取得有效指令ACT的时钟信号CLKA和CLKB同步地检查地址匹配。 [0590] In the arbitration circuit 5034, the address comparison circuit 5042 comparative row address signals RA, arbitration control circuit 5044 and to achieve effective instruction ACT clock signals CLKA and CLKB check the address match in synchronization. 因为总是在预定定时(即在定时信号的边沿)相互比较行地址信号RA,所以可以防止由与存储操作无关的地址信号引起的存储芯5040的不正常操作。 Because there is always at a predetermined timing (ie, the edge timing of the signal) are compared with each row address signals RA, it is possible to prevent normal operation of the memory core storage operations by the independent address signal due 5040.

[0591] 图123表示多端口存储器的第2实施例和根据本发明(第5方面)控制多端口存储器的方法。 [0591] FIG. 123 shows a second embodiment of the multi-port memory and control of multi-port memory according to the (fifth aspect) of the present invention method. 用相同的数字标记与第1实施例相同的部件,并省略对它们的详细描述。 By the same numerals and the same parts of the first embodiment, and a detailed description thereof will be omitted.

[0592] 在这个实施例中,以第1实施例的四分之一大小形成存储块MB(在图中用粗线框表示)。 [0592] In this embodiment, a quarter the size of the memory block is formed of a first embodiment MB (represented in the figure by bold frame). 即,同时被激活的读出放大器的数目是第1实施例的四分之一。 That is, while the number of activated sense amplifiers in a quarter of the first embodiment. 除了存储块MB的大小外,配置与第1实施例相同。 In addition to the size of the memory block MB, the configuration of the first embodiment. 因为图123的多端口存储器M具有较少的同时被驱动的读出放大器,所以在存储操作时的功率消耗减少了。 Because the view of a multi-port memory M 123 has a reduced simultaneously driven sense amplifier, so the storage operation reduces power consumption.

[0593] 这个实施例能够产生与上述第1实施例相同的优点。 [0593] This embodiment can produce the above-described first embodiment the same advantages. 此外,在本实施例中能够降低功率消耗。 Further, in the present embodiment, power consumption can be reduced.

[0594] 图IM表示多端口存储器的第3实施例和根据本发明(第5方面)控制多端口存储器的方法。 [0594] FIG. 3 shows an embodiment of IM multi-port memory and control of multi-port memory according to the (fifth aspect) of the present invention method. 用相同的数字标记与第1实施例相同的部件,并省略对它们的详细描述。 By the same numerals and the same parts of the first embodiment, and a detailed description thereof will be omitted.

[0595] 在这个实施例中,在每个存储块MB中提供数据寄存器(缓冲器)5046a和5046b, 它们暂时存储在数据锁存器50¾和存储芯5040之间的各数据信号DQA和DQB。 [0595] In this embodiment, there is provided data registers (buffers) 5046a and 5046b in each memory block MB, they are temporarily stored in the data latches and memory core 5040 50¾ among the data signals DQA and DQB. 数据寄存器5046a和504¾与输入/输出端口PORT-A和PORT-B中的任何一个结合起来进行操作。 Data registers 5046a and 504¾ and input / output ports PORT-A and PORT-B in a combination of any operation. 而且,判优电路5034的判优控制电路5048不同于第1实施例的判优控制电路5044。 Moreover, the arbiter circuit 5034 arbitration control circuit 5048 is different from the arbitration control circuit 5044 of the first embodiment. 判优控制电路5048不输出忙碌信号/BSYA和/BSTO,在I/O电路5010中不提供忙碌缓冲器。 The arbitration control circuit 5048 does not output the busy signal / BSYA and / BSTO, does not provide busy buffers in I / O circuit 5010. 其它配置几乎与第1实施例相同。 Other configuration is almost the same as the first embodiment. 即,在输入/输出端口PORT-A和PORT-B中,分别通过时钟端子,地址端子,指令端子,和数据输入/输出端子,传输时钟信号CLKA和CLKB,地址信号ADDA和ADDB,指令信号CMDA和CMDB,与数据信号DQA和DQB。 That is, when the input / output ports PORT-A and PORT-B are, respectively, through clock terminals, address terminals, command terminals, and data input / output terminals, transfer clock signals CLKA and CLKB, address signals ADDA and ADDB, command signals CMDA and CMDB, the data signal DQA and DQB. 存储块MB包括DRAM存储芯5040,并进一步包括图中未画出的控制电路,译码器等。 The memory block MB includes a DRAM memory core 5040, and further comprising a control circuit, a decoder not shown and the like. 存储单元包括根据数据信号值存储电荷的电容器。 According to the data signal storage means comprises a capacitor storing charge values.

[0596] 甚至当输入/输出端口PORT-A和PORT-B同时接收对于同一个地址信号RA进行存储操作的要求时,这个多端口存储器M也能够对输入/输出端口PORT-A和PORT-B两者实施存储操作,我们将在后面对此进行描述。 When the [0596] even when the input / output ports PORT-A and PORT-B while receiving an address signal RA for the same storage requirements of the operation, the multi-port memory M is also capable of input / output ports PORT-A and PORT-B Both memory operation, we will be described later. 因此,如第1实施例那样不需要向器件外部输出忙碌信号/BSYA和/BSTO。 Therefore, as in the first embodiment to the device that does not require an external output busy signal / BSYA and / BSTO.

[0597] 在每个输入/输出端口PORT-A和PORT-B中,设置加上有效指令ACT间隔等于存储芯5040的操作周期的2倍以上(根据定时说明)。 [0597] In each of the input / output ports PORT-A and PORT-B, set active commands ACT interval equal to 2 times the operation period of the memory core 5040 (according to timing specifications). 如果在同一个输入/输出端口PORT-A (或P0RT-B)中有效指令ACT间隔小于上面确定的周期,则取消所加的有效指令ACT。 If the same input / output port PORT-A (or P0RT-B) in the active commands ACT interval is less than the above-determined period, it cancels the applied active command ACT. 加到不同的输入/输出端口的有效指令ACT的间隔不受限制。 Applied to different input / output ports of the active command ACT is not limited interval.

[0598] 如第1实施例那样与跟随用于接收有效指令ACT的定时的时钟信号的特定的定时同步地提供读指令RD和写指令WR。 Specific timing [0598] The active command ACT received timing of a clock signal as a first embodiment of the follower for providing synchronization with the read command RD and write command WR. 存储芯5040随着它的操作被自动地充电。 Memory core 5040 with its operation is automatically charged. 在这个实施例中,例如,将时钟信号CLKA和CLKB的周期tCLK设置在10ns,将脉冲串长度BL设置在4, 将数据等待时间DL设置在4。 In this embodiment, for example, the clock signal CLKA and CLKB cycle tCLK set at 10ns, the burst length BL is set at 4, the data latency DL is set at 4. 数据等待时间DL定义从输入读指令RD到输出数据的时钟周期的数目。 DL define the number of data latency from input to output data read command RD clock cycle. 在模寄存器501¾和5012b中设置脉冲串长度BL和数据等待时间DL。 Setting the burst length BL and the data latency DL at 501¾ and 5012b in the mode registers.

[0599] 图125表示判优控制电路5048的详细情况。 [0599] 125 shows the details of the arbitration control circuit 5048.

[0600] 通过将控制电路5048a和5048b分别加到第1实施例的控制电路504½和5044b 构造判优控制电路5048。 [0600] The control circuit 5048a and 5048b are respectively applied to the control circuit of the first embodiment of 504½ and 5044b construction arbitration control circuit 5048. 与输入/输出端口PORT-A对应的控制电路5048a从控制电路5044a接收复位信号RESETA和反向信号RVS以及启动信号/ENAO和忙碌信号/BSTO,并输出启动信号/ΕΝΑ。 And input / output ports PORT-A corresponding control circuit 5048a receives a reset signal and a reverse signal RVS RESETA and start signal / ENAO and the busy signal / BSTO from the control circuit 5044a, and output enable signal / ΕΝΑ. 与输入/输出端口PORT-B对应的控制电路5048b从控制电路5044b接收复位信号RESETB和反向信号RVS以及启动信号/ENBO和忙碌信号/BSYA,并输出启动信号/ENB。 And an input / output port PORT-B corresponding control circuit 5048b receives a reset signal RESETB and a reverse signal RVS and start signal / ENBO and the busy signal / BSYA from the control circuit 5044b, and output enable signal / ENB. 在与第1实施例的启动信号/ENA和/ENB相同的定时产生启动信号/ENAO和/ΕΝΒ0。 In the first embodiment of the enable signal / ENA and / ENB same timing as the start signal / ENAO and / ΕΝΒ0.

[0601] 图1¾表示当加到输入/输出端口PORT-A和PORT-B的行地址信号相互匹配时实施的判优控制电路5048的操作。 [0601] FIG 1¾ means that when applied to the input / output ports PORT-A and the row address signal PORT-B match each other to implement the arbitration control circuit 5048 operation. 在这个例子中,时钟信号CLKA和CLKB的周期是相同的。 In this example, the clock signals CLKA and CLKB are the same cycle. 与时钟信号CLKA同步地将有效指令ACT加到输入/输出端口PORT-Α。 With the clock signal CLKA active command ACT is supplied in synchronization with the input / output port PORT-Α. 此后立即与时钟信号CLKB同步地将有效指令ACT加到输入/输出端口PORT-B。 Immediately thereafter with the clock signal CLKB active command ACT is supplied in synchronization with the input / output port PORT-B. 与输入/输出端口PORT-A连接的控制器要求写操作,与输入/输出端口PORT-B连接的控制器要求读操作。 Controller and input / output ports PORT-A connection request write operation, the controller input / output port PORT-B connection request reads.

[0602] 控制电路504½和5044b的操作几乎与上述第1实施例的(图119)相同。 [0602] Almost 504½ circuit of the first embodiment is the same as the operation of the control and 5044b (FIG. 119). 控制电路504½与延迟时钟信号DCLKA前沿同步地取得低电平的首先到达信号/FSTA,并激活忙碌信号图126-(a))。 The control circuit and the delayed clock signal 504½ DCLKA made low level in synchronization with the leading edge first-arrival signal / FSTA, and activates the busy signal in FIG 126- (a)). 因为控制电路5044b与延迟时钟信号DCLKB前沿同步地取得高电平的首先到达信号/FSTB,不激活忙碌信号/BSYA(图126-(b))。 Since the control circuit 5044b and the leading edge of the delayed clock signal DCLKB achieved a high level in synchronization with the first-arrival signal / FSTB, do not activate the busy signal / BSYA (FIG. 126- (b)). 控制电路5048a响应忙碌信号/BSTO的激活和反向信号RVS的低电平,激活启动信号/ENA(图126-(c))。 The control circuit 5048a in response to low-level busy signal / BSTO and activation of the reverse signal RVS to activate the enable signal / ENA (FIG. 126- (c)). 控制电路5048b响应忙碌信号/BSYA的激活和反向信号RVS的低电平,使启动信号/ENB去激活(图126-(d))。 The control circuit 5048b in response to the low level busy signal / BSYA and the reverse signal RVS to activate the enable signal / ENB deactivated (FIG. 126- (d)).

[0603] 与时钟信号CLKA和CLKB的下一个定时同步地,分别提供写指令WR和读指令RD(图126-(e))。 [0603] and the clock signal CLKA and CLKB at a timing synchronization, respectively write command WR and the read command RD (Fig 126- (e)). 响应写指令WR和读指令RD,产生反向信号RVS的控制电路(图中未画出)激活反向信号RVS (图126-(f))。 Response to the write command WR and the read command RD, a reverse signal RVS control circuit (not shown) activates the reverse signal RVS (Figure 126- (f)).

[0604] 控制电路5048a和5048b分别响应反向信号RVS的激活,切换启动信号/ENA 和/ENB的电平(图126-(g))。 [0604] The control circuit 5048a and 5048b, respectively, in response to the activation of the reverse signal RVS to switch the enable signal / ENA and / ENB level (Figure 126- (g)). 然后,首先实施对于输入/输出端口PORT-B的读操作(图126-(h))。 Then, the first embodiment of the input / output port PORT-B read operation (FIG. 126- (h)). 在完成读操作后,激活复位信号RESETB,并使反向信号RVS去激活(图U6-(i))。 After the completion of the read operation, the reset signal is activated RESETB, and the reverse signal RVS to activate (Fig U6- (i)). 控制电路5048a和5048b响应反向信号RVS的去激活,使启动信号/ENA和/ENB 的电平回复到它们各自原来的电平(图126-(j))。 The control circuit 5048a and 5048b respond to the deactivation of the reverse signal RVS, enable signal / ENA and / ENB levels return to their respective original level (Figure 126- (j)). 然后,响应启动信号/ENA的激活实施对于输入/输出端口PORT-A的读操作(图126-00)。 Then, in response to start activating the implementation of signal / ENA is the input / output port PORT-A read operation (Fig. 126-00).

[0605] 在完成读操作后,激活复位信号RESETA(图1¾-(1)),并使忙碌信号/BSTO去激活(图126-(m))。 [0605] After the completion of the read operation, the reset signal activation RESETA (Fig 1¾- (1)), and the busy signal / BSTO deactivated (Figure 126- (m)). 控制电路5048a响应忙碌信号/BSTO的去激活,使启动信号/ENA去激活(图126-(η))。 The control circuit 5048a in response to the busy signal / BSTO deactivates the enable signal / ENA deactivated (FIG. 126- (η)). 在本实施例的这个方式中,当行地址信号RA相同时和当第1个到达的指令要求写操作,接着第2个到达的指令要求读操作时,如此控制存储芯5040使它首先实施读操作。 In this embodiment of the present embodiment, when the row address signals RA are the same, and when the first one to reach the requirements of the Directive writes, then the first two requirements of the Directive reach a read operation, so that it controls the memory core 5040 first read operation . 在存储器LSI,如具有多端口存储器的DRAM中,通过在接收要写的数据后驱动存储芯执行写操作,和通过首先驱动存储芯然后输出数据实施读操作。 DRAM memory LSI, such as a multi-port memory through after receiving write data driver memory core perform a write operation, and then by first driving the memory core output data read operation. 因此,当在写操作后实施读操作时,全部操作周期通常变成等待时间。 Therefore, when a read after a write operation, total operation cycles usually become waiting time. 在这个实施例中,当写操作和读相互竞争时首先执行读操作,从而缩短全部操作周期和改善传输数据信号的数据总线的使用效率。 In this embodiment, when the write and read first read operation compete with each other, thus shortening total operation cycles and improving the efficiency of transmission of data signals the data bus.

[0606] 下面,我们描述根据第3实施例的多端口存储器M的操作。 [0606] Below, we describe operation of the multi-port memory M according to the third embodiment.

[0607] 图127表示当输入/输出端口PORT-A和P0RT-B接收有效指令ACT和相同的行地址信号RA时实施读操作的方法。 [0607] FIG. 127 indicates when the input / output ports PORT-A and P0RT-B receive active commands read manner when ACT and the same row address signals RA. 时钟信号CLKA的相位稍微超前时钟信号CLKB的相位。 The phase of the clock signal CLKA is slightly ahead of the phase of the clock signal CLKB. 即,有效指令ACT到输入/输出端口PORT-A的输入稍微早于有效指令ACT进入输入/输出端口PORT-B。 Namely, an active command ACT input to the input / output port PORT-A is slightly earlier than the active command ACT to enter the input / output port PORT-B.

[0608] 对于输入/输出端口P0RT-A,响应有效指令ACT实施读操作READ (图127- (a))。 [0608] For the input / output ports P0RT-A, in response to the active command ACT read operation READ (FIG. 127- (a)). 将从存储单元读出的数据存储在数据寄存器5046a (或5046b)中。 From the storage unit reads out data stored in the data register 5046a (or 5046b) in. 然后,对于输入/输出端口PORT-B,响应有效指令ACT实施读操作READ (图127- (b))。 Then, the input / output port PORT-B, an active command ACT in response to a read operation READ (FIG. 127- (b)). 在判优电路5034的控制下完成读操作READA后对于输入/输出端口PORT-B实施读操作READB (图127- (c))。 Upon completion of the read operation READA at arbitration circuit 5034 controls the input / output port PORT-B read operation READB (Figure 127- (c)). 将通过读操作READB从存储单元读出的数据存储在数据寄存器5046b (或5046a)中(图127_(d))。 Read out from the storage unit by the read operation READB data stored in data register 5046b (or 5046a) (Fig 127_ (d)). 在这个方式中,甚至当将有效指令ACT和相同的行地址信号RA基本上同时加到输入/输出端口PORT-A和PORT-B时,也能够对于输入/输出端口PORT-A和PORT-B中的每一个连续地实施读操作(或写操作)。 In this manner, even when an active command ACT and the same row address signals RA substantially simultaneously applied to the input / output ports PORT-A and PORT-B, it is possible to input / output ports PORT-A and PORT-B Each successively read operation (or write). 存储芯4050在完成读操作READA和READB中的每一个后自动地实施预充电操作,从而完成存储周期。 Memory core 4050 in a read operation READA and READB automatic implementation of the precharge operation after each to complete the storage period.

[0609] 与图所示的第5到第8个时钟信号CLKA同步地输入读指令RD后,连续地输出存储在与输入/输出端口PORT-A对应的寄存器5046a中的检索数据作为输出数据Q1_Q3(图127- (e))。 [0609] shown in FIG fifth to eighth clock signals CLKA read command RD in synchronization input, the output is continuously retrieve data stored in the input / output ports PORT-A in the corresponding registers 5046a as output data Q1_Q3 (FIG. 127- (e)). 与图所示的第5到第8个时钟信号CLKB同步地输入读指令RD后,连续地输出存储在与输入/输出端口PORT-B对应的寄存器5046b中的检索数据作为输出数据Q1-Q3 (图127-(f))。 Input synchronization with FIG fifth to eighth clock signals CLKB read command RD, the continuous output retrieve data stored in the input / output port PORT-B in the corresponding register 5046b as output data Q1-Q3 ( FIG. 127- (f)).

[0610] 输入/输出端口PORT-A和PORT-B两者在第1有效指令ACT后的4时钟脉冲,接收下一个有效指令ACT,进一步分别实施读操作READA和READB (图127- (g)和(h))。 [0610] Input / output ports PORT-A and PORT-B in both the first active command ACT after 4 clock, receive the next active command ACT, further read operations respectively READA and READB (Figure 127- (g) and (h)). 当在每4个时钟周期中加上有效指令ACT —次时,能够连续地输出检索的数据而没有任何间隙(即,无间隙读)。 When coupled with an active command ACT in every four clock cycles - times, data can be continuously output retrieved without any gap (ie, gapless read). 而且通过在每4个时钟周期中接收有效指令ACT —次得到随机存取操作。 And by receiving every four clock cycles, an active command ACT - times to get random access operation.

[0611] 图1¾表示当将有效指令ACT和相互不同的行地址信号RA加到输入/输出端口PORT-A和PORT-B时实施读操作的方法。 [0611] FIG 1¾ indicates when active commands ACT and mutually different row address signals RA are supplied to the method of operation of the read input / output ports PORT-A and PORT-B.

[0612] 对于首先已经接收有效指令ACT和行地址信号RA的输入/输出端口P0RT-A,响应有效指令ACT实施读操作READA (图128-(a))。 [0612] For the first active command ACT has been received and the row address signals RA input / output ports P0RT-A, in response to the active command ACT read operation READA (FIG. 128- (a)). 将从存储单元读出的数据存储在数据寄存器5046a中(图128-(b))。 From the storage unit reads out data stored in the data register 5046a (Figure 128- (b)) in. 然后,输入/输出端口P0RT-B,响应有效指令ACT实施指向另一个与用于读操作READA的存储芯不同的存储芯5040的读操作READB (图128-(c))。 Then, the input / output port P0RT-B, in response to the active command ACT and for read operations directed to another memory core READA different memory core read READB 5040 (FIG. 128- (c)). 艮口, 相互独立地实施读操作READA和读操作READB。 Gen mouth, independently of each other read operation READA and read READB. 将通过读操作READB从存储单元读出的数据存储在数据寄存器5046b中(图128-(d))。 Read out from the storage unit by the read operation READB data stored in the data register 5046b (FIG. 128- (d)).

[0613] 与图所示的第5到第8个时钟信号CLKA同步地输入读指令RD后,连续地输出存储在寄存器5046a中的检索数据作为输出数据Q0-Q3(图128-(e))。 [0613] shown in FIG fifth to eighth clock signals CLKA read command RD in synchronization input, the output is continuously retrieve data stored in the register 5046a are as output data Q0-Q3 (Figure 128- (e)) . 与图所示的第5到第8个时钟信号CLKB同步地输入读指令RD后,连续地输出存储在与输入/输出端口PORT-B 对应的寄存器5046b中的检索数据作为输出数据Q0-Q3(图128-(f))。 Input synchronization with FIG fifth to eighth clock signals CLKB read command RD, the continuous output retrieve data stored in the input / output port PORT-B in the corresponding register 5046b as output data Q0-Q3 ( FIG. 128- (f)).

[0614] 输入/输出端口PORT-A和PORT-B两者在第1有效指令ACT后的4个时钟脉冲, 接收下一个有效指令ACT,进一步分别实施读操作READA和READB (图和(h))。 [0614] Input / output ports PORT-A and PORT-B in both the first active command ACT 4 clock after receive the next active command ACT, further read operations respectively READA and READB (maps and (h) ).

[0615] 图1¾表示当输入/输出端口PORT-A和PORT-B接收有效指令ACT和相同的行地址信号RA时实施写操作的方法。 [0615] FIG 1¾ method of a write operation when the input / output ports PORT-A and PORT-B receive active commands ACT and the same row address signals RA.

[0616] 在输入/输出端口PORT-A和PORT-B中,与跟随用于接收有效指令ACT的前沿的下面的各时钟信号CLKA和CLKB的前沿同步地提供写指令WR,列地址信号CA和第1写数据QO和Q0(图和(b))。 [0616] In the input / output ports PORT-A and PORT-B in, and follow for each clock signal CLKA receiving active command ACT of the frontier and the frontier following the write command WR CLKB provide synchronization, and column address signals CA The first write data QO and Q0 (Fig and (b)). 此后,与各时钟信号CLKA和CLKB同步地提供写数据Q1-Q3和Q0-Q3(图和(d))。 Thereafter, provided with the clock signal CLKA and CLKB synchronous write data Q1-Q3 and Q0-Q3 (Figure and (d)). 将写数据Q0-Q3和Q0-Q3分别存储在各数据寄存器5046a和5046b中(图和(f))。 The write data Q0-Q3 and Q0-Q3 are stored for each data registers 5046a and 5046b in (Fig and (f)). 对于首先接收有效指令ACT和行地址信号RA的输入/输出端口P0RT-A,与取得写数据Q3的时钟信号CLKA的特定的定时同步地实施写操作WRITEA (图129-(g))。 For the first receives an active command ACT and the row address signals RA input / output ports P0RT-A, and get specific timing of the write data Q3 in synchronization with the clock signal CLKA write operation WRITEA (Figure 129- (g)). 在完成写操作WRITEA后实施与输入/输出端口PORT-B对应的写操作WRITEB (图129-(h))。 After the completion of the write operation WRITEA implementation and input / output port PORT-B corresponding write operation WRITEB (Figure 129- (h)). 通过写操作WRITEA和WRITEB,将存储在各数据寄存器5046a 和5046b中的写数据Q0-Q3和Q0-Q3写入与列地址信号CA对应的存储单元,从而完成写操作。 By the write operation WRITEA and WRITEB, the write data stored in the respective data registers 5046a and 5046b of the Q0-Q3 and Q0-Q3 and the write column address signal CA corresponding to the memory cell, thereby completing the write operation.

[0617] 在写操作中,在每4个时钟周期中提供一组写数据一次,使得写数据能够连续地进入而没有任何间隙(即,无间隙写)。 [0617] In the writing operation, provides a set of write data in each of the first four clock cycles, so that write data can be continuously entered without any gap (ie, gapless write).

[0618] 图130表示对于输入/输出端口PORT-A连续地实施写操作和读操作,和对于输入/输出端口PORT-B相继地实施指向与输入/输出端口PORT-A的写操作的行地址信号RA相同的行地址信号RA的写操作,和指向与输入/输出端口PORT-A的读操作的行地址信号RA 相同的行地址信号RA的写操作的情形。 [0618] FIG. 130 represents the input / output port PORT-A is continuously write operation and a read operation, and the input / output port PORT-B are successively write operation of the row address at the input / output ports PORT-A's Signal same row address signals RA RA writes, and writes the case points to the input / output ports PORT-A read operation of the row address signals RA same row address signals RA. 第1写操作的定时与图127相同,并省略对它的说明。 127 same as the first write operation timing diagram, and its description is omitted.

[0619] 在输入/输出端口P0RT-B,在与图127相同的定时提供与第2写操作对应的有效指令ACT(图130-(a))。 [0619] In the input / output port P0RT-B, with 127 providing the same timing as the write operation corresponding to the second active command ACT (FIG. 130- (a)). 因为不将指令信号加到输入/输出端口P0RT-A,所以在取得写数据Q0-Q3后立即实施写操作WRITEB (图130-(b))。 Because it is not a command signal supplied to the input / output ports P0RT-A, so obtaining write data Q0-Q3 immediately after the implementation of a write operation WRITEB (Figure 130- (b)).

[0620] 在输入/输出端口P0RT-A,与图所示的第7个时钟信号CLKA同步地提供下一个有效指令ACT(图130-(c))。 [0620] In the input / output ports P0RT-A, as shown in FIG. 7 of the first clock signal CLKA synchronized to provide the next active command ACT (FIG. 130- (c)). 虽然在图中未画出,但是在这个特定的瞬间激活对于输入/ 输出端口PORT-B的启动信号/ENB。 Although not shown in the figures, but in this particular instant activation of the input / output port PORT-B enable signal / ENB. 结果,在完成写操作WRITEB后实施读操作READA(图130-(d))。 As a result, after the completion of the write operation WRITEB read operation READA (Figure 130- (d)). 因为多端口存储器M以接收各指令的次序执行写操作WRITEB和读操作READA, 所以在完成写操作前被读的存储单元的数据不变。 Because the multi-port memory M receives each instruction in the order of the write operation WRITEB and the read operation READA, so the data before the completion of the write operation of the memory cell to be read is unchanged.

[0621] 此外,因为输入/输出端口PORT-A能够输出存储在与输入/输出端口PORT-B对应的数据寄存器5046b中数据作为检索数据,所以可以在输入/输出端口PORT-B的写操作WRITEB前实施输入/输出端口PORT-A的读操作READA。 [0621] In addition, since the input / output port PORT-A can output stored in the input / output port PORT-B corresponding to the data in the data register 5046b as retrieval data, a write operation WRITEB can be input / output port PORT-B of before the implementation of input / output ports PORT-A read operation READA.

[0622] 图131表示对于输入/输出端口PORT-A连续地实施写操作和读操作,和对于输入/输出端口PORT-B相继地实施指向与输入/输出端口PORT-A的写操作的行地址信号RA相同的行地址信号RA的读操作和指向与输入/输出端口PORT-A的读操作的行地址信号RA 相同的行地址信号RA的写操作的情形。 [0622] FIG. 131 shows how an input / output port PORT-A is continuously write operation and a read operation, and the input / output port PORT-B are successively write operation of the row address at the input / output ports PORT-A's read and pointing and input / read row address signals RA same row address signals RA writes situation output port PORT-A signals the same row address signals RA RA's. 对于输入/输出端口PORT-A的第1写操作的定时和对于输入/输出端口PORT-B的第1读操作的定时分别与图1¾的写操作和图1¾的读操作相同。 For input / write operation of the first timing and the timing of output ports PORT-A for the input / output port PORT-B of the first read operation, respectively, in FIG 1¾ write and read operations 1¾ same.

[0623] 在输入/输出端口P0RT-A,与图所示的第7和第8时钟信号CLKA同步地提供有效指令ACT和读指令(图131-(a))。 [0623] In the input / output ports P0RT-A, providing synchronization with FIG. 7 and 8 of the first clock signal CLKA active command ACT and a read command (Figure 131- (a)). 因为在这个特定的瞬间不将有效指令ACT加到输入/ 输出端口P0RT-B,所以实施对于输入/输出端口PORT-A的读操作READA (图131-(b))。 Because in this particular moment is not an active command ACT supplied to the input / output port P0RT-B, so the implementation of the input / output port PORT-A read operation READA (Figure 131- (b)).

[0624] 下面,在输入/输出端口P0RT-B,与图所示的第8和第9时钟信号CLKB同步地提供有效指令ACT和写指令WR(图131-(c))。 [0624] Next, the input / output port P0RT-B, providing synchronization with FIG. 8 and 9, the first clock signal CLKB active command ACT and a write command WR (FIG. 131- (c)). 在接收数据Q0-Q3后,实施对于输入/输出端口PORT-B的写操作(图中未画出)。 After receiving data Q0-Q3, the implementation of the input / output port PORT-B in the write operation (not shown).

[0625] 图132表示在时钟信号CLKA和CLKB具有不同的时钟周期的情形中当加到输入/ 输出端口PORT-A和PORT-B的行地址信号相互匹配时实施的操作。 When matched implemented [0625] FIG. 132 shows a clock signal CLKA and CLKB having different clock cycles when applied to the case where the input / output ports PORT-A and PORT-B of the row address signal operation. 在这个例子中,时钟信号CLKB的周期长度等于时钟信号CLKA的周期长度的两倍。 In this example, the length of the period of the clock signal CLKB of the clock signal CLKA is equal to twice the cycle length.

[0626] 在输入/输出端口P0RT-A,当在每4个时钟周期中加上一组有效指令ACT和读指令RD —次,以与图127相同的方式实施读操作。 [0626] In the input / output ports P0RT-A, when coupled with a set of active command ACT and the read command RD in every four clock cycles - times to 127 in the same manner with the read operation. 在输入/输出端口P0RT-B,也当在每4个时钟周期中加上一组有效指令ACT和读指令RD—次。 In the input / output port P0RT-B, but also a set of an active command ACT and a read command RD- once every four clock cycles. 向输入/输出端口PORT-B输入第1有效指令ACT的时间比向输入/输出端口PORT-A输入第1有效指令ACT的时间晚一些(图132-(a))。 To the input / output port PORT-B input active command ACT first time than to the input / output port PORT-A first active command ACT input time later date (Figure 132- (a)). 因此,与图127的情形相同在读操作READA后实施读操作READB (图132-(b))。 Thus, the same as with the case of Figure 127 after the read operation READA in a read operation READB (FIG. 132- (b)). 在两个读操作READA之间执行与输入/输出端口PORT-B的跟随的有效指令ACT对应的下一个读操作READB (图132-(c))。 Between two read operations READA active command ACT performs the input / output port PORT-B corresponding to follow the next read operation READB (FIG. 132- (c)).

[0627] 本实施例能够提供与上述的第1实施例相同的优点。 [0627] The present embodiment can provide the above-described first embodiment the same advantages. 此外,在每个输入/输出端口PORT-A和PORT-B中,本实施例用等于存储芯5040的操作周期的2倍以上的有效指令ACT的间隔(按照定时说明)。 2 times more effective instruction Furthermore, in each of the input / output ports PORT-A and PORT-B, the present embodiment is equal to the memory core operation period with 5040 at intervals of ACT (according to timing specifications). 因此,甚至当加到输入/输出端口PORT-A和PORT-B的行地址信号RA相同,也肯定能够对于每个端口实施读操作和写操作。 Therefore, even when applied to the input / output ports PORT-A and PORT-B in the same row address signals RA, each port can certainly implement read and write operations for. 因此,控制多端口存储器M的控制器不需要检测多端口存储器M的忙碌状态。 Therefore, controlling the multi-port memory controller does not need to detect M multi-port memory M busy. 这样就简化了控制器的控制(藉助硬件和软件)。 This simplifies the control of the controller (via hardware and software).

[0628] 图133表示多端口存储器的第4实施例和根据本发明(第5方面)控制多端口存储器的方法。 [0628] FIG. 133 shows a fourth embodiment of the multi-port memory and control of multi-port memory according to the (fifth aspect) of the present invention method. 用相同的数字标记与第1和第3实施例相同的部件,并省略对它们的详细描述。 By the same numerals with the first and third embodiments the same parts, and a detailed description thereof will be omitted.

[0629] 在这个实施例中,提供页面缓冲器5050a和5050b代替上述第3实施例的数据寄存器5046a和5046b。 [0629] In this embodiment, page buffers 5050a and 5050b provided in place of the third embodiment of the data registers 5046a and 5046b. 页面缓冲器5050a和5050b与输入/输出端口PORT-A和PORT-B中的至少一个结合起来进行操作。 Page buffers 5050a and 5050b and input / output ports PORT-A and PORT-B at least a combined operation. 其它配置几乎与第3实施例完全相同。 Other configuration is almost identical to the third embodiment.

[0630] 每个页面缓冲器5050a和5050b都包括锁存器,其中存储在存储芯5040中的所有存储单元的数据。 [0630] Each page buffer 5050a and 5050b includes a latch, the data of all memory cells which are stored in the memory core 5040. 在开始读操作和写操作时,将存储在选出的存储芯5040的存储单元中的数据读出到页面缓冲器5050a (或5050b)。 At the beginning of the read and write operations, the read data stored in the selected memory cell storage unit 5040 in the page buffer 5050a (or 5050b). 在读操作中,响应列地址信号CA输出锁存在页面缓冲器5050a中的数据作为数据信号。 In a read operation, in response to the column address signal CA output latched data page buffer 5050a as a data signal. 在写操作中,首先根据列地址信号CA将数据信号写入页面缓冲器5050a。 In a write operation, the column address signal CA according to the first data signal is written to the page buffer 5050a. 此后,在完成写操作时将页面缓冲器5050a的数据写入存储单元。 Thereafter, upon completion of the write operation of the page buffer 5050a of data written to the storage unit.

[0631] 下面,我们描述第4实施例多端口存储器M的操作。 [0631] In the following, we describe a fourth embodiment of the multi-port memory M of operation.

[0632] 图134表示当输入/输出端口PORT-A和P0RT-B接收有效指令ACT和相同的行地址信号RA时实施读操作的方法。 [0632] FIG. 134 showing the method of read operations when the input / output ports PORT-A and P0RT-B receive active commands ACT and the same row address signals RA. 时钟信号CLKA的相位稍微超前时钟信号CLKB的相位。 The phase of the clock signal CLKA is slightly ahead of the phase of the clock signal CLKB. 即,输入到输入/输出PORT-A的有效指令ACT比输入到输入/输出PORT-B的有效指令ACT That is, the input to the active command input / output PORT-A of ACT than active command ACT input to the input / output PORT-B's

稍微早一些。 A little earlier.

[0633] 在输入/输出端口P0RT-A,响应有效指令ACT实施读操作READA (图134- (a))。 [0633] In the input / output ports P0RT-A, in response to the active command ACT read operation READA (FIG. 134- (a)). 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并将检索数据存储在页面缓冲器5050a (或5050b)中的一个(图134-(b))。 The read operation READA selected from the group consisting of all the memory cells of the memory core 5040 are read out, and retrieve data stored in a page buffer 5050a (or 5050b) (FIG. 134- (b)). 另一方面,在输入/输出端口P0RT-B,行地址信号RA与加到输入/输出端口PORT-A的相同,所以不实施与有效指令ACT相应的读操作。 On the other hand, the input / output port P0RT-B, the row address signals RA supplied to the input / output port PORT-A is the same, it is not the active command ACT corresponding read operation.

[0634] 在输入/输出端口P0RT-A,与如图所示的第1和第5时钟信号CLKA同步地加上读指令RD (图134-(c)和(d))。 In the input / output ports P0RT-A, 1st and 5th clock signals CLKA shown in the figure in synchronization with the [0634] a read command RD (FIG. 134- (c) and (d)). 在接收各读指令RD后与第5到第12时钟信号CLKA同步地连续输出存储在页面缓冲器5050a中的数据作为输出数据Q0-Q7 (图134- (e))。 After receiving the respective read commands RD and the fifth to the 12th clock signals CLKA continuous output synchronization data in the page buffer 5050a are stored as output data Q0-Q7 (Fig 134- (e)). 即,实施页面读操作。 That is, a page read operation.

[0635] 由于同样的原因,在输入/输出端口P0RT-B,与如图所示的第1和第5时钟信号CLKB同步地加上读指令RD (图134-(f)和(g))。 [0635] For the same reason, the input / output port P0RT-B, with the 1st and 5th clock signals CLKB shown in the figure in synchronization plus a read command RD (FIG. 134- (f) and (g)) . 在接收各读指令RD后与第5到第12时钟信号CLKB同步地连续输出存储在页面缓冲器5050a中的数据作为输出数据Q0-Q7 (图134-(h))。 After receiving the respective read commands RD and 5 to 12 continuous clock signal CLKB output synchronization data stored in the page buffer 5050a as output data Q0-Q7 (FIG. 134- (h)). 在这个方式中,如果行地址信号RA是相同的,则输入/输出端口PORT-A和PORT-B共用一个页面缓冲器5050a (或5050b)。 In this manner, if the row address signals RA are the same, the input / output ports PORT-A and PORT-B share a page buffer 5050a (or 5050b).

[0636] 输入/输出端口PORT-A和PORT-B两者都在第1有效指令ACT后的8个时钟周期, 接收下一个有效指令ACT(图134-(i)和(j))。 [0636] Input / output ports PORT-A and PORT-B are both in the first active command ACT 8 clock cycles after receiving next valid command ACT (FIG. 134- (i) and (j)). 因为行地址信号RA是相同的,所以只实施读操作READA (图134-(k))。 Since the row address signals RA are the same, only a read operation READA (FIG. 134- (k)). 不实施对于输入/输出端口PORT-B的读操作READB。 Without respect to the input / output port PORT-B read operation READB. 通过在每4个时钟周期中加上读指令RD —次能够连续地输出读数据而没有任何间隙(即,无间隙读)。 By every four clock cycles plus a read command RD - times read data can be continuously output without any gap (ie, gapless read).

[0637] 图135表示当将有效指令ACT和不同的行地址信号RA加到输入/输出端口PORT-A 和PORT-B时实施读操作的方法。 [0637] FIG. 135 indicates when active commands ACT and different row address signals RA are supplied to the method of operation of read input / output ports PORT-A and PORT-B. 与输入/输出端口PORT-A对应的读操作的定时和图134 相同。 The same input / output port PORT-A read operation corresponding to the timing and 134.

[0638] 在首先接收有效指令ACT和行地址信号RA的输入/输出端口P0RT-A,响应有效指令ACT实施读操作READA (图135-(a))。 [0638] In the first receiving active command ACT and the row address signals RA input / output ports P0RT-A, in response to the active command ACT read operation READA (FIG. 135- (a)). 将从存储芯5040的所有存储单元读出的数据存储在页面缓冲器5050a中(图135- (b))。 All the memory cells from the memory core 5040 read data stored in the page buffer 5050a (Figure 135- (b)) in. 在输入/输出端口P0RT-B,响应有效指令ACT对于与读操作READA的不同的存储芯5040实施读操作READB(图135_(c))。 In the input / output port P0RT-B, in response to the active command ACT and the read operation READA of the memory core 5040 different read operation READB (FIG 135_ (c)). S卩,将由读操作READB 从存储芯5040的所有存储单元读出的数据存储在页面缓冲器5050b中(图135-(d))。 S Jie, will read READB read from all the memory cells of the memory core 5040 data is stored in the page buffer 5050b (FIG. 135- (d)). 此后,以与结合图134描述的相同方式实施读操作。 Thereafter, in the same manner as described in connection with FIG. 134 a read operation. 在这个方式中,当行地址信号RA相互不同时,独立的实施读操作READA和读操作READB,分别将检索数据存储在各页面缓冲器5050a 和5050b中。 In this manner, when the row address signals RA differ from each other, separate read operation READA and read READB, respectively, to retrieve data stored in the page buffer 5050a and 5050b in.

[0639] 图136表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,并实施写操作,接着加上有效指令ACT和不同的行地址信号RA,导致实施写操作的情形。 [0639] FIG. 136 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, and a write operation, followed by active commands ACT and different row address signals RA, led to the imposition case of a write operation.

[0640] 在输入/输出端口PORT-A和PORT-B,与时钟信号CLKA和CLKB的各前沿同步地加上有效指令ACT和相同的行地址信号RA。 In the input / output ports PORT-A and PORT-B, in synchronization with the [0640] and the clock signal CLKA and CLKB each frontier active commands ACT and the same row address signals RA. 图133所示的判优电路5034认定输入/输出端口PORT-A首先接收有效指令ACT,并实施读操作READA (图136- (a)),以便将数据从存储单元传输到页面缓冲器5050a (或5050b)。 133 arbitration circuit 5034 shown in identified input / output ports PORT-A which received the active command ACT, and a read operation READA (FIG. 136- (a)), so that the data from the storage unit is transferred to the page buffer 5050a ( or 5050b).

[0641] 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并存储在页面缓冲器5050a (或5050b)中(图136_(b))。 [0641] READA selected by the read operation from the memory core 5040 of all the memory cells read out and stored in the page buffer 5050a (or 5050b) (Fig 136_ (b)). 另一方面,在输入/输出端口P0RT-B,因为行地址信号RA与加到输入/输出端口PORT-A的相同,所以响应有效指令ACT不实施读操作。 On the other hand, the input / output port P0RT-B, since the row address signals RA supplied to the input / output port PORT-A identical, so in response to the active command ACT is not a read operation.

[0642] 此后,在输入/输出端口P0RT-A,与如图所示的第1和第5时钟信号CLKA同步地加上写指令WD和列地址信号CA (图136-(c)和(d))。 [0642] Thereafter, the input / output ports P0RT-A, 1st and 5th clock signals CLKA shown in the figure in synchronization plus the write command WD and column address signals CA (FIG. 136- (c) and (d )). 将与钟信号CLKA同步地连续加上的写数据Q0-Q7写入页面缓冲器5050a中(图134-(e))。 The continuous coupled with the clock signal CLKA synchronized write data Q0-Q7 written in the page buffer 5050a (FIG. 134- (e)). 即,实施页面写操作。 That is, a page write operation.

[0643] 在输入/输出端口P0RT-B,与如图所示的第1和第5时钟信号CLKB同步地加上写指令WR和列地址信号CA (图136-(f)和(g))。 In the input / output port P0RT-B, together with the write command WR and column address signals CA [0643] and the first and second clock signals CLKB shown in Figure 5 in synchronization (Figure 136- (f) and (g)) . 将与时钟信号CLKB同步地一个接一个地加上的写数据Q0-Q7写入共用的列页面缓冲器5050a中(图134_(h))。 Will be in synchronization with the clock signal CLKB one after Write data Q0-Q7 Write community column page buffer 5050a (FIG 134_ (h)). 在这个方式中,如果行地址信号RA相同,则在写操作中输入/输出端口PORT-A和PORT-B共用同一个页面缓冲器5050a (或5050b)。 In this manner, if the row address signals RA are the same, in a write operation input / output ports PORT-A and PORT-B share the same page buffer 5050a (or 5050b).

[0644] 在首先接收有效指令ACT的输入/输出端口P0RT-A,与取得写数据Q7的时钟信号CLKA的特定定时同步地实施写操作WRITEA (图136-(i))。 [0644] In the first receiving active command ACT input / output ports P0RT-A, synchronization implementation and get specific timing of the write data Q7 write clock signal CLKA WRITEA (Figure 136- (i)). 在完成写操作WRITEA后实施与输入/输出端口PORT-B对应的写操作WRITEB (图136- (j))。 After the completion of the write operation WRITEA implementation and input / output port PORT-B corresponding write operation WRITEB (Figure 136- (j)).

[0645] 此后,在输入/输出端口PORT-A和P0RT-B,与时钟信号CLKA和CLKB的各前沿同步地加上有效指令ACT和相互不同的行地址信号RA。 Thereafter, the input / output ports PORT-A and P0RT-B, in synchronization with the [0645] and the clock signal CLKA and CLKB each forefront of active commands ACT and mutually different row address signals RA. 图133所示的判优电路5034认定首先将有效指令ACT加到输入/输出端口P0RT-A,并一个接着一个地实施读操作READA和READB (图136-(k)禾Π (1))。 133 arbitration circuit 5034 shown ascertains that the active command ACT is supplied to the input / output ports P0RT-A, and one by one read operation READA and READB (Figure 136- (k) Wo Π (1)).

[0646] 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并存储在页面缓冲器5050a(或5050b)中(图136_(m))。 [0646] READA selected by the read operation from the memory core 5040 of all the memory cells read out and stored in the page buffer 5050a (or 5050b) (Fig 136_ (m)). 进一步,从由读操作READB选出的存储芯5040的所有存储单元读出数据,并存储在另一个页面缓冲器5050b (或5050a)中(图136_(n))。 Further, the read operation READB selected from the group consisting of all the memory cells of the memory core 5040 read out and stored in another page buffer 5050b (or 5050a) (Fig 136_ (n)).

[0647] 在输入/输出端口P0RT-A,与如图所示的第13和第17时钟信号CLKA同步地加上读指令RD和列地址信号CA (图136- (ο)和(ρ))。 [0647] In the input / output ports P0RT-A, 13 and 17 of the first clock signal CLKA shown in the figure in synchronization plus a read command RD and column address signals CA (FIG. 136- (ο) and (ρ)) . 将与钟信号CLKA同步地一个接着一个加上的写数据Q0-Q7存储在页面缓冲器5050a中(图136-(q))。 One after another in synchronization plus the write data Q0-Q7 with the clock signal CLKA are stored in the page buffer 5050a (FIG. 136- (q)).

[0648] 类似地,在输入/输出端口P0RT-B,与如图所示的第13和第17时钟信号CLKB同步地加上写指令WR和列地址信号CA (图136-(r)和(s))。 [0648] Similarly, in the input / output port P0RT-B, 13 and 17 of the clock signal CLKB shown in the figure in synchronization plus the write command WR and column address signals CA (FIG. 136- (r) and ( s)). 将与钟信号CLKB同步地一个接着一个加上的写数据Q0-Q7写入页面缓冲器5050b中(图136-(t))。 One after another in synchronization plus the write data and clock signals CLKB Q0-Q7 written in the page buffer 5050b (FIG. 136- (t)). 在这个方式中,当行地址信号RA不同时用页面缓冲器5050a和5050b。 In this manner, when the row address signals RA is not the same with the page buffer 5050a and 5050b.

[0649] 在首先接收有效指令ACT和行地址信号RA的输入/输出端口P0RT-A,与取得写数据Q7的时钟信号CLKA的特定定时同步地实施写操作WRITEA (图136-(u))。 [0649] In the first receiving active command ACT and the row address signals RA input / output ports P0RT-A, made the implementation of specific timing synchronization with the write data Q7 clock signal CLKA writes WRITEA (Figure 136- (u)). 在完成写操作WRITEA后实施与输入/输出端口PORT-B对应的写操作WRITEB (图136-(ν))。 After the completion of the write operation WRITEA implementation and input / output port PORT-B corresponding write operation WRITEB (Figure 136- (ν)). 通过写操作WRITEA和WRITEB,分别将存储器在页面缓冲器5050a和5050b中的写数据Q0-Q7写入与列地址信号CA对应的存储单元,从而完成写操作。 By the write operation WRITEA and WRITEB, the write data, respectively, in the memory page buffers 5050a and 5050b of the Q0-Q7 write column address signal CA corresponding to the memory cell, thereby completing the write operation.

[0650] 图137表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,实施写操作,接着加上有效指令ACT和相同的行地址信号RA,导致在输入/输出端口PORT-A实施读操作和在输入/输出端口PORT-B实施写操作的情形。 [0650] FIG. 137 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, a write operation, followed by active commands ACT and the same row address signals RA, leading to read operation on the input / output ports PORT-A and the input / output port PORT-B implementation case write operation. 第1写操作的定时与图137相同,我们将省略对它的描述。 The same as the first write operation timing diagram 137, the description will be omitted.

[0651] 在输入/输出端口PORT-A和P0RT-B,与图所示的第12时钟信号CLKA和CLKB的各前沿同步地提供有效指令ACT和相同的行地址信号RA(图137-(a)和(b))。 [0651] In the input / output ports PORT-A and P0RT-B, to provide effective instruction ACT and the same row address signals RA in synchronization with the leading edge of the first clock signal CLKA and CLKB 12 shown in FIG. (FIG. 137- (a ) and (b)). 图133所示的判优电路5034认定首先将有效指令ACT加到输入/输出端口P0RT-A,并实施读操作READA(图137-(c))。 133 arbitration circuit 5034 shown ascertains that the active command ACT is supplied to the input / output ports P0RT-A, and a read operation READA (Figure 137- (c)). 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并存储在页面缓冲器5050a (或5050b)中(图137_(d))。 READA selected by the read operation from the memory core 5040 of all the memory cells read out and stored in the page buffer 5050a (or 5050b) (Fig 137_ (d)). 在输入/输出端口P0RT-B,因为行地址信号RA与加到输入/输出端口PORT-A的信号相同,所以不实施与有效指令ACT对应的写操作。 In the input / output port P0RT-B, since the row address signals RA supplied to the input / output port of the same signal PORT-A, it is not the active command ACT corresponding write operation.

[0652] 此后,在输入/输出端口P0RT-A,与如图所示的第13和第17时钟信号CLKA同步地加上读指令RD(图137-(e)和(f))。 [0652] Thereafter, the input / output ports P0RT-A, 13 and 17 of the clock signal CLKA shown in the figure in synchronization plus a read command RD (Fig 137- (e) and (f)). 在接收各读指令RD后与如图所示的第17到第M 时钟信号CLKA同步地连续输出存储在页面缓冲器5050a中的数据(图137-(g))。 17 to M-th clock signals CLKA after receiving the respective read commands RD as shown in synchronism with the continuous output data (FIG. 137- (g)) is stored in the page buffer 5050a.

[0653] 在输入/输出端口P0RT-B,与如图所示的第13和第17时钟信号CLKB同步地加上写指令WR(图137-(h)和(i))。 [0653] In the input / output port P0RT-B, 13 and 17 of the clock signal CLKB shown in the figure in synchronization plus the write command WR (FIG. 137- (h) and (i)). 将与钟信号CLKB同步地连续加上的写数据Q0-Q7存储在共用的页面缓冲器5050a中(图137-( j))。 The continuous coupled with the clock signal CLKB write data in synchronization Q0-Q7 stored in the common page buffer 5050a (FIG. 137- (j)).

[0654] 此后,在输入/输出端口P0RT-B,与取得写数据Q7的时钟信号CLKB的特定定时同步地实施写操作WRITEB (图137-(k))。 [0654] Thereafter, the input / output port P0RT-B, and made specific timing of the write data Q7 in synchronization with the clock signal CLKB write operation WRITEB (Figure 137- (k)).

[0655] 图138表示将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和P0RT-B,实施写操作和读操作,接着加上有效指令ACT和不同的行地址信号RA,导致实施写操作和读操作的情形。 [0655] FIG. 138 shows a valid command ACT and the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, a write operation and a read operation, followed by active commands ACT and different row address signals RA, leading to the implementation of the case of a write operation and a read operation.

[0656] 在输入/输出端口PORT-A和P0RT-B,与时钟信号CLKA和CLKB的前沿同步地提供有效指令ACT和相同的行地址信号RA (图138-(a)和(b))。 [0656] In the input / output ports PORT-A and P0RT-B, providing synchronization with the leading edge of the clock signal CLKA and CLKB of active commands ACT and the same row address signals RA (FIG. 138- (a) and (b)). 判优电路5034确定首先将有效指令ACT加到输入/输出端口P0RT-A,并实施读操作READA(图138_(c))。 Arbitration circuit 5034 determines that the active command ACT supplied to the input / output ports P0RT-A, and a read operation READA (Fig 138_ (c)). 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并将读出数据存储在页面缓冲器5050a(或5050b)中(图137_(d))。 The read operation READA selected from the group consisting of all the memory cells of the memory core 5040 read data, and read data stored in the page buffer 5050a (or 5050b) (Fig 137_ (d)). 另一方面,在输入/输出端口P0RT-B,行地址信号RA 与加到输入/输出端口PORT-A的那些相同,所以不实施与有效指令ACT对应的读操作。 On the other hand, the input / output port P0RT-B, the row address signals RA supplied to the input / output ports are identical to those PORT-A, it is not the active command ACT corresponding to the read operation.

[0657] 此后,在输入/输出端口P0RT-A,与第1和第5时钟信号CLKA同步地加上写指令WR(图138-(e)和(f))。 Thereafter, the input / output ports P0RT-A, in synchronization with the [0657] and the first and the fifth clock signal CLKA write command WR (Fig 138- (e) and (f)). 将与时钟信号CLKA同步地连续加上的写数据Q0-Q7存储在页面缓冲器5050a中(图137-(g))。 The continuous coupled with the clock signal CLKA synchronized write data Q0-Q7 stored in the page buffer 5050a (FIG. 137- (g)) at.

[0658] 在输入/输出端口P0RT-B,与第1和第5时钟信号CLKB同步地加上读指令RD (图138-(h)和(i))。 [0658] In the input / output port P0RT-B, with the 1st and 5th clock signals CLKB synchronization plus a read command RD (FIG. 138- (h) and (i)). 在接收各读指令RD后与第5到第12时钟信号CLKB的定时同步地一个接着一个地输出存储在页面缓冲器5050a中的数据作为输出数据Q0-Q7(图138-(j))。 After receiving the respective read commands RD timing of the fifth to the first clock signal CLKB 12 one after another in synchronization with the output data stored in the page buffer 5050a as output data Q0-Q7 (FIG. 138- (j)). 在输入/输出端口P0RT-A,与取得写数据Q7的时钟信号CLKA的特定定时同步地实施写操作WRITEA(图138-(k))。 In the input / output ports P0RT-A, and get specific timing of the write data Q7 clock signal CLKA implemented synchronously writes WRITEA (Figure 138- (k)).

[0659] 然后,在输入/输出端口PORT-A和P0RT-B,与时钟信号CLKA和CLKB的前沿同步地提供有效指令ACT和相互不同的行地址信号RA(图138-(1)和(m))。 [0659] Then, in the input / output ports PORT-A and P0RT-B, to provide effective instruction ACT and mutually different row address signals RA (Fig.138- (1) and (m leading edge of the clock signal CLKA and CLKB of synchronization )). 判优电路5034认定首先将有效指令ACT加到输入/输出端口P0RT-A,并连续实施读操作READA和READB (图138-(η)和(ο))。 Arbitration circuit 5034 ascertains that the active command ACT is supplied to the input / output ports P0RT-A, and continuous read operation READA and READB (Figure 138- (η) and (ο)). 从由读操作READA选出的存储芯5040的所有存储单元读出数据,并将读出的数据存储在页面缓冲器5050a(或5050b)中的一个(图138-(ρ))。 READA selected from the group consisting read all the memory cells of the memory core 5040 read data, and a read-out of data stored in the page buffer 5050a (or 5050b) (FIG. 138- (ρ)). 进一步,从由读操作READB选出的存储芯5040的所有存储单元读出数据,并将读出的数据存储在页面缓冲器5050b (或5050a)中的另一个(图138- (q))。 Another further, selected from the group consisting READB read all the memory cells of the memory core 5040 read data and read data stored in the page buffer 5050b (or 5050a) (FIG. 138- (q)).

[0660] 在输入/输出端口P0RT-A,与时钟信号CLKA的第13和第17定时同步地加上写指令WR(图138-(r)和(s))。 [0660] In the input / output ports P0RT-A, the first 13 and 17 of the timing clock signal CLKA in synchronization plus write command WR (FIG. 138- (r) and (s)). 将与时钟信号CLKA同步地一个接着一个加上的写数据Q0-Q7 写入页面缓冲器5050a中(图138-(t))。 One after another in synchronization with the write data coupled with the clock signal CLKA Q0-Q7 written in the page buffer 5050a (FIG. 138- (t)).

[0661] 类似地,在输入/输出端口P0RT-B,与时钟信号CLKA的第13和第17定时同步地加上写指令WR(图138-(u)和(ν))。 [0661] Similarly, in the input / output port P0RT-B, 13 and 17 of the first timing clock signal CLKA in synchronization plus write command WR (FIG. 138- (u) and (ν)). 将与时钟信号CLKB同步地一个接着一个加上的写数据Q0-Q7写入页面缓冲器5050b中(图138-(w))。 One after another in synchronization with the write data coupled with the clock signal CLKB Q0-Q7 is written in the page buffer 5050b (FIG. 138- (w)).

[0662] 本实施例能够提供与上述的第3实施例相同的优点。 [0662] This embodiment can provide the above-described third embodiment, the same advantages. 进一步,在本实施例中,用作对于存储芯5040的所有存储单元的暂时数据存储的页面缓冲器5050a和5050b位于数据锁存器50¾和存储芯5040之间。 Further, in the present embodiment, as 50¾ between data latches 5040 and the memory core for the temporary storage of data of all memory cells of the memory core 5040 page buffers 5050a and 5050b located. 这使多端口存储器M能够实施页面读操作和页面写操作。 This allows multi-port memory M can be implemented page read and page write operation.

[0663] 当将相同的行地址信号RA加到输入/输出端口PORT-A和P0RT-B时,共用同一个页面缓冲器5050a。 [0663] When the same row address signals RA supplied to the input / output ports PORT-A and P0RT-B, share the same page buffer 5050a. 这防止写入存储单元的数据通过覆盖操作被破坏。 This prevents the data into the memory cell is destroyed by overwriting operation.

[0664] 当将相同的行地址信号RA加到输入/输出端口PORT-A和PORT-B时,响应一个端口只实施读操作。 [0664] When the same row address signals RA supplied to the input / output ports PORT-A and PORT-B, a port only in response to a read operation. 因此,与对于两个端口实施的各读操作的情形比较能够减少操作时的功率消耗。 Thus, with respect to the case of a read operation of each embodiment of the comparison of two ports operating power consumption can be reduced. 使用页面缓冲器5050a和5050b甚至当实施页面操作时也消除了对于控制多端口存储器M,检测多端口存储器M的忙碌状态的控制器的需要。 Use the page buffer 5050a and 5050b operate even when the implementation of the page also eliminates the need for control of the multi-port memory M, multi-port memory M to detect a busy state requires the controller. 因此,控制器等的控制(藉助硬件和软件)变得较容易了。 Therefore, the control (via hardware and software) controllers becomes relatively easy.

[0665] 图139表示根据多端口存储器的第5实施例的多端口存储器的操作和控制本发明的多端口存储器的方法。 [0665] FIG. 139 denotes a multi-port memory according to the operation of the multi-port memory of the fifth embodiment of the multi-port memory and control method of the present invention. 用相同的数字标记与第4实施例相同的部件,并省略对它们的详细描述。 By the same numerals in the fourth embodiment the same components, and a detailed description thereof will be omitted.

[0666] 这个实施例具有用于通常的脉冲串操作的读指令RD和写指令WR两者与用于页面操作的读指令PRD和写指令PWR两者。 [0666] This embodiment has the PWR both for ordinary burst operations and a read command RD and write command WR both for page operations read command PRD and a write command. 多端口存储器M的电路配置基本上与第4实施例相同。 Multi-port memory M of the circuit configuration of the fourth embodiment is substantially the same.

[0667] 在图139中,将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A 和PORT-B (图139-(a)和(b))。 [0667] FIG. 139 in the active commands ACT and the same row address signals RA supplied to the input / output ports PORT-A and PORT-B (FIG. 139- (a) and (b)). 与时钟信号CLKA和CLKB的下一个周期同步地,加上读指令PRD(图139-(c)和⑷),实施页面读操作(图139-(e))。 With the clock signal CLKA and CLKB of the next cycle synchronization, plus a read command PRD (Figure 139- (c) and ⑷), a page read operation (Figure 139- (e)). 页面读操作的定时与图134 相同,并省略对它的详细描述。 Read page 134 of the same timing diagram, and a detailed description thereof is omitted.

[0668] 此后,将有效指令ACT和相同的行地址信号RA加到输入/输出端口PORT-A和PORT-B (图139-(f)和(g))。 [0668] Thereafter, active commands ACT and the same row address signals RA supplied to the input / output ports PORT-A and PORT-B (FIG. 139- (f) and (g)). 与时钟信号CLKA和CLKB的下一个周期同步地,加上读指令RD (图139- (h)和⑴)。 With the clock signal CLKA and CLKB of the next cycle synchronization, plus a read command RD (FIG. 139- (h) and ⑴). 对于各输入/输出端口PORT-A和P0RT-B连续实施读操作READA 和READB(图139-(j)和(k))。 For each input / output ports PORT-A and P0RT-B consecutive read operations READA and READB (Figure 139- (j) and (k)). 即完成通常的读操作(即脉冲串读操作)。 Complete the normal read operation (ie a burst read operation).

[0669] 这个本实施例能够提供与上述的第4实施例相同的优点。 [0669] The present embodiment can provide the same advantages as the above-described fourth embodiment. 因为这个实施例准备了用于页面操作的读指令PRD和PWR以及用于通常操作的读指令RD和WR,所以多端口存储器M响应所加的指令信号不仅能够实施页面操作而且能够实施通常操作。 For this embodiment, prepared to read instructions for operating the PRD and PWR page and read command RD and WR for normal operation, so the multi-port memory M in response to the command signal applied not only to implement paging operations and to implement normal operation.

[0670] 上述实施例已经指向一个将本发明用于多路复用地址信号的地址多路复用型的多端口存储器的例子。 [0670] the above embodiments of the present invention have been pointing to for example an address multiplexed address signal multiplexing-type multi-port memory. 但是本发明不限于这些特定的实施例。 However, the present invention is not limited to these specific examples. 例如,也可以将本发明用于同时接收地址信号的地址非多路复用型的多端口存储器。 For example, the present invention can also be used to address signals received simultaneously address non-multiplexed type multi-port memory.

[0671] 上述实施例已经指向一个将本发明用于具有两个输入/输出端口PORT-A和PORT-B的多端口存储器M的例子。 [0671] the above embodiments of the present invention has been used to refer to a multi-port memory having two input / output ports PORT-A and PORT-B of M examples. 但是本发明不限于这些实施例。 However, the present invention is not limited to these examples. 例如,也可以将本发明用于具有4个输入/输出端口的多端口存储器。 For example, the present invention can also be used for multi-port memory having four input / output ports. 在这个情形中,将所加的有效指令ACT的间隔(按照定时说明)设置得等于或大于存储芯的操作周期的4倍。 In this case, the applied active commands ACT interval (according to timing specifications) is set equal to or greater than 4 times the operation period of the memory core.

[0672] 在上述实施例中,对将本发明用于具有同步DRAM存储芯的多端口存储器的例子进行了描述。 [0672] In the above embodiment, an example of the present invention is applied to a multi-port memory having a synchronous DRAM memory core are described. 但是本发明不限于这种形式的实施例。 However, embodiments of the present invention is not limited to this form. 例如,也可以将本发明用于具有同步SRAM存储芯的多端口存储器。 For example, the present invention may be used for multi-port memory having a synchronous SRAM memory core.

[0673] 进一步,在上述的多端口存储器中,可以将对于存储芯操作的要求作为指令信号输入。 [0673] Further, in the above-described multi-port memory, the memory core may be requirements for operation as an instruction signal input. 将这样的指令信号与时钟信号同步地加到一个输入/输出端口的指令端子。 Such a command signal in synchronization with the clock signal applied to an input command / output port terminal. 可以将该指令信号分成一个用于激活存储块的一个特定存储区域的有效指令和一个指示在这个存储区域中或者实施读操作或者实施写操作的动作指令,并且可以连续地加上这些指令。 The command signal may be divided into an active command for activating a specific memory area and a memory block for indicating the memory area in a read operation or a write operation or operation instructions, and these instructions may be continuously added. 由于同样的原因,也可以在时分基础上一个接着一个地加上地址信号。 By the same token, you can add one after the address signal in a time division basis. 通过在加上有效指令后的预定时钟周期上加上动作指令将读操作周期和写操作周期固定在琠w的周期上。 By adding action instruction on a predetermined clock cycles plus effective instruction will read cycle and the write cycle is fixed at a constant cycle.

[0674] 如果存储块的存储单元由DRAM单元构成则需要刷新操作。 [0674] If the memory cell block units is required by the DRAM refresh operation. 对于由加在任何一个输入/输出端口上的地址信号指示的刷新地址实施刷新操作。 For the refresh address from the address signals applied on any one of the input / output ports indicated refresh operation. 这个配置能够使在多端口存储器中的控制电路的尺寸减到最小,从而能够减小芯片尺寸。 This configuration enables the multi-port memory to minimize the size of the control circuit, it is possible to reduce the chip size.

[0675] 在读操作和写操作后自动地实施将与存储单元连接的位线复位到预定电位的预充电操作。 [0675] carried out automatically reset the memory cell connected to the bit line to a predetermined potential in the precharge operation after the read and write operations. 这使从开始各操作的预定时间周期内完成读操作和写操作成为可能。 This allows the read operation from the beginning of the predetermined time period within each operation and the write operation is possible. 即,能够将读周期时间和写周期时间固定为琠w的。 That is, the read cycle time and the write cycle time is fixed at a constant.

[0676] 而且,可以为每个输入/输出端口提供忙碌端子以便输出忙碌信号。 [0676] Moreover, a busy terminal may be provided so as to output a busy signal for each input / output port. 当加到一个输入/输出端口的地址信号与加到另一个输入/输出端口的地址信号相同时和当对于后一个输入/输出端口执行存储操作时,输出忙碌信号。 When applied to an address signal input / output ports and applied to the other input / output port address signals are the same and when for an input / output port when performing storage operation, the output busy signal. 用这种配置,与多端口存储器连接的控制器很容易知道还没有实施所要求的操作。 With this arrangement, the multi-port memory controller and connected easily know has not yet implemented the required operations.

[0677] 进一步,本发明不限于这些实施例,而且可以作出不同的变化和修改而没有偏离本发明的范围。 [0677] Further, the present invention is not limited to these embodiments, but various changes may be made and modifications without departing from the scope of the invention.

[0678] 例如,我们已经参考为了同步只用一个前沿或一个后沿的配置描述了本发明的第1到第5方面。 [0678] For example, we have a reference for synchronization with only one cutting edge or a configured describe the first to fifth aspect of the present invention along. 然而对于那些熟练的技术人员来说显然能够容易地改变上述任何一个配置, 使它与为了同步用前沿和后沿两者的DDR(双数据速率)操作匹配。 But apparently it can easily change any of the above configuration to those skilled in the art is, and in order to synchronize it with both leading and trailing edges of DDR (double data rate) operations to match. 我们有意使这样一个明显的改变处在本发明的范围内。 We intend to make such a significant change in the scope of the invention.

[0679] 本申请基于向日本专利局提出的日本优先权专利申请2000年12月20日递交的No. 2000-387891,2001 年2 月9 日递交的No. 2001-034361,2001 年2 月14 日递交的No. 2000-037547,2000 年12 月27 日递交的No. 2000-398893 和2000 年12 月27 日递交的No. 2000-399052,这里我们将这些专利申请的全部内容作为参考。 [0679] The present application to the Japanese Patent Office Japanese Priority Patent Application December 20, 2000 filed No. 2000-387891,2001 on February 9 No. filed on February 14 based 2001-034361,2001 All contents No. 2000-398893 and December 27, 2000 filed No. No. 2000-037547,2000 filed on December 27 filed 2000-399052, here we refer to these patent applications are incorporated by reference.

專利引用
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法律事件
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2009年7月8日C06Publication
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2012年5月23日C14Granted
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