CN101477829B - Multiport memory based on dynamic random access memory core - Google Patents

Abstract

The present invention provides a multi-port memory based on a plurality of dynamic random access memory cores. A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Description

Multiport memory based on dynamic random access memory core

It is 01139358.0 that the application of this division is based on application number, and the applying date is November 26 calendar year 2001, and denomination of invention is divided an application for the one Chinese patent application of " based on the multiport memory of dynamic random access memory core ".Say that more specifically it is 200510083508.3 that the application of this division is based on application number, the applying date is November 26 calendar year 2001, denomination of invention for " based on the multiport memory of dynamic random access memory core " divide an application divide an application once more.

Technical field

The present invention relates generally to semiconductor storage unit, particularly relate to the semiconductor memory that is equipped with a plurality of ports.

Background technology

Multiport memory, they are the semiconductor memories that are equipped with a plurality of ports, can be divided into different types.When hereinafter using a technical term " multiport memory ", it refers to the storer with a plurality of ports, and this multiport memory allows from any one port access to a common memory array independently.Such storer can have an A port and a B port, and allows for common memory array from carrying out read/write operation independently with the CPU of A port link with from the CPU with the B port link.

A multiport memory is equipped with an arbiter that is called arbiter.Arbiter is confirmed the right of priority that requires from each access that a plurality of ports receive, the control circuit of memory array according to the right of priority of confirming one by one carry out accessing operation.For example, an access requires more early to arrive a port, will give this access high more right of priority.

In this situation, because randomly from a plurality of interface access memory array, thus after having carried out the accessing operation that reads or writes, need memory array be resetted, thus the assurance memory array is got ready for access next time.Promptly; Make a word line remain on a state of selecting if respond a access from a given port; With as in the row accessing operation that in DRAM, uses such continuous earthquake move each column address so that read continuous data, then will wait for from the access of another port in this operating period always.Therefore, after each read or write, need memory array be resetted.

Routinely, typically with the memory array of a SRAM as a multiport memory.This is because a SRAM allows high random access, and can carry out the non-destructive read operation.

In a multiport memory with two ports, for example, SRAM storage unit have two groups of word lines and bit line right.Port with one group of word line and bit line to implementing read/write operation, another port with another group word line and a bit line to implementing read/write operation.In this mode, can implement read/write operation independently from two different ports.Yet,, carry out the right of priority of write operation so give a port, and give a BUSY of another port (having much to do) signal because when two port attempts write same storage unit with data at one time, can not carry out two write operations simultaneously.This is called a BUSY state.

When system of exploitation makes it that the performance of improvement arranged, can also increase by this system handles data volume.As a result, a multiport memory needs very big capacity.Yet SRAM type multiport memory has a shortcoming, and promptly the size of storage unit is big.

In order to eliminate this shortcoming, it is understandable in a multiport memory, adopting a DRAM array.For obtain than multi-port SRAM high the current densities that Duo very much, a DRAM storage unit that need be used for multiport memory is connected with a bit lines with a word line with the mode identical with typical DRAM unit.If process storage block with the DRAM element in such a way, if then a port is carried out read or write to a given storage block, another port just can not this storage block of access.This be because in a DRAM storage unit only so that a non-destructive read operation to be arranged.That is, when read message, can not be chosen in the same storage block another word line up to this information in storage unit be exaggerated and recover with a word line and a bit lines by pre-charge till.

Because this reason, if one of given port access by the storage block of another port access, then will detect a BUSY state.Have only when a plurality of ports send same storage unit simultaneously and write when requiring, in SRAM type multiport memory, just the BUSY state can occur.On the other hand, when the access of simultaneously same storage unit being sent any kind when a plurality of ports requires, in DRAM type multiport memory the BUSY state can appear.So the probability that the BUSY state in DRAM type storer, occurs is very greater than the probability that the BUSY state in SRAM type storer, occurs.Further, in case be in the BUSY state, DRAM type multiport memory will receive operation or because the puzzlement that the stand-by period processing becomes very slow this problem that can not hope.

Yet different with SRAM type multiport memory, DRAM type multiport memory needs the refresh operation that one-period ground carries out so that keep canned data, thereby must take certain measure to guarantee suitable refresh timing.

Therefore, the purpose of this invention is to provide the DRAM type multiport memory that to eliminate each special relevant problem with DRAM.

Summary of the invention

A general purpose of the present invention provides the semiconductor storage unit (multiport memory) that can eliminate one or more problems that restriction and shortcoming by prior art cause basically.

We will propose characteristics of the present invention and advantage in following description, and a part of characteristics and advantage will become very clear from describing with appended each figure, perhaps can understand these characteristics and advantage through putting into practice the present invention according to the guidance that provides in the description.We will be through with making the sort of complete that common those skilled in the art can embodiment of the present invention; Clear, each purpose of the present invention and each its its feature and the advantage that can realized and obtain by a multiport memory specifically noted in brief and accurate term in instructions.

For realize these with other advantage and according to the object of the invention; As here particularly and widely; The present invention provides such semiconductor storage unit, and this device comprises that the quantity that each port all accepts to instruct is a plurality of outside ports and an internal circuit of during the minimum interval of each instruction that is input to an outside port, carrying out N accessing operation at least of N.

Further, an arbiter is provided, the instruction execution order when this arbiter confirms that internal circuit is carried out a plurality of instruction that is input to N outside port.

Among the present invention who describes in the above, when instruction gets into N port, all corresponding with N port N instruct minimum instruction at any given port in the cycle by one follow one execution.Therefore, one appears in the device outside and in minimum instruction with the relevant access instruction of any given port and to be performed in the cycle.In this situation, have only a BUSY signal just can take place when from the same address of a plurality of port accesses.So just can obtain the same low BUSY state probability of occurrence of BUSY state probability of occurrence with SRAM type multiport memory.

And in semiconductor storage unit of the present invention, internal circuit comprises a memory cell array, and the refresh circuit of the timing that this array is refreshed by each storage unit of many dynamic type storage unit and one definition is formed.In first pattern, respond a refreshing instruction that is input to N at least one port in the outside port and refresh each storage unit, in second pattern, in definite each storage unit of periodic refreshing of refresh circuit.

Have first operator scheme like above-described the present invention, wherein respond a instruction and carry out refresh operation and second operator scheme, wherein respond internal refresh circuitry and carry out refresh operation from an outside port.Because this configuration; Allow an outside port as a port that is used to refresh management operate; So that receive refreshing instruction in each constant time interval, if perhaps this port that is used to refresh management is a deactivation status, then internal refresh circuitry is implemented refresh operation.This makes according to system configuration becomes possibility with a kind of flexible way management refresh operation.

Description of drawings

Fig. 1 is the figure that is used to explain the principle of the invention (the 1st aspect);

Fig. 2 is the figure of expression refresh operation of enforcement when having only a port being used.

Fig. 3 A is at 2 ports to 3C, is used to explain the figure of the principle of the invention in the situation of 3 ports and N port;

Fig. 4 is the block scheme of expression the 1st embodiment of the multiport memory of (the 1st aspect) according to the present invention;

Fig. 5 imports relevant circuit block diagram with the instruction to an arbiter;

Fig. 6 A and 6B are the circuit diagrams of a configuration of expression arbiter;

Fig. 7 is the timing diagram of expression arbiter operation;

Fig. 8 imports relevant circuit block diagram with the address to a DRAM core;

Fig. 9 is and the relevant circuit block diagram of data output;

Figure 10 is the circuit diagram of the configuration of a transmission signals generation circuit of expression.

Figure 11 is and the relevant circuit block diagram of data input;

Figure 12 is the timing diagram of expression operation of enforcement when input Read (reading) instructs continuously;

Figure 13 is the timing diagram of expression operation of enforcement when input Write (writing) instructs continuously;

Figure 14 is the timing diagram of expression when A port and B port both operate on the maximum clock frequency;

Figure 15 is the timing diagram of expression when A port and B port both operate on the maximum clock frequency;

Figure 16 is expression when the timing diagram of the operation of instruction when Read instruction changes to Write and instructs;

Figure 17 is that expression is when instructing the figure that when " Read " changes to " Write ", imports the timing of a refreshing instruction;

Figure 18 is the timing diagram of the operation when making a port deactivation, implemented of expression;

Figure 19 is the timing diagram of the operation when making two port deactivations, implemented of expression;

Figure 20 A and 20B are the timing diagrams of expression DRAM core operation;

Figure 21 is the timing diagram of the dual-rate operation when only making a port operation, implemented of expression;

Figure 22 is the timing diagram that expression is operated when dual-rate when making clock frequency twice height make the message transmission rate twice;

Figure 23 is the figure that is used to explain the present invention's (the 1st aspect) the 2nd embodiment;

Figure 24 is the block scheme of expression the 2nd embodiment of the multiport memory of (the 1st aspect) according to the present invention;

Figure 25 A and 25B are the timing diagrams that is used to explain continuous mode;

Figure 26 is the timing diagram of the operation when the Write for the Read of A port instruction and B port instructs generation BUSY signal, implemented of expression;

Figure 27 is the timing diagram of the operation when the Write for the Read of A port instruction and B port instructs generation BUSY signal, implemented of expression;

Figure 28 is the timing diagram of the operation when the Write for the Write of A port instruction and B port instructs generation BUSY signal, implemented of expression;

Figure 29 is the timing diagram of the operation when the Write for the Write of A port instruction and B port instructs generation BUSY signal, implemented of expression;

Figure 30 is illustrated in one can handle the timing diagram of operating in the configuration of the interrupt instruction of being sent by controller;

Figure 31 is an address comparator of expression multiport memory of the 2nd embodiment of (the 1st aspect) according to the present invention, the figure of the configuration of a BUSY I/O system and an interrupt system;

Figure 32 is the timing diagram of expression main device operation;

Figure 33 is the timing diagram of expression from device operation;

Figure 34 is the timing diagram that main device that expression is implemented when the write address of two ports is identical is operated;

Figure 35 is the timing diagram from device operation of expression enforcement when the write address of two ports is identical;

Figure 36 is expression when the write address of two ports matees each other main device is operated when making controller send interrupt instruction timing diagram;

Figure 37 is expression when the write address of two ports matees each other when making controller send interrupt instruction from the timing diagram of device operation;

Figure 38 is the figure that is used to explain the present invention's (the 2nd aspect) principle, the situation of expression when for two ports enforcement read operations;

Figure 39 is the figure that is used to explain the present invention's (the 2nd aspect) principle, and the indicating impulse string length is 4 example;

Figure 40 is the figure that is illustrated in the relation between a minimum external command cycle and each built-in function cycle in the sight situation of 2 and 3 ports;

Figure 41 is the figure that is illustrated in the relation between a minimum external command cycle and each built-in function cycle in the situation of n port;

Figure 42 is the figure of expression configuration of the multiport memory of an embodiment of (the 2nd aspect) according to the present invention;

Figure 43 A is the figure of expression configuration of the multiport memory of the embodiment of (the 2nd aspect) according to the present invention to 43C;

Figure 44 is the configuration of each relevant device is handled in expression according to the 1st embodiment and instruction figure;

Figure 45 is the configuration of each relevant device is handled in expression according to the 1st embodiment and instruction figure;

Figure 46 is the embodiment of arbiter;

Figure 47 is the figure of expression according to the configuration of the 1st embodiment part relevant with address process;

Figure 48 is the figure of expression according to the configuration of the 1st embodiment part relevant with data output;

Figure 49 is the figure of the transmission signals generation circuit of expression Figure 48.

Figure 50 is the figure of expression according to the configuration of the 1st embodiment part relevant with the data input;

Figure 51 is the figure of the operation when Read being instructed adjoining land import two ports, implemented of expression;

Figure 52 is the figure of the operation when Read being instructed adjoining land import two ports, implemented of expression;

Figure 53 representes the example when adjoining land input Write instruction;

Figure 54 representes to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both;

Figure 55 representes to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both;

Figure 56 to be expression carry out Write operation of enforcement when operating when A port and B port both operate on the maximum clock frequency figure;

Figure 57 representes to be operating in highest frequency when two ports, and makes the time diagram that changes to the operation of implementing when Read instructs from the Write instruction with the inner refreshing instruction that produces;

Figure 58 representes to be operating in highest frequency when two ports, and makes the time diagram that changes to the operation of implementing when reading instruction from write command with the inner refreshing instruction that produces;

Figure 59 A and 59B are the timing diagrams of DRAM core operation;

Figure 60 is the circuit diagram of the configuration of expression refresh circuit;

Figure 61 is the figure of the circuit arrangement of expression the 2nd arbiter;

Figure 62 representes that instruction that two ports stand Write → Read changes and during the REF transmission is forbidden, take place the situation of a refresh timer incident;

Figure 63 representes that instruction that two ports stand Write → Read changes and during the REF transmission is forbidden, take place the situation of a refresh timer incident;

Figure 64 representes that two ports stand the instruction change of Write → Read as top situation, but the situation of a refresh timer takes place before during the REF transmission is forbidden;

Figure 65 representes that two ports stand the instruction change of Write → Read as top situation, but the situation of a refresh timer takes place before during the REF transmission is forbidden;

Figure 66 representes the instruction transition of having only the A port to stand Write → Read and the situation that a refresh timer incident takes place during the REF transmission is forbidden;

Figure 67 representes the instruction transition of having only the A port to stand Write → Read and the situation that a refresh timer incident takes place during the REF transmission is forbidden;

Figure 68 is illustrated in the timing diagram of the situation that two ports write continuously;

Figure 69 is illustrated in the timing diagram of the situation that two ports write continuously;

Figure 70 representes to operate with the 1st embodiment shown in Figure 57 and Figure 58 the timing diagram of corresponding the 2nd embodiment operation;

Figure 71 representes to operate with the 1st embodiment shown in Figure 57 and Figure 58 the timing diagram of corresponding the 2nd embodiment operation;

Figure 72 representes to operate with the 1st embodiment shown in Figure 56 the timing diagram of corresponding the 2nd embodiment operation;

Figure 73 is the figure that is used to explain the present invention's (the 3rd aspect) principle, and the situation of read operations is implemented in expression for two ports;

Figure 74 is the figure that is used to explain the present invention's (the 3rd aspect) principle, and the indicating impulse string length is 4 example;

Figure 75 is illustrated in the figure that between a minimum external command cycle and each built-in function cycle, concerns in 2 and 3 port situations;

Figure 76 is illustrated in the figure that between a minimum external command cycle and each built-in function cycle, concerns in N the port situation;

Figure 77 is the figure of expression configuration of the multiport memory of an embodiment of (the 3rd aspect) according to the present invention;

Figure 78 A is the figure of expression configuration of the multiport memory of the foregoing description of (the 3rd aspect) according to the present invention to 78C;

Figure 79 is the configuration of each relevant device is handled in expression according to the 1st embodiment and instruction figure;

Figure 80 is the configuration of each relevant device is handled in expression according to the 1st embodiment and instruction figure;

Figure 81 is the embodiment of arbiter;

Figure 82 is the figure of the configuration of presentation directives's register;

Figure 83 is the figure of the configuration of presentation directives's register;

Figure 84 A and Figure 84 B represent the operation of register controlled circuit;

Figure 85 is the figure of presentation directives's register manipulation;

Figure 86 is the figure of presentation directives's register manipulation;

Figure 87 is the figure of expression according to the configuration of the 1st embodiment part relevant with address process;

Figure 88 is the figure of expression according to the configuration of the 1st embodiment part relevant with data output;

Figure 89 is the figure of the transmission signals generation circuit of expression Figure 88;

Figure 90 is the figure of expression according to the configuration of the embodiment part relevant with the data input;

Figure 91 is the figure of expression according to the configuration of the embodiment part relevant with the data input;

Figure 92 representes the operation when Read being instructed two ports of adjoining land input, implemented;

Figure 93 representes the operation when Read being instructed two ports of adjoining land input, implemented;

Figure 94 representes the example when adjoining land being imported the Write instruction;

Figure 95 representes to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both;

Figure 96 representes to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both;

Figure 97 to be expression carry out Write operation of enforcement when operating when A port and B port operate on the maximum clock frequency figure;

Figure 98 be expression when two port operations all at highest frequency, and make the time diagram of the operation of enforcement when the Write instruction changes to the Read instruction with the inner refreshing instruction that produces;

Figure 99 representes to be operating in highest frequency when two ports, and makes the time diagram that changes to the operation of implementing when Read instructs from the Write instruction with the inner refreshing instruction that produces;

Figure 100 A and 100B are the timing diagrams of DRAM core operation;

Figure 101 is the block scheme of expression embodiment of the multiport memory of (the 4th aspect) according to the present invention;

Figure 102 is the timing diagram of expression example of the multiport memory operation of (the 4th aspect) according to the present invention;

Figure 103 is the timing diagram of expression example of the multiport memory operation of (the 4th aspect) according to the present invention;

Figure 104 is the timing diagram of expression another example of the multiport memory operation of (the 4th aspect) according to the present invention;

Figure 105 is the block scheme of presentation directives's code translator register;

Figure 106 is the block scheme of the arbiter of the embodiment of (the 4th aspect) according to the present invention;

Figure 107 is the timing diagram of expression arbiter operation;

Figure 108 is the block scheme of address buffer/register and address modification circuit;

Figure 109 is the block scheme of storage block;

Figure 110 A and 110B are the timing diagrams of expression storage block operation;

Figure 111 representes the 1st embodiment of the multiport memory of (the 5th aspect) according to the present invention;

Figure 112 representes the I/O circuit 5010 of multiport memory and the details of storage block MB;

The details of Figure 113 presentation address comparator circuit;

Figure 114 representes the details of comparer;

Figure 115 representes the comparator operations of enforcement when the row address signal RA that is added to input/output end port PORT-A and PORT-B matees each other;

Figure 116 representes the operation of comparer when row address signal RA does not match between input/output end port PORT-A and PORT-B;

Figure 117 representes the operation when the row address signal RA that is added to input/output end port PORT-A and PORT-B comparer when clock signal clk A and clock signal clk B have coupling under the condition of different cycles;

Figure 118 representes to offer the arbitration control circuit of the arbiter shown in Figure 112;

Figure 119 representes the operation of the arbitration control circuit of enforcement when being added to the row address signal coupling of input/output end port PORT-A and PORT-B;

Figure 120 representes the operation of enforcement when the row address signal RA that is added to input/output end port PORT-A and PORT-B matees each other;

Figure 121 representes when the cycle of clock signal CLKA and CLKB identical, the operation that the phase place of the leading clock signal clk B of the phase place of clock signal clk A is implemented during more than half period;

Figure 122 representes almost to be added to simultaneously the mutual asynchronous operation of row address signal RA of input/output end port PORT-A and PORT-B;

The method that Figure 123 representes the 2nd embodiment of multiport memory and multiport memory is controlled in (the 5th aspect) according to the present invention;

Figure 124 representes the method for the 3rd embodiment with control (the 5th aspect) control multiport memory according to the present invention of multiport memory;

Figure 125 represent to arbitrate details of control circuit;

Figure 126 representes the operation of the arbitration control circuit of enforcement when the row address signal that is added to input/output end port PORT-A and PORT-B matees each other;

Figure 127 representes when input/output end port PORT-A and PORT-B receive effective instruction ACT with identical row address signal RA, to implement the method for read operation;

Figure 128 representes when effective instruction ACT is added to input/output end port PORT-A and PORT-B with mutual different row address signal RA, to implement the method for read operation;

Figure 129 representes when input/output end port PORT-A and PORT-B reception effective instruction ACT and same lines address signal RA, to implement the method for write operation;

Figure 130 representes to implement write operation and read operation continuously for input/output end port PORT-A, the situation of the write operation of the row address signal RA identical with the row address signal RA of the read operation of the row address signal RA identical with the row address signal RA of the write operation of input/output end port PORT-A of write operation one after the other implement to point to to(for) input/output end port PORT-B and sensing and input/output end port PORT-A;

Figure 131 representes to implement write operation and read operation continuously for input/output end port PORT-A, the situation of the write operation of the row address signal RA identical with the row address signal RA of the read operation of the row address signal RA identical with the row address signal RA of the write operation of input/output end port PORT-A of read operation one after the other implement to point to to(for) input/output end port PORT-B and sensing and input/output end port PORT-A;

Figure 132 is illustrated in clock signal clk A and has the operation of when the row address signal that is added to input/output end port PORT-A and PORT-B matees each other, implementing in the situation of different clock period with CLKB;

The method that Figure 133 representes the 4th embodiment of multiport memory and multiport memory is controlled in (the 5th aspect) according to the present invention;

Figure 134 representes when input/output end port PORT-A and PORT-B receive effective instruction ACT with identical row address signal RA, to implement the method for read operation;

Figure 135 representes when effective instruction ACT is added to input/output end port PORT-A and PORT-B with different row address signal RA, to implement the method for read operation;

Figure 136 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA, implements write operation, then adds effective instruction ACT and different row address signal RA, causes implementing the situation of write operation;

Figure 137 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA; Implement write operation; Then add effective instruction ACT and identical row address signal RA, cause implementing the situation of write operation in input/output end port PORT-A enforcement read operation with at input/output end port PORT-B;

Figure 138 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA; Implement write operation and read operation; Then add effective instruction ACT and different row address signal RA, cause implementing the situation of write operation and read operation;

Figure 139 representes the method according to the operation of the multiport memory of the 5th embodiment of multiport memory and control the present invention's (the 5th aspect) multiport memory.

Embodiment

Below, we describe various embodiments of the present invention with reference to appended each figure.

[the present invention the 1st aspect]

We at first describe the principle of the present invention (the 1st aspect).

Fig. 1 is the figure that is used to explain the present invention's (the 1st aspect) principle.Though Fig. 1 representes to be used for to explain the figure of the principle of 2 port situations, even if provide plural port (N port) also can obtain identical operations.

The time span that is equivalent to two cycles of internal circuit (DRAM core) operation is defined as the one-period in external command cycle.That is, the core operating cycle is the twice of the speed in external command cycle.More early arrive with regard to this ordered pair entering A port of processing instruction more early and the instruction of B port with instruction at dual-rate by internal storage and to handle.Then output data is sent to each port.That is, implement to comprise word line of selection in the operating cycle at a core, amplification data is selected an alignment, and the read and write operation is dashed the sequence of operations that electricity is operated in advance, thereby relevant storage block is accomplished an accessing operation.

For example, at the timing C1 in the external command cycle relevant, get into a Read instruction at the A port with the A port of Fig. 1.Further, at the timing C1 ' in an external command cycle relevant, get into a Read instruction at the B port with the B port.Because the timing of the Read of A port instruction a little earlier, so this Read instruction is performed reading instruction of entering B port before.Here, an external command cycle is corresponding to 4 clock cycles.As shown in Figure 1, in 2 clock cycles corresponding, carry out and accomplish each Read instruction with 1 core operating cycle.Therefore; Response gets into the Read instruction of A port and B port in the time interval of 4 clock cycles that are equivalent to an external command cycle; Can implement read operation, even and if can not produce a BUSY state and all point to same storage block from the read access of A port with from the read access of B port.This is through carrying out in 2 clock cycles and accomplishing each access and realize.

In this mode, even if a plurality of port same storage block of access simultaneously, because internal storage can carry out in succession and continuous processing with the speed of twice, so also can not produce a BUSY state.

And, when providing a refreshing instruction, can implement refresh operation and can not influence access from device outside (for example at the A port) when as shown in Figure 1 from another port (being the B port in this example) at this device inside.In this situation, can select one (being the A port in Fig. 1 example) conduct in a plurality of ports to refresh the port of management, always get into refreshing instruction from this port.

And data output can be fetched from a plurality of column addresss sense data and through parallel data being transformed into when the output form of the train of impulses of serial data output data concurrently.This has increased message transmission rate and has made the continuous Read of response instruct continuously, and output data becomes possibility.

Fig. 2 is the figure of expression refresh operation of enforcement when having only a port being used.

As shown in Figure 2, when 2 ports are provided, for example, when A port and B port, need not let 2 ports all operate.In device, provide a refresh timer to make the inner refreshing instruction that produces become possibility.

As shown in Figure 2, for example, when a port (for example, the B port) can innerly not produce refreshing instruction in when operation, thereby carry out refreshing instruction and can not influence access at the A port.

We consider an example now, and wherein when refreshing management, controller A controls the A port, controller B control B port.In this situation, if having one as above-mentioned internal refresh function, then the B port can stop fully when only with the A port.This just can reduce because the power consumption that the change of following system operation causes.

Fig. 3 A is when 2 ports to 3C, is used to explain the figure of the principle of the invention when 3 ports and N port.

As described above, the present invention also can be applicable to 3 or the multiport memory of multiport more.Fig. 3 A is illustrated in the operation of 1 port in the situation that 2 ports are provided as depicted in figs. 1 and 2.Fig. 3 B is illustrated in the operation of 1 port in the situation of 3 ports, and Fig. 3 C representes the situation of N port.Shown in Fig. 3 C, can be suitably with the length setting in the built-in function cycle external command cycle in the situation of 1/N and N port store the same long.

Below, we describe semiconductor storage unit according to an embodiment of the invention.

Fig. 4 is the block scheme of expression according to the 1st embodiment of multiport memory of the present invention.In this example, provide to have 2 ports, i.e. A port and B configuring ports.

The multiport memory 10 of Fig. 4 comprises A port one 1, B port one 2, self-refresh circuit 13, DRAM core 14; Arbiter 15, refreshing instruction register 16, order register A 17, order register B 18; Address update register 19, address register A 20, address register B 21, write data register A 22; Write data register B 23, transmission gate A 24 and transmission gate B 25.

A port one 1 comprises mould register 31, CLK impact damper 32, data I/O circuit 33, address buffer 34 and command decoder 35.Further, B port one 2 comprises mould register 41, CLK impact damper 42, data I/O circuit 43, address buffer 44 and command decoder 45.At A port one 1 and B port one 2, synchronously be established to the access of external bus independently with clock signal clk A and CLKB respectively and from the access of external bus.Mould register 31 and 41 can storing therein for mode initialization such as the data stand-by period and the burst length of each port.In this embodiment, A port one 1 has mould register separately with B port one 2 boths, makes each port can both carry out mode initialization.Yet, can the mould register only be arranged in the port, for example, making can be by this setting of ports is realized for 2 setting of ports.

Self-refresh circuit 13 comprises refresh timer 46 and refreshing instruction generator 47.Self-refresh circuit 13 produces refreshing instruction in device, receive signal CKEA1 and CKEB1 from A port one 1 and B port one 2 respectively.Signal CKEA1 and CKEB1 cushion with CLK impact damper 32 and the 42 couples of external signal CKEA and CKEB respectively and obtain.Suspend the clock buffer of each port and make each port go base to live with external signal CKEA and CKEB.If make one in A port one 1 and the B port one 2 to get into deactivation status, then self-refresh circuit 13 its operations of beginning.In mould register 31 and 41, be provided with, make a port be responsible for refreshing in the situation of management, when be responsible for refreshing management port can activate self-refresh circuit 13 when becoming inoperation.

Further, the DRAM core comprises memory array 51, code translator 52, control circuit 53, WriteAmp (write amplifier) 54 and sense buffer 55.The data that memory array 51 storing therein are write and read, and comprise the DRAM storage unit, cell gate transistor, word line, bit line, sensor amplifier, alignment, row door etc.Decipher 52 pairs of addresses by access of code translator.The operation of control circuit 53 control DRAM cores 14.The data that WriteAmp 54 amplifies write store array 51.Sense buffer 55 amplifies the data of reading from memory array 51.

The input that to arrive A port one 1 is transferred to address register A 20, refreshing instruction register 16, order register A 17 and write data register A 22.Further, the input that will arrive B port one 2 is added to address register B 21, refreshing instruction register 16, order register B 18 and write data register B 23.

Arbiter (arbiter) 15 is confirmed the order that instruction gets into, and gives which instruction so that confirm the right of priority that will be used between A port one 1 and B port one 2, handling.With the order of confirming, arbiter 15 will instruct, and address and data (in the situation of write operation) are given DRAM core 14 from each register transfer.DRAM core 14 is operated according to the data that receive.In the situation of Read instruction, will give the port of input command adapted thereto from the data transmission that DRAM core 14 is read, then these data are transformed into serial data from parallel data, follow clock synchronization ground output with this port.

Fig. 5 is the block scheme of the circuit relevant with the instruction that is input to arbiter 15;

Command decoder 35 comprises input buffer 61, command decoder 62 and (n-1) clock delay circuit 63.And command decoder 45 comprises input buffer 71, command decoder 72 and (n-1) clock delay circuit 73.Order register A 17 comprises read instruction register 17-1 and write command register 17-2.And order register B 18 comprises read instruction register 18-1 and write command register 18-2.

In the situation of Read instruction, the instruction that will be input to input buffer 61 or 71 through command decoder 62 or 72 respectively is transferred to read instruction register 17-1 or 18-1, and has no fixed cycle operator.In the situation of Write instruction; Make instruction delay (n-1) clock of entering by (n-1) clock delay circuit 63 or 73, the timing when n the data (being last data) of a series of pulse series datas that will be write of input the time is transferred to write command register 17-2 or 18-2 with it then.

In the situation of refreshing instruction, will be from A port one 1, the refreshing instruction that B port one 2 or refreshing instruction generator 47 provide is transferred to refreshing instruction register 16.Because do not occur refreshing instruction so frequently, so a plurality of refreshing instruction registers need be provided.Further, provide the self-refresh that is input to refreshing instruction generator 47 that information is set from mould register 31 and 41, this information points out that in each port which be responsible for refreshing management.

Arbiter 15 detects the order that instruction is transferred to each order register, and will instruct one to follow a ground and be transferred to DRAM control circuit 53 with this order.

When receiving instruction (or when end of carrying out near instruction), DRAM control circuit 53 generation RESET1 signals let arbiter 15 get ready for next instruction.In the specific configuration of this embodiment, DRAM control circuit 53 receives next instruction when the RESET1 signal ended.

When receiving the RESET1 signal, arbiter 15 is reset signal ResetRA, ResetWA, and ResetRB, one among ResetWB and the ResetREF is added to order register A 17, in order register B 18 and the refreshing instruction register 16 corresponding one.Through this operation, make storing therein be transferred to the instruction of DRAM core 14 order register reset, in this order register, prepare to receive next instruction.

Fig. 6 A and 6B are the circuit diagrams of the configuration of expression arbiter 15.

Shown in Fig. 6 A, arbiter 15 comprises comparer 80-1 to 80-10, and AND (" with ") circuit 81-1 is to 81-5; AND circuit 82-1 is to 82-5, and AND circuit 83-1 is to 83-5, and delay circuit 84-1 is to 84-5; Phase inverter 85 to 87, NAND (NAND) circuit 88 and phase inverter 89 and 90.Each all has identical circuit arrangement to comparer 80-1 to 80-10, shown in Fig. 6 B, comprise NAND circuit 91 and 92 with phase inverter 93 and 94.

Will be from read instruction signal RA2 and the write command signal WA2 of order register A 17, from read instruction signal RB2 and the write command signal WB2 and be added to arbiter 15 of order register B 18 from the refreshing instruction REF2 of refreshing instruction register 16.For by 2 whole 10 combinations that obtain selecting in 5 command signals, which the timing that 10 comparer 80-1 arrive according to instruction to 80-10 confirms is instructed more Zao than another.

Each comparer is the timing of 2 instructions relatively, and one during each is exported is arranged on HIGH (height), and it is corresponding with the input that before other input, has received HIGH.For example, which morning is comparer 80-1 each in the 80-4 confirm in corresponding in other the instruction of signal RA2 or 4 that reads instruction from A port one 1 one.Signal RA2 is more Zao than in 4 other instructions any one if read instruction, and then will be arranged on HIGH from the signal RA31 that reads instruction of AND circuit 81-1 output.When the RESET1 signal is LOW (low), this signal RA31 that reads instruction is added to DRAM core 14 as the signal RA3 that reads instruction from arbiter 15.

When DRAM core 14 received instruction, it was the RESET1 signal of HIGH that DRAM core 14 produces.By phase inverter 85 to 87, NAND circuit 88 becomes pulse signal with phase inverter 89 with this RESET1 signal transformation, and is added to AND circuit 83-1 to 83-5.When Read command signal RA31 is HIGH, for example, produce the signal that the order register that wherein has the instruction that receives is resetted through delay circuit 84-1.

Fig. 7 is the timing diagram of the operation of expression arbiter 15.

Signal indication with name of enumerating among Fig. 7 is in each position of Fig. 6 A.Fig. 7 is that expression is when the operation that the Read instruction is added to A port one 1 and B port one 2 last time arbiter 15.As shown in Figure 7, select to instruct RA2 as instruction, thereby produce RA31 with right of priority with A port one 1 corresponding Read, make the core circuit implement read operation READ-A.Respond consequent reset signal RESET1, the signal RA2 that reads instruction is resetted.Accordingly, select to instruct RB2 with B port one 2 corresponding Read, thus generation RB31.When reset signal RESET1 became LOW, the signal RB3 that will read instruction was added to the core circuit, thereby carried out read operation READ-B.

Fig. 8 is the circuit block diagram relevant with the address that is input to a DRAM core 14.

The address buffer 34 of A port one 1 comprises input buffer 34-1, transmission gate 34-2 and OR (" or ") circuit 34-3.Adding has the pulse signal of the pulse corresponding with the forward position of the signal RA1 that reads instruction that exports from command decoder shown in Figure 5 62 as the RA1P that is added to the input end of OR circuit 34-3.Further, add the WA1P that the pulse signal conduct with pulse corresponding with the forward position of the write command signal WA1 that exports from command decoder shown in Figure 5 62 is added to another input end of OR circuit 34-3.Hereinafter, the signal representative that has a letter " p " at its not end of signal name has the signal of the pulse that produces from the forward position of the signal of the signal name of correspondence.

The address buffer 44 of B port one 2 comprises input buffer 44-1, transmission gate 44-2 and OR circuit 44-3.

Address register A 20 comprises address latch 101, transmission gate 102, address latch 103, transmission gate 104, transmission gate 105, address latch 106 and transmission gate 107.Further, address register B 21 comprises address latch 111, transmission gate 112, address latch 113, transmission gate 114, transmission gate 115, address latch 116 and transmission gate 117.

Address update register 19 comprises refresh address counter/register 19-1, phase inverter 19-2 and transmission gate 19-3.Produce and the maintenance refresh address by refresh address counter/register 19-1.

Through the operation of foregoing circuit configuration, when outside device, importing Read instruction or Write instruction, the address transfer that and instruction is got into together arrives address latch 101 or 111.In the situation of Read instruction with address transfer to address latch 105 or 116 and do not need to operate any time.Timing in last data that obtains a series of write datas in the situation of Write instruction is arrived address latch 103 or 113 with address transfer.

Shown in the circuit arrangement of Fig. 8, response and the command signal RA3 that respectively is transferred to DRAM core 14, WA3 from arbiter 15; RB3, the pulse signal RA3P that WB3 and REF3 are corresponding, WA3P; RB3P, WB3P and REF3P are transferred to DRAM core 14 with address signal from an address latch.

Fig. 9 is and the relevant circuit block diagram of data output.

Comprise data latches 121, transmission gate 122, data latches 123, parallel-to-serial converter 124, output buffer 125 and transmission signals generation circuit 126 with the relevant part of data output of data I/O circuit 33.And, comprise data latches 131, transmission gate 132, data latches 133, parallel-to-serial converter 134, output buffer 135 and transmission signals generation circuit 136 with the relevant part of data output of data I/O circuit 43.

Amplified by sense buffer 55 from the data that memory array 51 is read, be added to data I/O circuit 33 or data I/O circuit 43 through transmission gate A 24 or transmission gate B 25 respectively.If the instruction of carrying out with read relevantly from the data of A port one 1, then transmission gate A 24 opens, and if execution instruction with read relevantly from the data of B port one 2, then transmission gate B 25 opens.The data that provide are by this way latched by data latches 121 or 131 and keep.

Transmission gate 122 or 132 responses are opened the scheduled wait time from the transmission signals that transmission signals generation circuit 126 or 136 provides after a corresponding ports reception reads instruction.So the data transmission with data latches 121 or 131 arrives data latches 123 or 133 respectively.After this with parallel-to- serial converter 124 or 134 data are transformed to serial data from parallel data. Give output buffer 125 or 135 with this data transmission then, and output therefrom.

Figure 10 is the circuit diagram of the configuration of expression transmission signals generation circuit 126 or 136.

Transmission signals generation circuit 126 or 136 comprises trigger 141 to 144 and multiplexer 145.To read instruction signal RA1 or RB1 is added to trigger 141, and synchronously is transferred to the next one from a trigger with clock signal clk A1 or CLKB1 continuously.Stand-by period information A and B are added to multiplexer 145.This stand-by period information is for example confirmed the length of stand-by period with the number of clock period.According to stand-by period information, multiplexer 145 is selected the Q output of a relative trigger device, and it is exported as data transfer signal.

Figure 11 is and the relevant circuit block diagram of data input;

Comprise data input buffer 151, serial-to-parallel converter 152 and data transmission device 153 with the relevant part of data input of data I/O circuit 33.Comprise data input buffer 154, serial-to-parallel converter 155 and data transmission device 156 with the relevant part of data input of data I/O circuit 43.

Respectively with serial-to- parallel converter 152 or 155 with serial be input to data input buffer 151 or 154 data conversion become parallel data.When last data of input, parallel data is transferred to write data register A 22 or write data register B 23.When with Write instruction when arbiter 15 is transferred to DRAM core 14; Response expression and Write instruct the corresponding signal WA3P or the WB3P regularly of transmission of DRAM core 14, with the data transmission of write data register A 22 or write data register B 23 to DRAM core 14.

Figure 12 is the timing diagram of expression operation of enforcement when getting into the Read instruction continuously.

A port one 1 and B port one 2 respectively with have clock signals of different frequencies CLKA and CLKB and synchronously operate.In this example, the operation of A port one 1 usefulness maximum clock frequency, and the lower clock frequency operation of B port one 2 usefulness.

A port one 1 has following setting: cycle=4 that read instruction (CLKA), data stand-by period=4, and burst length=4.B port one 2 has following setting: cycle=2 that read instruction (CLKA), data stand-by period=2, and burst length=2.In the mould register of each port, data stand-by period and burst length are set.

The instruction storage that will be received by port is in each order register.Refreshing instruction is stored in the refreshing instruction register.Arbiter is kept watch on these order registers, and with the order that receives instruction instruction is transferred to the DRAM core.Transmission next instruction when accomplishing the processing of a last instruction.

To be transferred to each port data latch (seeing also Fig. 9) from sense buffer from the data that the DRAM core is read.Later on data are become serial from parallel transformation, output is synchronously exported with external clock as train of impulses.

Though once, do not influence the operation of B port from A port input refreshing instruction, shown in figure 12.

Figure 13 is the timing diagram of expression operation of enforcement when input Write instructs continuously.

When write operation, get the form that train of impulses is imported from the data of the outside input of device.The timing of Write instruction storage in the write command register is the timing of last data of input pulse string input.

Shown in figure 13, the refreshing instruction that provides from the A port does not influence the operation of B port.

Figure 14 is the timing diagram of expression when A port and B port both operate on the maximum clock frequency.

Shown in figure 14, between the clock signal of these ports, possibly there is phase differential.Two ports have following setting: cycle=4 that read instruction, data stand-by period=4, and burst length=4.As from scheme visible, even also no problem about operation when two ports are operating in maximum clock frequency with continuous input Read instruction.

Figure 15 is the timing diagram of expression when A port and B port both operate on the maximum clock frequency.In Figure 15, two ports receive the Write instruction continuously.

Shown in figure 15, between the clock signal of these ports, possibly there is phase differential.Two ports have following setting: write command cycle=4, data stand-by period=4, and burst length=4.As from scheme visible, even when two ports are operating in maximum clock frequency with continuous input Write instruction, also can carry out suitable operation.

Figure 16 is expression when instruction each timing diagram of operating when Read instruction changes to the Write instruction;

Shown in figure 16, instruction transmission " Write → Read " needs an extra command interval when the command interval with " Write → Read " or " Read → Write " compares.This is it to be handled in the timing when getting into last data of train of impulses input because we transmit the Write instruction.On the contrary, for the timing of it being handled Read of transmission instruction is defined as the timing that gets into the Read instruction, making need provide an extra command interval when in succession instruction is " Write → Read ".Such needs can be thought to become this fact of parallel data to cause the input data conversion of getting the train of impulses input form.If only import a blocks of data rather than as the train of impulses input, import 4 blocks of data, what for to an extra command interval need be provided when two instructions in succession all are " Write → Read " yet.

In this configuration as only import a blocks of data for a Write write command; Even if use identical command interval in the situation with " Write → Write " or " Read → Read ", also can suitably operate for " Write → Read " continuity of command.

Figure 17 is that expression is when instructing the timing diagram of when " Read " changes to " Write ", importing refreshing instruction.

At the top of figure, express the timing that get into refreshing instruction.Can both suitably get into refreshing instruction in any timing in during like explanation.For example, even if at timing shown in Figure 17 input refreshing instruction, refreshing instruction has only when the previous Write write command of completion and just begins refresh operation, when refreshing instruction is kept at stand-by state till.Therefore, if refreshing instruction drop on corresponding with this stand-by state during inherent any timing can both suitably get into refreshing instruction.

Figure 18 is the timing diagram of the operation when making a port deactivation, implemented of expression;

Shown in figure 18, when making a port (that is, the A port among Figure 18) deactivation, produce refreshing instruction, thereby carry out refresh operation according to refresh timer inside.

Figure 19 is the timing diagram of the operation when making two port deactivations, implemented of expression.

Shown in figure 19, when making two port deactivations, produce refreshing instruction, thereby carry out refresh operation according to refresh timer inside.

Figure 20 A and 20B are the timing diagrams of expression DRAM core operation.

Figure 20 A representes the situation of read operation, and Figure 20 B representes the situation of write operation.In the operation timing shown in Figure 20 A and 20B, before accomplishing whole operation, to select through word line, data are amplified, and write back and the instruction of entering is sent in precharge consecutive operation.

Figure 21 is the timing diagram of the dual-rate operation when only making a port operation, implemented of expression;

Through making a shut-down operation in two ports, can shorten instruction input half the at interval to operation port.When this situation took place, the earliest possible cycle of external command and the earliest possible cycle of internal actions were mutually the same.In the example of Figure 21, shortened command interval and do not changed clock frequency.In this situation, shorter because burst length also becomes, so message transmission rate identical with when the time with two ports.

Figure 22 is the timing diagram that expression is operated when dual-rate when making clock frequency twice height make the message transmission rate twice;

In Figure 22, during shut-down operation in making two ports, be arranged on the frequency of high twice being input to the operation port clock signal.Relevant therewith, the time interval of instruction input shortens half the.In this situation, because burst length identical with when with two ports, so message transmission rate is fast for the twice that kind when with two ports.

In addition, because only external timing signal is imported the I/O circuit arrangement, so if design this circuit arrangement to such an extent that can deal with high speed operation then accomplish dual-rate operation in fact easily.

Figure 23 is the figure that is used to explain the 2nd embodiment of the present invention;

Generally, enlarge storer according to its expenditure.This is applied to the situation of multiport memory equally, and possibly exist in order to enlarge storage space provides the situation of a plurality of multiport memories.

Multiport memory comprises arbiter, and detects which instruction and early get into each port, then with detected order execution command.Even when will instruct each port of input in timing much at one the time, also confirm an order for one after the other executing instruction.In example shown in Figure 23, provide a plurality of multiport memory 200-1 to 200-n, from A port controller 201 and B port controller 202, identical instruction is added to multiport memory 200-1 to 200-n.Even if simultaneously instruction is added to A port and B port, because signal wire has the different length and/or the influence of power supply noise, the relative timing of each multiport memory of instruction arrival also maybe be slightly different.In this situation, the arbiter of each multiport memory can be to execute instruction from the different order of memory to memory.

If point to different address to the instruction of A port with to the instruction of B port, the different order that then execute instruction between the memory device maybe not can become a problem.Yet, when each instruction is during for same address, problem will take place.

For example, when sense data after writing the same storage unit of access during with sense data before writing the same storage unit of access between data retrieved be different.And the data of B port are retained in the storer when writing the data of B port after the data that writing the A port, if operate then the data of A port are retained in the storer with opposite order.

If different from the order of memory to memory execution command with above-described mode, then just there is serious problem in the reliability about data.

Therefore, when with a plurality of multiport memory, the decision that arbiter is made is consistent between storer.For this reason, the 2nd embodiment of the present invention specifies in the multiport memory one to be main device 200-1, and with remaining device conduct from device 200-2 to 200-n.Observe the decision of making by the arbiter of main device from device.

Figure 24 is the block scheme of expression according to the 2nd embodiment of multiport memory of the present invention.It is A port and B port that the configuration of this example has two ports.

With the different A of the comprising port one 1A of the 1st embodiment shown in Figure 4 and B port one 2A have respectively BUSY signal I/ O device 36 and 46 this true with the address comparator 26 relatively address of A ports and this fact of address of B port are provided.If address comparator 26 detects matching addresses, therefore produce matched signal, then arbiter 15A will change the operator scheme of DRAM core so that begin continuous mode.

Figure 25 A and 25B are the timing diagrams that is used to explain continuous mode.

Shown in the operation of the 1st embodiment of figure (Figure 20) expression, the operation of DRAM core is divided into ROW (OK) operation and COLUMM (row) operates.In the present invention, carry out the ROW operation, COLUMM operation and precharge operation are as a series of continuous executable operations, and this has defined the single built-in function cycle.

Continuous mode in the 2nd embodiment is identical with the row accessing operation of common DRAM, carries out an instruction repeatedly for same storage unit.That is, this pattern is repeatedly carried out COLUMM and is operated laggard line precharge after the ROW operation.When adding continuously, carry out the instruction of back and do not carry out the instruction of front the Write of same memory unit address instruction.One after the other carried out these Write instruction even if this is, the data that write by the instruction of front will be covered by the data of the instruction of back.

Shown in Figure 25 A, it is shorter than 2 cycles of common built-in function that continuous mode allows to make operation to shorten to, thereby the extra time is provided.To distribute to the point (during hereinafter this edge being called Wait (wait)) between ROW operation and COLUMM operation by the edge, limit that obtains this extra time.During this Wait, implement to be used to make main device and from the consistent processing of the instruction execution order between the device.

Below, we explain with the BUSY signal and make main device and from the consistent process of the operation between the device.

In order to guarantee at main device with from there being identical instruction execution order to use the BUSY signal between the device.BUSY signal I/ O device 36 and 46 is as the BUSY output circuit of the BUSY signal among the output main device 200-1 with as the BUSY input circuit that from device 200-2 to 200-n, receives the BUSY signal.With indication main device sign or from the information stores of device identification mould register 31 or 41.

Memory device receives the instruction from a port, the operation of beginning shown in Figure 20 A and 20B.

When the port input instruction from other, when being accessed in the same address in ROW operating period, address comparator 26 produces a matched signal.When repeating this matched signal, arbiter 15A provides the continuous mode signal to the control circuit 53 of DRAM core 14.Response continuous mode signal, DRAM core 14 is transferred to continuous mode shown in Figure 25 B.

During Wait, main device 200-1 produces BUSY-A signal or BUSY-B signal according to the decision that arbiter 15A makes.In this example, produce the BUSY signal for a port of receiving instruction more already by arbiter 1SA identification.

Similarly, during Wait in, detect by main device from device and to produce the BUSY signal, change the decision of making by its arbiter 15A, if just defer to main device so that it is different from the indication of BUSY signal.Implement the COLUMM operation according to altered instruction order then.

Figure 26 is the timing diagram of the operation when the Write for the Read of A port instruction and B port instructs generation BUSY signal, implemented of expression.

In this embodiment, the BUSY signal has the logic level " L " that an indication is selected.And, preferentially transmission with non-synchronously receive the BUSY signal.This is because promptly exchange the BUSY signal in need be during limited Wait.

In the example of Figure 26, because the ReadA2 of A port is more Zao than the WriteB2 of B port, so main device produces the BUSY signal of indication A port in during Wait.Receive this BUSY signal from device, and rely on the ReadA2 of A port more Zao than the WriteB2 of B port.Then, main device and from device with ReadA2 at first then the order of WriteB2 carry out the row operation continuous mode.

Figure 27 is the timing diagram of the operation when the Write for the Read of A port instruction and B port instructs generation BUSY signal, implemented of expression.And Figure 26 explains the Read instruction situation early of A port.Figure 27 representes the Write instruction situation early of B port.

Figure 28 is the timing diagram of the operation when the Write for the Write of A port instruction and B port instructs generation BUSY signal, implemented of expression.

Example of operation shown in Figure 28 is about the Zao situation of Write instruction of the Write of A port instruction than B port.That is, because the WriteA2 of A port is more Zao than the WriteB2 of B port, thus produce the BUSY signal of indication A port, and be added to from device.In this situation, because the data that are written into through the Write instruction of carrying out the A port will be capped immediately, so have only the write command of B port because WriteB2 is because it gets into and be performed in the back.

Figure 29 is the timing diagram of the operation when the Write for the Write of A port instruction and B port instructs generation BUSY signal, implemented of expression.

Example of operation shown in Figure 29 is about the Zao situation of Write instruction of the Write of B port instruction than A port.In this situation, because the data that are written into through the Write instruction of carrying out the B port will be replaced immediately, so have only the write command WriteA2 of A port to be performed.In this example, be provided with the clock frequency of A port to such an extent that be lower than the clock frequency of B port slightly.Though when comparison order WriteA2 and WriteB2, for A port command input a little earlier, be B port morning when receiving last data input.Therefore, the Write that confirms the B port instructs more Zao than the Write instruction of A port.

The description that provides does not above also have the situation that combines of instructing with reference to the Read about the Read of A port instruction and B port.Because no matter relative timing how, the reliability of data is unaffected, so in this situation, need not produce the BUSY signal.

Figure 30 is the timing diagram that is illustrated in the operation in the configuration that can handle the interrupt instruction of being sent by controller.

" interrupt instruction " is the indication that instruction changes the decision of being made by the arbiter of main device when beginning BUSY signal.Cause the method for interruption to comprise:

A) as the instruction input;

B) special-purpose terminal pins is provided;

C) with specific address combination; With

D) use the BUSY signal.

Method d) use controller pair BUSY to be provided signal with different port of port for its generation BUSY signal, and arrangement primary memory and it is detected from storer.

In the example of Figure 30, when the BUSY signal takes place the Write instruction for the Write of A port instruction and B port, produce interruption.As Figure 28 and Figure 29 being combined the description of carrying out, when the combination results BUSY of Write and Write signal, have only in instructing one of the Write of Write instruction and the B port of A port to be performed.As a result, with losing the data that early get into.

In Figure 30, the WriteA2 of A port is more Zao than the WriteB2 of B port, makes to produce the BUSY signal that points to the A port.After receiving the BUSY signal of main device generation, controller produces interrupt instruction so that prevent to delete the Write data of A port.

Main device and receive interrupt instruction from the device slave controller changes the decision of being made by arbiter, then finishes the back according to interrupt instruction at waiting time and carries out the Write operation.That is, arbiter changes their decision and points out that the instruction WriteA2 of A port is more late than the instruction WriteB2 of B port, implements the write operation relevant with WriteA2.This write data that can prevent the A port is deleted.In the situation of Write → Write combination, all need just carry out write operation once, making can distribution ratio Read → Write combination or the long waiting time of continuous mode of Write → Read combination.Carry out interrupt instruction so can utilize this waiting time response BUSY signal.

Below, we describe the address comparator that is used to realize aforesaid operations, the configuration of BUSY I/O system and interrupt system.

Figure 31 is the address comparator of expression according to the multiport memory of the 2nd embodiment of the present invention, the figure of the configuration of BUSY I/O system and interrupt system.

Address comparator 26 relatively is stored in the address in the address register, and when having coupling between the address of the address of A port one 1 and B port one 2 the output matched signal.And, in order to point out that which two address is match address, produce signal ARA, AWA, ARB and AWB.For example, when showing, the address of the Write instruction of the address of the Write of A port instruction and B port AWA and AWB are arranged on " H " when mating.Each all obtains a logic NAND of these signals NAND circuit 208 to 210, makes N1, and one among N2 and the N3 becomes " L ".

(below address comparator 26) provides BUSY signal I/ O device 36 and 46 and interrupt circuit on Figure 31 left side.According to the setting of mould register 31 or 41, the detection of BUSY and I/O hardware controller 211 responses match signal in the main device situation produce activation signal (master) and from the device situation, produce activation signal (from).Activation signal (master) activates BUSY output circuit 212 and 213, and activation signal (from) activation BUSY input circuit 214 and 215.

In arbiter, the instruction of selecting is outputed to output terminal RA3 as in the instruction order first, WA3, among RB3 and the WB3 one (be in the output terminal one be " H ").In the main device situation, RA3 is latched by latch 216 and 217 response signal N4 to WB3, and signal N4 is made up of the pulse corresponding with the forward position of matched signal.According to latched data output BUSY-A signal and BUSY-B signal.

From the device situation, be the BUSY-A signal of " L " if receive, then will be arranged on " L " from the signal N10 of interrupt circuit 218 outputs.If receiving is the BUSY-B signal of " L ", then will be arranged on " L " from the signal N11 of interrupt circuit 219 outputs.When signal N10 and N11 were in deactivation status, they were " H ", and they become " L " when detecting BUSY signal or interrupt instruction.

Break detection device 220 detects the interrupt instruction that slave controller provides, and output look-at-me A or B.Give the right of priority of the BUSY signal of look-at-me, and they are transferred out as signal N10 and N11 getting into.

Three comparer 80-3 shown in Figure 31 bottom, 80-5 and 80-6 are the parts (seeing also Fig. 6 A and Figure 24) of the comparator circuit of arbiter 15A.These comparers compare for the packing of orders that needs BUST to confirm.

Figure 32 is the timing diagram of the operation of a main device of expression.Figure 33 is timing diagram from the operation of device of expression.

The situation that mate each other the address of the address of the Read instruction of these three timing diagram explanation A ports and the Write instruction of B port.The main device decision A port of Figure 32 is morning, and Figure 33 determines the B port early from device.In this situation, the comparer 80-3 of main device output is the N21 of " L " and is the N22 of " H ".Further, the comparer 80-3 output from device is the N21 of " H " and is the N22 of " L ".Main device produces the BUSY-A signal, when receiving the BUSY-A signal, N10 is changed over " L " from device.Because at this time point N1 is " L ", so be added to from the comparer 80-3 of device through NOR (nondisjunction) circuit 221 and the LOW signal of phase inverter 222 with N10.Accordingly, from the output of the comparer 80-3 of device change to be " L " N21 be the N22 of " H ".In this mode, changed the decision of making by arbiter.

The situation that mate each other the address of the address of the Write instruction of the A port that my consideration now is opposite with said circumstances and the Read instruction of B port.In this situation, be changed from the comparer 80-5 of device output, thereby change in the decision of from device, making by arbiter.

Relatively the comparer 80-6 of WA2 and WB2 has a peripheral circuit configuration that is different from comparer 80-3 and 80-5.This is because when response Write and Write combination results BUSY signal, have only one will be retained in the instruction of the instruction of A port and B port.

Figure 34 is the timing diagram of expression operation of the main device of enforcement when the write address of two ports is identical.Figure 35 is the timing diagram from the operation of device of expression enforcement when the write address of two ports is identical.

We consider that main device shown in figure 34 decision A port early and shown in figure 35 from device decision B port situation early now.In the moment that address comparator 26 has just produced a matched signal, the comparer 80-6 of main device output be " L " N25 be the N26 of " H " and from the comparer 80-6 output of device be " H " N25 be the N26 of " L ".Main device is RA3, WA3, and RB3 and WB3 are latched in this state, and export a BUSY-A signal.

When as in this situation, in the Write-Write combination, producing the BUSY signal, the Write instruction that needs one of deletion early to get into.For this purpose, phase inverter 231 is provided, NOR circuit 232, NAND circuit 233 and 234, phase inverter 235 and 236.The responses match signal, " H " pulse that HIGH edge pulsing circuit 230 produces signal N4.Through certain logical operation signal N4 and signal N3 are combined, produce " H " pulse among the signal N31.In this example, N26 is " H " for main device, makes N33 produce " H " pulse, causes N25 to change over " H " and N26 changes over " L ".Here, delay circuit 237 and 238 is used to provide one can be used for before the change generation, producing the extra time of BUSY signal, and prevents to be changed once more when altered feedback of status has been got back to NAND circuit 233 and 234 when inciting somebody to action.From device, N25 is changed over " L ", N26 is changed over " H ".

As described in the past, main device produces the BUSY-A signal, and what receive this signal makes its N10 change over " L " from device.Because at this specified moment N3 is " L ", so be inverted once more, cause making N25 to change over " H " from the comparer 80-6 of device, make N26 change over " L ".

Delay circuit 250 receives signal N4, and makes schedule time length of this signal delay, thereby produces during the Wait.Here, when selecting N1 or N2, select Delay (delay) (t1), when selecting N3, select Delay (t2).

Provide NAND circuit 251 and 252 and phase inverter 253 and 254 be used for when finishing during the Wait, removing the Write instruction of being skipped from order register.For example, if N25 is that " L " and N26 are " H " when during Wait, finishing, the Write that then will carry out the A port instructs.Therefore, produce RESTWB2 for Write instruction from register deletion B port.Because need in during Wait to receive or interruption change decision, so the instruction in the order register is intactly remained during this through BUSY.

Figure 36 is expression when the write address of two ports matees each other main device is operated when making controller send interrupt instruction timing diagram.Figure 37 is expression when the write address of two ports matees each other when making controller send interrupt instruction from the timing diagram of device operation.

Shown in figure 36, the Instruction Selection state in main device reverses owing to interrupting, and, shown in figure 37, at the Instruction Selection state from device owing to the BUSY signal reverses, then further owing to interruption is reversed.Here owing to interrupt the operation of inverted status with owing to the BUSY signal and the operation of inverted status is identical, we will omit its detailed description.

In the operation of above-mentioned the 2nd embodiment, the instruction cycle of the instruction expansion that design is followed from a given instruction to the next one makes it even after producing BUSY signal or interrupt instruction, does not also change.

In Figure 26, for example, though the BUSY signal takes place response ReadA2, the command interval of ReadA2 → ReadA3 is identical with the command interval of ReadA1 → ReadA2.Requirement is treatments B USY signal and look-at-me during Wait.Because this reason, a large amount of from device when because long system bus, the exchange of BUSY signal such as the slow-response of controller or look-at-me just need during the long Wait when long-time to need.

In order to eliminate this problem, when the next instruction that postpones to follow BUSY signal and look-at-me is imported, can expand Wait during.That is the command interval that, can expand ReadA2 → ReadA3 when time during the lengthening Wait makes it longer than the command interval of the ReadA1 → ReadA2 in Figure 26.

In order to postpone an instruction input, delay that can declarative instruction input in design sheets and can it operated CONTROLLER DESIGN according to tables of data.Shown in figure 31 through reaching the expansion during the Wait time delay that adds long delay circuit 250.If during expenditure needs adjustment Wait, two or many lag lines can be provided in delay circuit 250 then, make through being provided with of a mould register to change the possibility that is set to that postpones length.

When expanding by this way during the Wait, produce except the response Write-Write packing of orders during the Wait that also can provide long in external other situation of situation of BUSY signal.Consider this point, even controller also can send an interrupt instruction when the BUSY signal appears in response Read-Write or the Write-Read packing of orders.

Among the present invention who describes in the above, when instruction gets into N port, a minimum instruction of any given port in the cycle one then ground carry out and N the corresponding all N of port instructs.Therefore, one appears in the device outside in minimum instruction with the relevant accessing operation of any given port and to be implemented in the cycle.In this situation, have only when the time and just the BUSY signal can take place from the same address of a plurality of port accesses.So can obtain BUSY signal probability of happening, this probability is the same low with the BUSY signal probability of happening of SRAM type multiport memory.

And in semiconductor storage unit of the present invention, internal circuit comprises a memory cell array, and this array is made up of the refresh circuit of the timing that each dynamic type storage unit and define storage units are refreshed.In the 1st pattern, response is input at least one the refreshing instruction refresh of memory cells in N port, in the 2nd pattern, in the definite periodic refreshing storage unit of refresh circuit.

That is, above-described the present invention has the 1st operator scheme, and response is implemented refresh operation and the 2nd operator scheme from the instruction of an outside port in this pattern, and the response internal refresh circuitry is implemented refresh operation in this pattern.Because this configuration; Allow an outside port to operate as a port that is used to refresh management; So that receive refreshing instruction at constant interval, if perhaps this port that is used to refresh management is in deactivation status then internal refresh circuitry is implemented refresh operation.This makes according to system configuration becomes possibility with a kind of flexible way management refresh operation.

[the 2nd aspect of the present invention]

Below we describe the 2nd aspect of the present invention.

There are some kinds of multiport memories.Hereinafter, relate to storer, and allow from common memory array of each port access independently of each other with a plurality of ports.For example, the multiport memory of two port types is equipped with an A port and a B port, and allows from proceed to the read/write access of common storage independently with the CPU-A of A port link with from the CPU-B with the B port link.

As this type multiport memory, the storer with SRAM memory array is known, wherein duplicate be provided with in provide each word line and bit line right, each storage unit all with 2 groups of word lines and bit line to being connected.Yet this multiport memory has the low problem of current densities, wherein need provide word line and bit line right copy group.

In order to eliminate this problem, can with the used shared storage identical mechanism of computing machine with a plurality of processors configurations.Shared storage has a plurality of ports that offer common storage.Typically, SRAM is used as storer, and processes a plurality of ports with discrete IC (integrated circuit).When a plurality of ports carry out access simultaneously, because memory array is shared, so can not carry out simultaneously operating accordingly with a plurality of ports.Prevent the simplest method that this problem takes place be to each port produce BUSY signal in case prevent when when a port carries out access to the access of another port.Yet this causes the problem of limits storage expenditure.Consider this point, for common storage provides the arbiter that is called arbiter, arbiter is confirmed the right of priority that the access of a plurality of ports receptions requires.The controller of structure memory array is carried out and the corresponding operation of access requirement with the order of right of priority.For example, promptly handle the access requirement with the order that arrives with the order that access is required be added to each port.

In this situation, memory array finally randomly from a plurality of ports by access.Therefore, can not be provided at the same row address row accessing operation of access column address in succession continuously, and such row accessing operation can obtain in DRAM typically.That is, select, be the read/write operation access and the storage unit that resets, respond single access and implement all these operations.

When processing a shared storage, usually, SRAM is used as memory array by routine.This is because SRAM can carry out the high random access operation, so and because do not need refresh operation can easily use SRAM.Yet the multiport memory of monolithic chip has with word line and the right copy group of bit line routinely, and the multiport memory of the monolithic chip on the basis of the memory array with common SRAM configuration does not also use in practice.

Sum up, multiport memory and shared storage are processed with SRAM, and need not need the DRAM of refresh operation.

The data volume that when system constantly provides high-performance, will be processed increases, and multiport memory also need have big capacity.Can use dynamic type storage unit (DRAM) array to process multiport memory, the DRAM array has higher current densities than SRAM, thereby with low cost the multiport memory with large storage capacity is provided.Yet the refresh operation of storage unit becomes a problem.

In the DRAM of routine, need with constant interval refreshing instruction be provided between read/write instruction from the device outside.For this reason, the controller device in the system that with DRAM is the basis has timer and/or the control circuit that is used to refresh management.Yet, in order to the system of SRAM, such circuit is not provided for the multiport memory on basis.Even be that process in the situation of storer on the basis with DRAM, in these systems, need and can use sort memory with the mode identical with the multiport memory of routine.That is the multiport memory that, has the memory array of being made up of DRAM need oneself carry out refresh operation by it.

The purpose of this invention is to provide and have the memory array of forming by the DRAM core, and need not consider refresh operation, have large storage capacity and easy-to-use multiport memory thereby provide with low cost with regard to employable multiport memory.

Figure 38 is the figure that is used to explain the principle of the invention, the situation of expression when implementing read operation for two ports.

On the minimum interval that can implement 3 built-in function cycles, provide and be added to two outside ports, the instruction of A port and B port.That is, an external command cycle is arranged on the length of the longer duration that needs than 3 built-in function cycles.Respectively clock signal clk A and CLKB are input to A port and B port, and clock signal is synchronously carried out an external device (ED) and the address between each outside port and the exchange of data at device.Address (not drawing among the figure) and instruction is got into simultaneously.Read instruction when getting into the A port with the B port when making on the cycle at minimum external command, the input signal of arbiter through right of priority is given at first to arrive controlled the operation of core.Can implement 3 built-in functions in cycle at an external command as stated, list 2 read operations of execution at memory array in the cycle, then read data outputed to A port and B port at this external command.A port and B port both keep data retrieved, and when the external command cycle that the next one is followed begins, promptly synchronously export data retrieved with the 4th clock signal that reads instruction from input.That is, the stand-by period of data is 4 in this situation.

Provide refresh timer as internal circuit, refresh timer produces refreshing instruction on one's body at it.Because can implement 3 built-in functions in the cycle at an external command as stated, thus when producing refreshing instruction at the single external command A that can execute instruction in the cycle, instruction B and refreshing instruction.Output read data when the external command cycle that the next one is followed begins.In this mode, can have no relation with refresh operation from device external access multiport memory.

In the example of Figure 38, respond the read data of output that reads instruction.That is, burst length is 1.So after the output of completion read data, externally outside port is not exported any data in the clock period of 3 of the instruction cycle remainders in a clock cycle, this causes invalid data transmission.Can eliminate this problem through the lengthening burst length.

Figure 39 is the figure that is used to explain the principle of the invention, and the indicating impulse string length is 4 example.In this example, identical with said circumstances, external command cycle of 2 outside ports is arranged on the length that can supply 3 built-in function cycles.Further, corresponding 4 clock period in external command cycle.With clock signal synchronously single external command in the cycle from 4 output datas of an outside port.So,, then can both realize gapless read operation, thereby increase message transmission rate very bigly at two ports if burst length is set according to the number of clock period in an external command cycle.In this situation, require to respond internally input store array or internally export of single access from memory array with the as many data item of burst length.For example, if the number of the data I/O pin of outside port be 4 and burst length be 4, then need guarantee to export 16 bit data or with 16 bit data input store arrays from memory array by single accessing operation.

We should be noted that A port and the not necessarily synchronous operation of B port, as long as and will be provided with the minimum period to such an extent that equal the duration that 3 built-in function cycles need, just can each external command cycle be arranged on any timing independently of each other.

And the number of outside port also can be any number.If the number of outside port is set to n, then the external command cycle with each port is arranged on and can carries out on the minimum period in n+1 built-in function cycle.If meet this requirement, what for to all operations that when refresh operation is performed, also can implement each port requirement at an external command in the cycle, thereby allow the use multiport memory and have no relation with refresh operation.

Figure 40 and Figure 41 be expression as 2, the figure of the relation when 3 and n port between a minimum external command cycle and each built-in function cycle.

As these figure shown in, if the number of port is 2, the then minimum external command cycle has the length that can supply 3 built-in functions, and if the number of port be 3, the then minimum external command cycle is the time span that can carry out 4 built-in functions.Further, if the number of port is n, the then minimum external command cycle equals to carry out the time span of n+1 built-in function.

Figure 42 and Figure 43 A are to represent the figure of the configuration of multiport memory according to an embodiment of the invention to 43C.Figure 42 representes DRAM core and its interlock circuit, and Figure 43 A representes the A port, and Figure 43 B representes the B port.Further, Figure 43 C representes refresh circuit.Figure 43 A is connected with the each several part of Figure 42 to the circuit shown in the 43C.

Shown in these figure; The multiport memory of this embodiment comprises DRAM core 2011; Be used to control and confirm order of operation and guarantee to organize temporary transient storage instruction, the register of address and data more with the arbiter 2026 of the order implementation and operation of confirming; 2 outside port and refresh circuits of forming by A port 2030 and B port 2,040 2050.

A port 2030 comprises mould register 2031 and 2041 respectively with B port 2040; CLK impact damper 2032 and 2042; Data I/ O circuit 2033 and 2043; Address input circuit 2034 and 2044, and instruction input media 2035 and 2045, they are operated according to the clock frequency of respectively separating that provides from the device outside.Data stand-by period and burst length are stored in mould register 2031 and 2041, they can be provided with respectively.Data I/ O circuit 2033 and 2043 is equipped with according to burst length implements the parallel-to-serial conversion of output/output data and the mechanism of serial-to-parallel conversion.

Refresh circuit 2050 comprises refresh timer 2051 and refreshing instruction generator 2052.Refresh timer 2051 produces on predetermined space and refreshes commencing signal, and refreshing instruction generator 2052 produces refreshing instruction accordingly.

To be added to the instruction of A port and B port respectively, address and write data are stored in the register.Also refreshing instruction is stored in the refreshing instruction register 2027, and refresh address is stored in refresh address counter/register 2018.

The order that arbiter 2026 arrives according to instruction is confirmed the order of execution command, and instruction is transferred to the control circuit 2014 of DRAM core 2011 with the order of confirming.Further, arbiter 2026 is transferred to corresponding address register and corresponding data register (in the write operation situation) with transmission signals.In DRAM core 2011, the instruction that control circuit 2014 responses provide, control code translator 2013, write amplifier (WriteAmp) 2015 and sense buffer 2016, thus implement accessing operation for memory array 2012.In the situation of write operation; Code translator 2013 is deciphered the address of access in order to carry out write operation; So that activate word line and column signal line in memory array 2012, cause the write data that is stored among write data register A2022 and the B2023 is passed through WriteAmp 2015 write store arrays 2012.In the situation of read operation, access memory array 2012 in a similar fashion, cause through transmission gate A2024 and B 2025 read data being transferred to from sense buffer 2016 data output circuit of each port.According to the transmit timing of the operating cycle control transmission door of DRAM core 2011, and confirm transmit timings by control circuit 2014.Synchronously export output data with corresponding external timing signal from the data output circuit of each port.

Below, we describe and instruction and handle, each the relevant detailed situation in address process and the data processing.

Figure 44 is relevant device configuration is handled in expression according to the 1st embodiment and instruction figure with Figure 45.With Figure 42 and Figure 43 A-43C in add identical reference number on the identical parts.This is applied to other figure too.

Shown in figure 44; The instruction inputting device 2035 of A port comprises input buffer 2036; Command decoder 2037 and (n-1) clock delay circuit 2038, the instruction inputting device 2045 of B port comprises input buffer 2046, command decoder 2047 and (m-1) clock delay circuit 2048.Here, n and m are burst lengths.And shown in figure 45, order register A 2028 comprises Read order register AR and Write order register AW, and order register B 2029 comprises Read order register BR and Write order register BW.

Input buffer 2036 and 2046 requires synchronously to add the Read instruction with each clock signal clk A1 and CLKB1, and command decoder 2037 and 2047 is deciphered processing.Command decoder 2037 and 2047 produces RA1 and RB1 respectively in the situation that reads instruction, and produces WA1 and WB1 respectively in the write command situation.Respectively signal RA1 and RB1 are transferred to Read order register AR and BR; Without any need for fixed cycle operator; And signal WA1 and WB1 are respectively by (n-1) clock delay circuit 2038 and (m-1) clock delay circuit 2048 delays; Till last data item of input pulse string data, then be transferred to Write order register AW and BW.And, will be transferred to refreshing instruction register 2027 by the refreshing instruction REF1 that refresh circuit 2050 produces.

Arbiter 2026 detects instruction is transferred to this 5 order register AR, AW, and BR, BW and 2027 order, and one of these instruction then are transferred to DRAM control circuit 2014 in a ground with detected order.The instruction that 2014 execution of DRAM control circuit receive, generation signal RESET1 sends next instruction when requiring arbiter 2026 when instruction execution end or near end.Response RESET1 signal, the order register that arbiter makes storage be performed instruction resets, and next instruction is transferred to DRAM control circuit 2014.

Figure 46 is the embodiment of arbiter 2026.The order that instruction arrives 5 order registers of Figure 45 detects like this shown in Figure 46 by comparer 2053.Relatively timing of two order registers of each comparer 2053 changes over " H " with its output in the situation of at first input " H ".Whether AND door 2054 is that " H " confirms whether given instruction is imported before all 4 other instructions through all relevant outputs of checking relevant comparer 2053.If the instruction of a response be the earliest signal RA3 of each instruction of response, WA3, RB3, WB3 and REF become " H ", and the address of the instruction that will respond etc. is transferred to DRAM core 2011.Carry out should instruction the time when DRAM core 2011, produce signal RESET1, and produce the signal (ReasetRA, ReasetWA etc.) that is used to make the order register that is performed instruction to reset from DRAM core 2011.When the order register that is performed instruction was resetted, the output that receives this comparer that is performed instruction 2053 changed, and the next instruction in order is transferred to DRAM core 2011.In this mode, with the order execution command of instruction input.

Figure 47 is the figure of expression according to the configuration of the 1st embodiment part relevant with address process.Hereinafter, the signal representative that has a letter " P " at its not end of signal name has the signal of the pulse that produces from the forward position of the signal of the signal name of correspondence.As shown in the figure, address input circuit 2034 and 2044 comprises input buffer 2057A and 2057B and transmission gate 2058A and 2058B respectively.Further, address register A 2019 and address register B 2020 comprise address latch A1 and B1 respectively, transmission gate 2060A and 2060B, and address latch A2 and B2, transmission gate 2062A and 2062B are with transmission gate 2063A and 2063B.Will be through address bus 2017 from transmission gate 2062A, 2062B, the address transfer that 2063A and 2063B provide is to DRAM core 2011.Further, will be transferred to DRAM core 2011 from the refresh address that refresh address counter/register 2018 provides through transmission gate 2064 and address bus 17.

When from the outside input of device Read instruction or Write instruction, the address and the input instruction that will be added to input buffer 2057A or 5027B through transmission gate 2058A or 2058B respectively are transferred to address latch A1 or B1 simultaneously.In the situation of Read instruction, through transmission gate 2063A or 2063B with to the instruction transmitting synchronous of DRAM core send the address to DRAM core 2011.In the situation of Write instruction, further give address latch A2 or B2 with address transfer in the timing of data acquisition last time, then, with to the instruction transmitting synchronous of DRAM core be transferred to the DRAM core through transmission gate 2062A or 2062B.Further, refresh address counter/register 2018 produces and preserves therein refresh address, gives DRAM core 2011 through transmission gate 2064 with this address transfer with the refreshing instruction transmitting synchronous ground to the DRAM core then.

Figure 48 is the figure of expression according to the configuration of the 1st embodiment part relevant with data output.Figure 49 is the figure of the transmission signals generation circuit of expression Figure 48.Each data I/ O circuit 2033 and 2043 of A port 2030 and B port 2040 comprises for the circuit 2065A and the 2065B of output data respectively and in order to import the circuit 2074A and the 2074B of data, we will be described later them.As shown in the figure, will be transferred to circuit 2065A or 2065B respectively through data bus 2021 and transmission gate 2024 or 2025 through the data that sense buffer 2016 is read from memory array 2012 for output data.

For the circuit 2065A and the 2065B of output data comprises data latches A1 or B1 respectively; Transmission signals generation circuit 2067A and 2067B, transmission gate 2069A or 2069B, data latches A2 or B2; Parallel-to-serial transducer 2070A and 2070B, and output buffer 2071A and 2071B.

Control circuit 2014 by DRAM core 2011 is controlled transmission gate 2024 and 2025 according to built-in function.If the instruction that is performed is Read-A (that is, for the read operation of A port), then transmission gate 2024 will be opened.If the instruction that is performed is Read-B, then transmission gate 2025 will be opened.Data latches A1 and B1 storing therein data; In each port, receive a definite stand-by period after Read instructs then; Introduce this stand-by period at these ports through transmission gate 2068A or 2068B, give each data latches A2 or B2 data transmission.Then, data are carried out conversion, then be transferred to output buffer 2071A and 2071B respectively by parallel-to-serial transducer 2070A and 2070B, and output therefrom.

Shown in figure 49, transmission signals generation circuit 2067A and 2067B adopt a series of trigger 2072 to make each Read instruction RA1 and RB1 postpone to set many time cycles of confirming by the stand-by period, thereby produce data transfer signal 2002.Because from the read data transmission response data transmission signals 2002 of transmission gate 2068A or 2068B,, finishes read data so beginning to be postponed many all after dates suitable with the stand-by period from the timing of read operation.

Figure 50 is the figure of expression according to the configuration of the 1st embodiment part relevant with the data input.For circuit 2074A and the 2074B that imports data comprises data input (Din) impact damper 2075A and 2075B, serial-to- parallel transducer 2076A and 2076B, and data transmission device 2077A and 2077B respectively.Respectively through Write data register 2022 and 2023, data transmission device 2078A and 2078B, and data bus 21 will send WriteAmp 2015 from the write data of data transmission device 2077A and 2077B to, and be written into memory array 2012.

According to burst length with serial input data from serial converted to parallel, the timing in last data item of input is transferred to Write register 2022 and 2023 then.When arbiter 2026 is transferred to DRAM core 2011 with Write instruction, through data transfer gate 2078A and 2078B also with the data transmission of correspondence to DRAM core 2011.

Figure 51 is the time diagram of the multiport memory operation of expression the 1st embodiment to Figure 58.Figure 51 and Figure 52, Figure 54 and Figure 55 and Figure 57 and Figure 58 be for the ease of explanation with single time diagram figure divided into two parts, first of an express time figure is half the, second of another express time figure is half the, exists some overlapping between them.

Figure 51 and Figure 52 represent the operation when two ports are one after the other imported in Read instruction, implemented.A port and B port, they have respectively mutual clock signals of different frequencies CLKA and CLKB are arranged, synchronously get instruction with the clock signal that receives, address and write data, and synchronously export data retrieved with clock signal.In this example, the A port operation is at maximum clock frequency, and the B port operation is in low slightly clock frequency.For the A port, Read instruction cycle=4 (CLKA), data stand-by period=4, and burst length=4.For the B port, Read instruction cycle=2 (CLKB), data stand-by period=2, and burst length=2.In the mould register 2031 and 2041 of each port, data stand-by period and burst length are set respectively.In this example, respond the I/O 4 times that an instruction and clock signal are synchronously implemented data, export data retrieved in 4 clock signals after input reads instruction.

The instruction storage that will be added to A port and B port respectively is in order register 2028 and 2029.When refresh timer 2051 produced signal, refreshing instruction register 2027 was stored in refreshing instruction its inside.Arbiter 2026 is kept watch on these order registers, and with the order that sends instruction these instructions is transferred to DRAM core 2011.After the processing of accomplishing a last instruction, transmit next instruction.The data that to read from DRAM core 2011 are transferred to the data latches 2069A and the 2069B of each port from sense buffer 2016, then data are transformed into serial data from parallel data, then synchronously export as pulse series data and each external timing signal.

As shown in the figure, will instruct Read-A2 input Read order register AR and will instruct Read-B2 to import Read order register BR.Before this, take place once to refresh, and refreshing instruction is imported the refreshing instruction register.According to the order that sends instruction, arbiter 2026 is transferred to DRAM core 2011 with the order of Read-A2 → Ref → Read-B2 with these instructions, carries out these instructions by core then.Even when at the internal implementation refresh operation, it seems that from the outside data export after the stand-by period a tentation data.Like this, just need not consider any refresh operation.

Figure 53 is illustrated in an example of adjoining land input Write instruction under the condition same as described above.Also the form with the train of impulses input is given in the data of Write running time from the outside input of device.The input last blocks of data timing with the Write instruction storage in Write order register AW.In this situation, even when producing in inside and carrying out refreshing instruction, need not consider any refresh operation yet.

Figure 54 and Figure 55 represent to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both.The figure of Figure 56 operation that to be expression implement when carrying out the Write write operation on the maximum clock frequency when A port and B port operate in.In this situation, in the clock signal of two ports, possibly there is phase differential.For two ports, Read instruction cycle=4, Write instruction cycle=4, data stand-by period=4, and burst length=4.Visible from scheming, also implementation and operation suitably in this situation.

Figure 57 and Figure 58 are that expression is operating in highest frequency when two ports, and with the time diagram of the inner refreshing instruction that produces operation of enforcement when the Write instruction changes to the Read instruction.This is to instruct the most crowded situation.

As shown in the figure, DRAM core 2011 is operated with the order of Ref → Write-A1 → Write-B1 → Read-A2 → Read-B2, between them, has no the gap.In this example, 6 time clock after input Write instruction are imported Read-A2 and Read-B2.Even if 2 clock signals of these timing advances, the also built-in function of DRAM core in advance.By the output of read data regularly being controlled from the data stand-by period of input Read instruction beginning.If the incoming timing of Read-A2 and Read-B2 is leading, then also need data output regularly be moved forward.The data output of response Read-B2 regularly too near the start time of DRAM core operation, makes and can not suitably carry out Read-B2 in this situation.Because this reason need be provided with the public interval of Write → Read transition quite longly like 6 time clock in this example.

About the public interval of Read → Write, only if because accomplished the output of Read data, can not be with in the Write data input DQ terminal, so public interval is elongated inevitably.

Figure 59 A and 59B are the figure of expression DRAM core 2011 operations.Figure 59 A representes the Read operation, and Figure 59 B representes the Write operation.Shown in these figure, respond single instruction and amplify → write back → precharge order enforcement sequence of operations, thereby accomplish whole operation with word line selection → data.

As stated, instruct from Write in the 1st embodiment that command interval is lengthened out time of instruction transition of Read instruction.In the 2nd embodiment, this is improved.When a relevant command interval was 6 clock cycles in the 1st embodiment, the 2nd embodiment can shorten to 5 clock cycles with it.

The multiport memory that the multiport memory of the 2nd embodiment of the present invention has with the 1st embodiment similarly disposes, and difference is that refresh circuit has the configuration shown in Figure 60.Figure 61 is the circuit diagram of the configuration of expression the 2nd refresh circuit 2083.

Shown in Figure 60; The refresh circuit of the 2nd embodiment comprises timer/refreshing instruction generator 2081 that the refresh timer of Figure 43 C 2051 and refreshing instruction generator 2052 are combined; The 2nd refreshing instruction register 2082 and the 2nd arbiter 2083, and will be input to refreshing instruction register 2027 from the refreshing instruction of the 2nd arbiter 2083 outputs.Identical refreshing instruction REF2 with refreshing instruction register 2027 with the 1st embodiment is input to arbiter 2026.In this configuration, the reset signal ResetREF that also will be after accomplishing refresh operation outputs to refreshing instruction register 2027 from arbiter 2026 is added to the 2nd refreshing instruction register 2082.

In the refresh circuit of the 2nd embodiment, the 2nd arbiter 2083 is provided along the path of refreshing instruction.If our expection as in the situation of the instruction transition that Write instruction → Read instructs, instruct crowdedly, then the 2nd arbiter 2083 delay refreshing instructions are to the transmission of refreshing instruction register 2027.Whether the change of instructing Read to instruct from Write takes place with the circuit arrangement shown in Figure 61 in the inspection of the 2nd arbiter 2083, and if check out that such change just postpones the transmission of refreshing instruction from the 2nd refreshing instruction register 2082 to refreshing instruction register 2027.

Shown in Figure 61; When each port is received the Write instruction that rotary device provides from the device outside; Make signal A and the B deactivation of forbidding the REF transmission; After a clock cycle, be activated, then several clock cycles after receiving last data item, (that is, 3 time clock) in this example was again by deactivation again.3 CLK deferred mount 2084A and the 2084B of Figure 61 comprise trigger etc., and are resetted by WA1 and WB1 respectively, and this causes, and WA1D and WB1D are reset when through deferred mount.The logic AND of signal A and B that obtains forbidding the REF transmission is so that produce a signal of forbidding that REF transmits.All stand when Write instructs the change of Read instruction, just can go wrong in this example because have only when two ports, and when having only a port to stand this change, do not have problems, so obtain this logic AND.Further, forbid that the signal A of REF transmission and B are that this provides an extra time so that accomplish the refresh operation before receiving last data item to the reason of a clock period deactivation only receiving Write instruction back.Further, provide deferred mount 2086 for respect to clock signal delay timing a little, so that increase in the signal of forbidding REF instruction transmission and the difference the relevant timing between the instruction that the device outside provides.

Figure 62 is the timing diagram of the operation of expression the 2nd arbiter to Figure 69.Figure 70 is the timing diagram of the multiport memory operation of expression the 2nd embodiment to Figure 72.Figure 62 and Figure 63, Figure 64 and Figure 65, Figure 66 and Figure 67; Figure 68 and Figure 69, Figure 70 and Figure 71 be for the ease of for the purpose of the explanation with single time diagram figure in two, the 1st of an express time figure is half the; The 2nd of another express time figure is half the, exists some overlapping between them.

Figure 62 and Figure 63 represent that two ports stand Write → Read and instruct change, and during the REF transmission is forbidden, the situation of refresh timer incident take place.In this situation, after accomplishing Read-A2 and Read-B2, implement refresh operation Ref.

Figure 64 and Figure 65 represent that identical two ports with said circumstances stand Write → Read and instruct change, but the situation of generation refresh timer before during the REF transmission is forbidden.In this situation, after implementing refresh operation Ref, implement the Read operation.

Figure 66 and Figure 67 explanation has only the A port to stand Write → Read instruct transition, and the situation of generation refresh timer incident in during the REF transmission is forbidden.In this situation,, implement the Read operation then accomplishing Write instruction back enforcement refresh operation Ref.

Figure 68 and Figure 69 are presented at the situation that two ports continue Write.In this situation, one when in then last data input, after the input Write instruction, just makes 3 CLK deferred mount 2084A and 2084B deactivation.

Figure 70 and Figure 71 are the time diagrams of the operation of expression 2nd embodiment corresponding with the operation of the 1st embodiment shown in Figure 57 and Figure 58.Relatively make the command interval of Write → Read instruction transition shorten to 5 time clock with the 1st embodiment from 6 time clock.

Figure 72 is the time diagram of the operation of expression 2nd embodiment corresponding with the operation of the 1st embodiment shown in Figure 56.Though relatively changed instruction execution order with the 1st embodiment, kept operation orderly about refresh operation.

As stated, the 2nd embodiment can be under any condition implementation and operation suitably, and can Write be instructed → command interval of Read instruction transition shortens to 5 clock cycles.

As stated, the present invention allows when being basis use multiport memory and need not consider any refresh operation when processing storage array with the DRAM core, has high capacity and easy-to-use multiport memory thereby provide with low cost.

[the 3rd aspect of the present invention]

Below we describe the 3rd aspect of the present invention.

There are some kinds of multiport memories.Hereinafter, relate to storer, and allow from common memory array of each port access independently of each other with a plurality of ports.For example, the multiport memory of two port types is equipped with A port and B port, and allows from proceed to the read/write access of common storage independently with the CPU-A of A port link with from the CPU-B with the B port link.

As this type multiport memory, the storer with SRAM memory array is known, wherein in copy group, provides each word line and bit line right, each storage unit all with 2 groups of word lines and bit line to being connected.Yet this multiport memory has the low problem of current densities, wherein need provide word line and bit line right copy group.

In order to eliminate this problem, can with the used shared storage identical mechanism of computing machine with a plurality of processors configurations.A shared storage has a plurality of ports that offer common storage.Typically, SRAM is used as storer, and processes a plurality of ports with discrete IC.When a plurality of ports carry out access simultaneously, because memory array is shared, so can not carry out the operation corresponding simultaneously with a plurality of ports.Prevent the simplest method that this problem takes place be to each port produce a BUSY signal in case prevent when when a port is made access to the access of another port.Yet this causes the problem of limits storage expenditure.Considering this point, is that a common storage provides an arbiter that is called arbiter, and arbiter is confirmed the right of priority that the access of a plurality of ports receptions requires.The controller of structure memory array is carried out and the corresponding operation of access requirement with the order of right of priority.For example, promptly handle the access requirement with the order that arrives with the order that access is required be added to each port.Yet this does not change the situation that when the instruction of another port is being processed, can not carry out new instruction.In this situation, need transmission BUSY signal, the device of access memory need have the mechanism of treatments B USY signal.

Randomly from a plurality of interface access memory array.Therefore, be not provided on the same row address row accessing operation of access column address in succession continuously, but in DRAM, typically can utilize this row accessing operation.That is, select a storage unit, for this storage unit of read/write operation access, this storage unit is resetted, all these operations all are performed when the single access of response.

When accomplishing a shared storage, general, routinely SRAM is used as memory array.This is because SRAM can carry out the high random access operation, again, because do not need refresh operation, so be easy to use SRAM.And the multiport memory of monolithic chip has word line and the right copy group of bit line usually, but the multiport memory of the monolithic chip on the basis of the memory array with common SRAM configuration does not also use in practice.

Sum up, multiport memory and shared storage are processed with SRAM, and need not need the DRAM of refresh operation.

The data volume that when system constantly provides high-performance, will be processed increases, and multiport memory also need have big capacity.Can use dynamic type storage unit (DRAM) array to process multiport memory, DRAM has higher current densities than SRAM, thereby with low cost the multiport memory with large storage capacity is provided.Yet the refresh operation of storage unit becomes a problem.

In the DRAM of routine, need with constant interval refreshing instruction be provided between read/write instruction from the device outside.For this reason, the controller device in the system that with DRAM is the basis has timer and/or the control circuit that is used to refresh management.Yet, in order to the system of SRAM, such circuit is not provided for the multiport memory on basis.Even be that process in the situation of storer on the basis with DRAM, in these systems, need and can use sort memory with the mode identical with the multiport memory of routine.That is the multiport memory that, has the memory array of being made up of DRAM need oneself carry out refresh operation by it.

When arbiter output busy signal, exist and use the quite problem of trouble of storer as stated.

The purpose of this invention is to provide and have the memory array of forming by the DRAM core; And need not consider to refresh any refresh operation with regard to employable multiport memory, have large storage capacity and easy-to-use multiport memory thereby provide with low cost.

In order to eliminate above-mentioned problem, dispose multi-port semiconductor memory device of the present invention and make it carry out n built-in function for the minimum input period m (m >=2) of each outside port in the time cycle doubly in length, wherein satisfy mN＜n＜m (N+1).

Above-mentioned conditional request is arranged on the time cycle that allows N built-in function cycle with each minimum instruction cycle of N port and adds on the time cycle α that lacks than the single built-in function cycle.For example when N=2, minimum external command cycle of each port is arranged on allows the time cycle in 2 built-in function cycles to add on the time period alpha.Here, time cycle α is shorter than a built-in function cycle.

The present invention utilizes the time cycle that allows 2 built-in function cycles so that eliminate because the storer that arbiter output busy signal causes uses the problem of trouble, and utilizes time cycle α to solve the refresh operation problem.

Figure 73 is the figure that is used to explain the present invention (the 3rd aspect) principle, and the situation of read operation is implemented in expression for two ports.

Make two outside ports, the instruction of A port and B port gets in the minimum interval, in this interval, can implement built-in function cycle 2.2 times.That is, 2.2 times of the built-in function cycle equal the minimum external command cycle, and are provided with the external command cycle longer than allowing enforcement 2.2 times time cycle of built-in function cycle.With time clock CLKA and CLKB input A port and B port, synchronously implement instruction with corresponding time clock respectively, address and data arrive the input of outside port and from the output of outside port.Though do not add explanation, and instruction is INADD simultaneously.When being added to A port and B port when reading instruction in the cycle at minimum external command, as shown in the figure, arbiter is controlled the instruction that when implementing the core operation, right of priority is given at first to arrive.

The DRAM core is implemented two read operations, an external command in the cycle from the memory array sense data, and data are outputed to A port and B port.A port and B port are preserved data retrieved respectively, and regularly synchronously export data retrieved with the specific clock of each clock pulse signal, and these clock pulse signals are the 6th time clock that read instruction and begin from input.That is, the data stand-by period is 6 in this situation.

Provide refresh timer as internal circuit, and produce refreshing instruction from one's body at it.When refresh operation not taking place, the internal circuit of device is operated with the mode of routine so that implement and instruction A and two corresponding operations of B in the cycle at an external command.Because can carry out built-in function 2.2 times in the cycle at an external command, thus the DRAM core will have after accomplishing two built-in functions, stay one extra time t α.

When inside produced refreshing instruction, the internal circuit of device was operated fast.Here, mean executable operations fast and do not produce t α extra time.When producing refreshing instruction, device is implemented refresh operation.Because will instruct input A port and B port simultaneously, so the instruction that will be processed will accumulate.Device apace one by one the execution command and do not provide extra time t α.Though will instruct and import A port and B port one by one, at the interval longer than the external command cycle refreshing instruction takes place only, have only instruction A and instruction B must be performed up to producing next refreshing instruction.Because the processing speed of built-in command is very fast, so when finishing, will not have the instruction of accumulation.In other words, inter-process will be caught up with the input of external command.After this, device is got back to its routine operation.Through considering the number of outside port, the number in built-in function cycle, definite extra time of α such as refresh interval.

Because when internal refresh instruction and the instruction that is input to another port take place immediately, regularly become the worst before the Read instruction, so need to instruct with Read (in the situation of two ports) in 3 cycles that are arranged on built-in function time delay (data stand-by period) that (RD) corresponding data export.Yet, because be longer than slightly the external command cycle in two built-in function cycles be exactly the device proper handling needed all, so message transmission rate is quite high.

As stated, the present invention can cancel from the outside refresh operation of device, and is provided with the external command cycle to such an extent that be longer than slightly two built-in function cycles.Need not refresh control, even when carrying out refresh operation in inside, this is invisible fully to external device (ED), and does not influence the mode of the device operation of seeing from external device (ED) from external device (ED).Therefore, can proceed to the access of storer and need not consider other port from each outside port.

In this mode, the present invention can provide the multiport memory with the DRAM storage unit, and it has high capacity and fast message transmission rate, allow to use storer simultaneously and need not consider that any refresh operation accomplishes on the basis of SRAM just as it.

In the example of Figure 73, respond one and read instruction and external clock pulse is synchronously exported a read data.That is, burst length is 1.So, in a clock cycle, accomplish the output of read data after, externally outside port is not exported any data in 3 of the instruction cycle clock cycles that stay, this causes invalid data transmission.This problem can be eliminated through the lengthening burst length.

Figure 74 is the figure that is used to explain the principle of the invention, and the indicating impulse string length is 4 example.In this example, as former situation, external command cycle of two outside ports is arranged on the length that 2.2 built-in function cycles can be provided.Further, an external command cycle is corresponding to 4 clock cycles.With time clock synchronously with the data stand-by period is provided is 6 mode single external command in the cycle from an outside port output data 4 times.So,, then in two ports, can both reach gapless read operation, thereby promote the raising of message transmission rate very bigly if burst length is set according to the number of the clock cycle in an external command cycle.In this situation, need the single access of response will with the as many data item of burst length input store array or export internally from memory array.For example, if the data I/O pin number of an outside port be 4 with burst length be 4, then need guarantee through single accessing operation 16 bit data from memory array output or input store array.

We should be noted that the not necessarily synchronously operation of A port and B port; Equal to add the duration that the duration α shorter than the single built-in function cycle needs as long as the minimum period is set, just can independently of each other each external command cycle be arranged on any timing for N built-in function cycle.

Figure 75 and Figure 76 be illustrated in 2,3 and the situation of N port in the figure of relation between a minimum external command cycle and each built-in function cycle.As shown in the figure, if port number is 2, the then minimum external command cycle is to allow the time span of 2 built-in functions to add α, if port number is 3, the then minimum external command cycle is to allow the time span of 3 built-in functions to add α.Further, if port number is N, the time span that the then minimum external command cycle etc. therebetween can be carried out N+1 built-in function adds time span α.

Figure 77 and Figure 78 A are the figure of the configuration of expression multiport memory according to an embodiment of the invention to Figure 78 C.Figure 77 representes DRAM core and interlock circuit thereof, and Figure 78 A representes the A port, and Figure 78 B representes the B port.Further, Figure 78 C representes refresh circuit.Figure 78 A is connected with the each several part of Figure 77 to the circuit shown in Figure 78 C.

Shown in these figure; The multiport memory of present embodiment comprises DRAM core 3011, is used to control confirm order of operation and guarantee the arbiter 3026 with the order implementation and operation of confirming, order register 3025; The instruction that its temporary transient storage provides from arbiter 3026; And these instructions are transferred to the control circuit 3014 of DRAM core 3011, the instruction of temporarily storing each port, many groups register of address and data with the order of receiving them; 2 outside port and refresh circuits of forming by A port 3030 and B port 3,040 3050.

A port 3030 comprises mould register 3031 and 3041 respectively with B port 3040; CLK impact damper 3032 and 3042; Data I/ O circuit 3033 and 3043; Address input circuit 3034 and 3044, and instruction input media 3035 and 3045, they are operated according to the clock frequency of respectively separating that provides from the device outside.Data stand-by period and burst length are stored in mould register 3031 and 3041, they can be provided with respectively.Data I/ O circuit 3033 and 3043 is equipped with according to burst length implements the parallel-to-serial conversion of output/output data and the mechanism of serial-to-parallel conversion.

Refresh circuit 3050 comprises refresh timer 3051 and refreshing instruction generator 3052.Refresh timer 3051 produces on predetermined space and refreshes commencing signal and refreshing instruction generator 3052 produces refreshing instruction accordingly.

The instruction storage that will be added to A port and B port respectively is in order register A 28A and order register B 28B.Store the addresses in respectively among address register A 19A and the address register B 19B, respectively with the data storage that writes in Write data register A 22A and Write data register B 22B.Further, refreshing instruction is stored in the refreshing instruction register 3027, and refresh address is stored in refresh address counter/register 3018.

The order that arbiter 3026 arrives according to instruction is confirmed the order of execution command, and with the order of confirming instruction is transferred to order register 3025.Order register 3025 sends these instructions to the order of receiving instruction from arbiter 3026 control circuit 3014 of DRAM core 3011.When the DRAM core is handled given instruction, make control circuit 3014 be in the state that can receive next instruction.Accordingly, order register 3025 next instructions send control circuit 3014 to.To temporarily be stored in the order register 3025 from the instruction that arbiter 3026 provides simultaneously.Further, order register 3025 also is transferred to corresponding address register and corresponding data register (in the write operation situation) with transmission signals except the control circuit 3014 that instruction is transferred to DRAM core 3011.In DRAM core 3011, the instruction that control circuit 3014 responses provide, control code translator 3013, write amplifier (WriteAmp) 3015 and sense buffer 3016, thus implement accessing operation for memory array 3012.In the situation of write operation; Code translator 3013 is deciphered the address of access in order to carry out write operation; So that activate word line and column signal line in memory array 3012, cause the write data that is stored among Write data register A and the B is passed through WriteAmp 3015 write store arrays 3012.In the situation of read operation, access memory array 3012 in a similar fashion, cause respectively read data being transferred to the data output circuit of each port from sense buffer 3016 through being labeled as transmission gate A and the B of 3024A and 3024B.According to the operating cycle of DRAM core 3011, the transmit timing of control transmission door, and by control circuit 3014 definite transmit timings.Synchronously export output data with corresponding external clock from the data output circuit of each port.

Below, we describe and each instruction process, the detailed situation that address process is relevant with data processing.

Figure 79 is the configuration of relevant device is handled in expression according to the 1st embodiment and instruction figure with Figure 80.On the parts identical with Figure 78 A-78C, add identical reference number with Figure 77.This is applied to other figure too.

Shown in Figure 79; The instruction inputting device 3035 of A port comprises input buffer 3036; Command decoder 3037 and (n-1) clock delay circuit 3038, the instruction inputting device 3045 of B port comprises input buffer 3046, command decoder 3047 and (m-1) clock delay circuit 3048.Here, n and m are burst lengths.And shown in Figure 80, order register A comprises Read order register AR and Write order register AW, and order register B comprises Read order register BR and Write order register BW.

Input buffer 3036 and 3046 requires synchronously to add the Read instruction with each time clock CLKA1 and CLKB1, and command decoder 3037 and 3047 is deciphered processing.Command decoder 3037 and 3047 produces RA1 and RB1 respectively in Read instruction situation, and produces WA1 and WB1 respectively in Write instruction situation.Respectively signal RA1 and RB1 are transferred to Read order register AR and BR; Without any need for fixed cycle operator; And signal WA1 and WB1 are by (n-1) clock delay circuit 3038 and (m-1) clock delay circuit 3048 delays; Till last data item of input pulse string data, then be transferred to Write order register AW and BW respectively.And, will be transferred to refreshing instruction register 3027 by the refreshing instruction REF1 that refresh circuit 3050 produces.

Arbiter 3026 detects instruction is transferred to this 5 order register AR, AW, and BR, BW and 3027 order, and then a ground these instructions are transferred to order register 3025 with one of detected order.When receiving from instruction that arbiter 2026 sends, order register 3025 confirms to be transferred to arbiter 3026 with command reception.Response instruction confirmation of receipt, arbiter 3026 send to order register with next instruction.

Order register 3025 will instruct one to follow the control circuit 3014 that a ground is transferred to DRAM core 3011 with the order of receiving instruction from arbiter 3026.The control circuit 3014 of DRAM core is carried out the instruction of receiving, and carries out the signal that finishes or will be ready to receive instruction during near end when instruction and be transferred to order register 3025.Response is ready to receive the signal of instruction, and order register 3025 is transferred to control circuit 3014 with next instruction.Simultaneously, will temporarily be stored in the order register 3025 from the instruction that arbiter 3026 provides.

Figure 81 is the embodiment of arbiter 3026.The order that instruction arrives 5 order registers (Read order register AR, Write order register AW, Read order register BR, Write order register BW and refreshing instruction register 3027) of Figure 80 detects as shown in the drawing by comparer 3053.Relatively timing of two order registers of each comparer 3053, and at first its output is changed over " H " during input " H ".Whether AND door 3054 all relevant outputs through detecting relevant comparer 3053 are that " H " confirms that whether a given instruction import before all 4 other instructions.If the instruction of a correspondence be the earliest and be transferred to order register 3025, then each instruction of response, signal RA31, WA31, RB31, WB31 and REF31 become " H ".If RA2 is RA2 in the REF2 the earliest, the comparer that then is connected with RA2 have with one side that RA2 is connected on be the output of " H ".In this specific moment, command reception confirms also not produce (=" L "), makes N1=" H ", and causing RA3 is " H ".So instruction is sent to order register 3025.

Order register 3025 produces command reception and confirms when receiving instruction.When this thing happens, produce " L " pulse at node N1, causing RA3 all is " L " to REF3.Simultaneously, with producing ResetRA in the ResetREF.If RA31 is " H ", then produces ResetRA, thereby Read order register AR is resetted.Accordingly, RA2 becomes " L ", so RA31 in the REF31 becomes " H ", and next online instruction in the indication.When " L " pulse does not hold N1 to become " H ", the instruction that the next one is online is transferred to order register 3025.After this repeat above-mentioned operation.

Figure 82 and Figure 83 are the figure of the configuration of presentation directives's register 3025.With order register 3025 in two and be illustrated among two figure.

Order register 3025 mainly comprises shift register 3092; The instruction of shift register 3092 storing therein; These instructions are outputed to DRAM core 3011 continuously, and comprise switch (SW1-SW3) 3082-3084 that the instruction that receives from arbiter 3026 is transferred to shift register 3092.In this example; Shift register 3092 has three grades of configurations; And comprise the register 3085-3087 that is used for storage instruction, the sign 3088-3090 of the store status of indicator register 3085-3087 and the reseting data device 3091 that the state of register 3085-3087 is resetted.Do not having instruction storage in the state of register 3085-3087, sign 3088-3090 is in low state (FL1-FL3=" L "), makes switch 3082 (SW1) connect.Through SW1 with the 1st instruction storage in register 3085, make FL1 become " H ".When FL1 became " H ", " H " edge pulsing circuit 3093 produced pulse, and command reception is confirmed to be transferred to arbiter 3026.

If assert the signal that is ready to receive instruction at this specific moment DRAM core 3011, then door 3097 instruction of opening register 3085 is transferred to latch 3098, then instruction is sent to the control circuit 3014 of DRAM core 3011.Simultaneously, will be transferred to DRAM core 3011 corresponding to address of this instruction etc.DRAM core 3011 cancellation when beginning to operate according to the instruction of receiving is ready to receive the signal of instruction.So door 3097 is closed.The data that 3096 generations of register controlled circuit impel the data of register 3086 to move on to register 3085 and register 3087 move on to the shift signal of register 3086.If before shift signal produces, do not have storage instruction in the register 3086, then shifting function causes making register 3085 to reset and makes FL1 become " L ".Register controlled circuit 3096 produces at the generation shift signal simultaneously forbids transmission signals so that break off SW1-SW3, thereby when shifting function, forbids data are sent to shift register 3092.When through SW1 with the 1st instruction (instruction 1) when being added to register 3085, if DRAM core 3011 is being carried out previous instruction with instruction storage in register 3085.FL1 becomes " H ", and it breaks off SW1, and further behind a predetermined delay, breaks off SW2.Here, predetermined delay with confirm that from producing command reception the time cycle that arbiter output is resetted is corresponding.If before DRAM core 3011 is ready to receive instruction, add next instruction from arbiter 3026 (instruction 2), then through SW2 with instruction storage in register 3086.FL2 becomes " H ", and it produces, and command reception is confirmed and disconnection SW2, then behind a scheduled delay, further breaks off SW3.When the DRAM core is in the state that can receive instruction, produce to prepare receive command signal, open door 3097, make that the instruction 1 with register 3085 is transferred to latch 3098, be transferred to DRAM core 3011 then.DRAM core 3011 cancellation when beginning to operate according to instruction 1 prepares to receive command signal.Correspondingly, door 3097 is closed.Register controlled circuit 3096 produces shift signals, and this shift signal moves on to the instruction 2 of register 3086 register 3085 and the content (reset mode) of register 3087 is moved on to register 3086.The storage of register 3085 END instructions 2, register 3086 and 3087 terminates in reset mode.Because FL1 is " H ", FL2 and FL3 are " L ", break off SW1 and SW3 so connect SW2.

Reseting data device 3091 is connected with register at the shift register 3092 on its left side.The purpose that this configuration is provided is when when instruction all is stored on the whole piece path of register 3087, uses shift signal then that the instruction of register 3087 is moved on to register 3086.In this mode, order register 3025 temporary transient accumulation detect the state of DRAM core 3011 from the instruction that arbiter 3026 sends, and follow transfer instruction one by one.

To instruct and produce detection signal input register control circuit 3096.When from arbiter 3026 transfer instructions, produce instruction and produce detection signal.Figure 84 A and Figure 84 B represent the operation of register controlled circuit 3096.When the preparation to register controlled circuit 3096 receives the command signal deactivation, produce shift signal and forbid transmission signals.Yet during immediately from arbiter 3026 transfer instructions, preferential is only after the instruction that will more early receive is transferred to shift register 3092, just to implement shifting function before just prepare receiving the command signal deactivation.Therefore, compare so that which early in definite forward position of preparing to receive the back edge of command signal and instruct the generation detection signal.If the former early, then responds the former back along producing shift signal and forbidding transmission signals, if the latter early, then responds the back along producing shift signal and forbidding transmission signals of the latter.

Figure 85 and Figure 86 are the figure of presentation directives's register 3025 operations.Here the situation that produces refreshing instruction about the time that Write → the Read instruction is transmitted in the most crowded timing condition of expression input instruction is described.SW1 shown in the figure points out the SW that connects to the number of SW3, and has explained the duration that connects SW.Further, resistance 1 to 3 corresponds respectively to register 3085 to 3087.

Figure 87 is the figure of expression according to the configuration of the 1st embodiment part relevant with address process.Hereinafter, the signal representative that has a letter " P " at its not end of signal name has the signal of the pulse that produces from the forward position of the signal of the signal name of correspondence.As shown in the figure, address input circuit 3034 and 3044 comprises input buffer 3057A and 3057B respectively, transmission gate 3058A and 3058B.Further, address register 3019A and address register 3019B comprise respectively address latch A1 to A4 and B1 to B4, transmission gate 3059A to 3063A and 3059B to 3063B.Will be through address bus 3017 from transmission gate 3062A, 3062B, the address transfer that 3063A, 3063B provide is to DRAM core 3011.Further, will be transferred to DRAM core 3011 from the refresh address that refresh address counter/register 3018 provides through transmission gate 3064 and address bus 3017.

When from the outside input of device Read instruction or Write instruction, the address and the input instruction that will be added to input buffer 3057A or 3057B through transmission gate 3058A or 3058B respectively are transferred to address latch A1 or B1 simultaneously.In the situation of Read instruction, through transmission gate 3061A and 3063A or 3061B and 3063B and address latch A4 or B4 and to the instruction transmitting synchronous of DRAM core send the address to DRAM core 3011.In the situation of Write instruction, further give address latch A2 or B2 with address transfer in the timing of data acquisition last time, then, with to the instruction transmitting synchronous of DRAM core be transferred to DRAM core 3011 through transmission gate 3062A or 3062B.Further, refresh address counter/register 3018 produces and preserves therein refresh address, gives DRAM core 3011 through transmission gate 3064 with this address transfer to the transmitting synchronous ground of DRAM core with refreshing instruction then.

Figure 88 is the figure of expression according to the configuration of the 1st embodiment part relevant with data output.Figure 89 is the figure of the transmission signals generation circuit of expression Figure 88.Each data I/ O circuit 3033 and 3043 of A end 3030 and B port 3040 comprises respectively for the circuit 3065A of output data and 3065B and reaching in order to import the circuit 3074A and the 3074B of data.As shown in the figure, will be transferred to circuit 3065A or 3065B through data bus 3021 respectively with transmission gate 3024A or 3024B through the data that sense buffer 3016 is read from memory array 3012 for output data.

For the circuit 3065A and the 3065B of output data comprises data latches A1 or B1 respectively; Transmission signals generation circuit 3067A and 3067B, transmission gate 3068A or 3068B, data latches A2 or B2; Parallel-to- serial transducer 3070A and 3070B, and output buffer 3071A and 3071B.

Transmission gate 3024A and 3024B are controlled according to built-in function by the control circuit of DRAM core 3,011 3014.If the instruction of carrying out is Read-A (that is, for the read operation of A port), then transmission gate 3024A will open.If the instruction of carrying out is Read-B, then transmission gate 3024B will open.Data latches A1 or B1 storing therein data receive the scheduled wait time after Read instructs then in each port of introducing the stand-by period through transmission gate 3068A and 3068B, give each data latches A2 or B2 with data transmission.Then, data are carried out conversion, then be transferred to output buffer 3071A and 3071B respectively by parallel-to- serial transducer 3070A and 3070B, and output therefrom.

Shown in Figure 89, transmission signals generation circuit 3067 (being 3067A or 2067B) adopts a series of trigger 3072 to make each Read instruction RA1 or RB1 postpone to set many clock cycles of confirming by the stand-by period, thereby produces data transfer signal 3002.Because response data transmission signals 3002, through transmission gate 3068A and 3068B transmission read data, so read data begins to be postponed and finishes after the stand-by period is provided with identical many clock cycles from the timing of read operation.

Figure 90 is the figure of expression according to the configuration of the present embodiment part relevant with the data input with Figure 91.For circuit 3074A and the 3074B that imports data comprises data input (Din) impact damper 3075A and 3075B, serial-to- parallel transducer 3076A and 3076B, and data transmission device 3077A and 3077B respectively.Respectively through the 1st Write data register 3078A and 3078B; Data transfer gate 3079A and 3079B; The 2nd Write data register 3080A and 3080B; Data transfer gate 3081A and 3081B, and data bus 3021 will send WriteAmp 3015 to from Write data W DA and the WDB of data transmission device 3077A and 3077B, be written into memory array 3012 then.

According to burst length with serial input data from serial converted to parallel, the timing in last data item of input is transferred to the 1st Write register 3078A and 3078B then.When order register 3025 is transferred to DRAM core 3011 with Write instruction, also corresponding data is transferred to DRAM core 3011.

Figure 92 is the timing diagram of operation of the multiport memory of expression the 1st embodiment to Figure 99.Figure 92 and Figure 93, Figure 95 and Figure 96, Figure 98 and Figure 99 be for the ease of for the purpose of the explanation with single time diagram figure in two, the 1st of an express time figure is half the, the 2nd of another express time figure is half the, exists some overlapping between them.

Figure 92 and Figure 93 represent the operation when two ports are imported in Read instruction in succession, implemented.A port and B port, they have respectively mutual clock signals of different frequencies CLKA and CLKB are arranged, synchronously get instruction with the clock signal that receives, address and write data, and synchronously export data retrieved with clock signal.In this example, the A port operation is at maximum clock frequency, and the B port operation is in low slightly clock frequency.For the A port, Read instruction cycle=4 (CLKA), data stand-by period=6 (CLKA), and burst length=4.For the B port, Read instruction cycle=2 (CLKB), data stand-by period=3 (CLKB), and burst length=2.In the mould register 3031 and 3041 of each port, data stand-by period and burst length are set respectively.For the A port, respond the I/O 4 times that an instruction and clock signal are synchronously implemented data, export data retrieved 6 clock cycles after input reads instruction.For the B port, respond the I/O 2 times that an instruction and clock signal are synchronously implemented data, export data retrieved 3 clock cycles after input reads instruction.

The instruction storage that will be added to A port and B port respectively is in order register 3028A and 3028B.When refresh timer 3051 produces signal, refreshing instruction register 3027 storing therein refreshing instructions.Arbiter 3026 is kept watch on these order registers, and with the order that sends instruction these instructions is transferred to order register 3025.Order register 3025 is temporarily stored the instructions that receive, and with the order of receiving them they is transferred to DRAM core 3011 continuously.That is, on accomplishing, transmit next instruction after the processing of a transfer instruction.

As shown in the figure, will instruct Read-A2 input Read order register AR and will instruct Read-B2 to import Read order register BR.Before this, take place once to refresh, and refreshing instruction is imported the refreshing instruction register.According to the order that sends instruction, arbiter 3026 is transferred to DRAM core 3011 with the order of Read-A2 → Ref → Read-B2 with these instructions, carries out these instructions by core then.

Because there is extra time in operating between Read-B1 and the Read-A2 of core, and all implement normal and the routine operation up to this point.When refreshing, behind Read-A2, implement immediately to refresh and have no the time slot betwixt.After this, implement Read-B2 in succession, Read-A3 etc. and have no the time slot up to carrying out Read-A5.With normal opposite, all carry out operation fast up to this point with the routine operation.

Because the execution of refreshing instruction, built-in function is with respect to outside instruction input demonstrates some delays from device.The operation compensation should postpone fast, before execution command Read-A5, caught up with.Between Read-A5 and Read-B5, there is extra time once more, points out to get back to normal and the routine operation.To be transferred to the data latches (data latches A1 or B1) of the port that receives corresponding Read instruction through the data that sense buffer 3016 is read from DRAM core 3011 through transmission gate.Data latches A1 or B1 are that data provide time adjustment, give data latches A2 or B2 with data transmission then, and with the clock signal of corresponding port output data synchronously.

Even when at the internal implementation refresh operation, it seems that from the outside data export after the stand-by period a tentation data.Like this, just need not consider any refresh operation.

Figure 94 representes the example when the input of adjoining land under condition same as described above Write instruction.The data of importing from the device outside when form of also importing with train of impulses is given in the Write operation.The input last data block timing with the Write instruction storage in Write order register AW.In this situation, even when producing in inside and carrying out refresh operation, need not consider any refresh operation yet.

Figure 95 and Figure 96 represent to operate in the operation of implementing when carrying out the Read operation on the maximum clock frequency as A port and B port both.Figure 97 to be expression carry out Write operation of enforcement when operating when A port and B port both operate on the maximum clock frequency figure.In this situation, in the clock pulse signal of these two ports, possibly there is phase differential.For two ports, Read instruction cycle=4, Write instruction cycle=4, data stand-by period=6, and burst length=4.As from scheme visible, also implementation and operation suitably in this situation.

Figure 98 and Figure 99 are that expression be operating in highest frequency when two ports, and the time diagram of the operation of implementing when standing from the Write write command to change that Read reads instruction with the refreshing instruction of inner generation.This is to instruct the most crowded situation.

As illustrated, DRAM core 3011 is operated with the order of Ref → Write-A1 → Write-B1 → Read-A2 → Read-B2, between them, has no the gap.In this example, instruct back 6 time clock to import Read-A2 and Read-B2 at input Write.Even if 2 time clock of these timing advances, the also built-in function of DRAM core in advance.By the output of read data regularly being controlled from the data stand-by period of input Read instruction.If the incoming timing of Read-A2 and Read-B2 is leading, then also need make data output is leading regularly.For example, if 4 time clock are imported Read-B2 behind Write-B1, the data output that then responds Read-B2 makes and can not suitably carry out Read-B2 regularly too near the start time of DRAM core operation.Because this reason need be provided with the command interval of Write → Read transition quite longly like 6 time clock in this example.

About the command interval of Read → Write, only if because accomplished the output of Read data, can not be with in the Write data inputs DQ terminal, so that command interval becomes inevitably is very long.

Figure 100 A and 100B are the timing diagrams of expression DRAM core 3011 operations.Figure 100 A representes the Read operation, and Figure 100 B representes the Write operation.Shown in these figure, respond single instruction and amplify → write back → precharge order enforcement sequence of operations, thereby accomplish whole operation with word line selection → data.Make and prepare to receive the command signal deactivation when receiving when instruction DRAM core 3011, and prepare the reception command signal when accomplishing or producing during near the execution of END instruction.

As stated, the present invention allows when being basis use multiport memory and need not consider any refresh operation when processing memory array with the DRAM core, thereby provides high capacity and easy-to-use multiport memory with low cost.

[the 4th aspect of the present invention]

Below we describe the 4th aspect of the present invention.

Multiport memory, they are the semiconductor memories that are equipped with a plurality of ports, can be divided into different types.When hereinafter using a technical term " multiport memory ", it refers to the storer with multiport, and this storer allows from any one port access common memory array independently.Such storer can have A port and B port, and allows for common memory array from carrying out read/write operation independently with the CPU of A port link with from the CPU with the B port link.

A multiport memory is equipped with the arbiter that is called arbiter.Arbiter is confirmed the right of priority that requires from the access that a plurality of ports receive, the control circuit of memory array according to the right of priority of confirming one by one carry out accessing operation.For example, access requires more early to arrive port, will give this access requirement high more right of priority.

In this situation, because randomly from a plurality of interface access memory array, thus after having carried out the accessing operation that reads or writes, need memory array be resetted, thus guarantee that memory array classifies access next time as and get ready.Promptly; If response requires to make a word line remain on selection mode from the access of given port; With as in the row accessing operation that in DRAM, uses such continuous earthquake move each column address so that read continuous data, then the access from another port requires and will wait for always when this operating period.Therefore, after each read or write, need memory array be resetted.

Routinely, typically with the memory array of SRAM as multiport memory.This is because SRAM allows high random access, and can carry out the non-destructive read operation.

In multiport memory with two ports, for example, SRAM storage unit have two groups of word lines and bit line right.Port with one group of word line and bit line to implementing read/write operation, another port with another group word line and bit line to the enforcement read/write operation.In this mode, can implement read/write operation independently from two different ports.Yet,, carry out the right of priority of write operation so give a port, and give another port BUSY (having much to do) signal because when two port attempts write same storage unit with data at one time, can not carry out two write operations simultaneously.This is called the BUSY state.

When development system makes it that the performance of improvement arranged, also increased by the data volume of this system handles.As a result, multiport memory needs very big capacity.Yet SRAM type multiport memory has the big shortcoming of size of storage unit.

In order to eliminate this shortcoming, it is understandable in multiport memory, adopting the DRAM array.In order to obtain to be used for DRAM storage unit of multiport memory and only to be connected with a bit lines with a word line with the mode identical with typical DRAM unit than the high current densities of Duoing very much that gets of multi-port SRAM.If process storage block with the DRAM element in such a way, if a port is carried out read or write to given storage block, then another port can not this storage block of access.This be because in the DRAM storage unit only so that destructive read operation to be arranged.That is, when reading information, another word line that can not be chosen in the same storage block is exaggerated and is stored in the storage unit up to this information, word line and bit line by pre-charge till.

Have only when a plurality of ports simultaneously same storage unit to be proposed to write when requiring, in the SRAM of routine type multiport memory, just the BUSY state can occur.Therefore, DRAM type multiport memory need have the different BUSY State Control function of a SRAM type multiport memory uniqueness and routine.

Further, different with SRAM type multiport memory, DRAM type multiport memory need be implemented refresh operation periodically so that keep canned data, thereby must take certain measure to guarantee suitable refresh timing.

Therefore, the purpose of this invention is to provide the DRAM type multiport memory that to eliminate special relevant problem with DRAM.

According to the present invention; Semiconductor storage unit comprises a plurality of N outside port, and each in them all receives instruction, a plurality of N bar buses corresponding with each outside port; A plurality of storage blocks that are connected with N bar bus; Compare address comparator by the address of the instruction accessing that is input to N each outside port, and arbiter, it is confirmed when the address comparator circuit relatively detects the access of same storage block according to the address; The same storage block of access each the instruction in which or which to be performed and the same storage block of access each the instruction in which or which be not performed.

Among the present invention who describes in the above, if during from the same storage block of instruction attempt access of device external input port, arbiter confirm that in each instruction which will be performed and each instruction in which be not performed.For example, comparison order is regularly carried out instruction early, and does not carry out other one or more instructions.When having the instruction that is not performed, generation BUSY signal etc. also output to the device outside.This makes even when instruction accessing clashes each other in the multiport memory that is the basis with the DRAM core, also can implement suitable accessing operation and realize suitable BUSY control.

According to an aspect of the present invention, storage block is included in the memory cell array of processing on the basis of dynamic type storage unit, and semiconductor storage unit comprises the refresh circuit of the timing that defines refresh of memory cells.In first pattern, response is input to the refreshing instruction refresh of memory cells of N at least one port in the outside port, in second pattern, and the periodic refreshing storage unit of pointing out at refresh circuit.

Above-described the present invention has an operator scheme, wherein responds the operator scheme of carrying out refresh operation from the instruction of internal refresh circuitry from the operator scheme and the response of the outside instruction execution refresh operation of device.This makes in a kind of like this mode; Predetermined outside port specifies and is used for receiving at constant interval the port that refreshing instruction refreshes management as one and becomes possibility with multiport memory; Perhaps make in a kind of like this mode, promptly internal refresh circuitry begins to become possibility with multiport memory in the refresh operation when all outside ring portion ports all are in deactivation status.Therefore, the present invention provides the foundation for the management that refreshes flexibly that compliance system requires.

Below we will describe the present invention's (the 4th aspect) embodiment with reference to appended each figure.

Figure 101 is the block scheme of expression according to the embodiment of multiport memory of the present invention.In this example, configuration is such, and two ports promptly are provided, A port and B port.

The multiport memory 4010 of Figure 101 comprises A port 4011, B port 4012, self-refresh circuit 4013; Storage block 4014-1 is to 4014-n, arbiter 4015, refresh address counter 4016; Address modification circuit 4017; Address modification circuit 4018, address comparator 4019, bus A 4020-1 and bus B 4020-2.

A port 4011 comprises mould register 4031, CLK impact damper 4032, data I/O circuit 4033, instruction decode register 4034, address buffer/register 4035 and BUSY signal I/O device 4036.Further, B port 4012 comprises mould register 4041, CLK impact damper 4042, data I/O circuit 4043, instruction decode register 4044, address buffer/register 4045 and BUSY signal I/O device 4046.At A port 4011 and B port 4012, synchronously be established to the access of external bus independently with each clock signal clk A and CLKB and from the access of external bus.Mould register 4031 and 4041 can storing therein for mode initialization such as the data stand-by period and the burst length of each port.In this embodiment, A port 4011 has mould register separately with B port 4012 boths, makes each port can both carry out mode initialization.Yet, can the mould register only be arranged in the port, for example, making can be by this setting of ports is realized for 2 setting of ports.

Self-refresh circuit 4013 comprises refresh timer 4046 and refreshing instruction generator 4047.Self-refresh circuit 4013 produces refreshing instruction in device, receive signal CKEA1 and CKEB1 from A port 4011 and B port 4012 respectively.Signal CKEA1 and CKEB1 cushion with CLK impact damper 4032 and the 4042 couples of external signal CKEA and CKEB respectively and obtain.Suspend the clock buffer of each port and make each port deactivation with external signal CKEA and CKEB.If make A port 4011 and B port 4012 boths get into deactivation status, then self-refresh circuit 4013 its operations of beginning.

Each all is connected with internal bus B 4020-2 with internal bus A 4020-1 storage block 4014-1 to 4014-n.There are a plurality of outside ports (promptly; A port and B port); Wherein A port 4011 passes through bus A 4020-2 and storage block 4014-1 each interface in the 4014-n through bus A 4020-1 and storage block 4014-1 each interface and B port 4012 in the 4014-n.

If import at the same time that access from A port 4011 requires and from the access requirement of B port 4012; Suppose that then these access requirements are to point to different storage blocks, accessed memory blocks just requires to implement independently their operation corresponding to these accesses.

If requiring and require from the access of B port 4012 from the access of A port 4011 is to point to same storage block, then arbiter (arbiter) 4015 is confirmed the order that instruction arrives, and carries out the instruction of the 1st arrival and delete the instruction of the 2nd arrival.When delete instruction, arbiter 4015 produces the BUSY signal so that the notice peripheral control unit has been deleted the access requirement of the instruction of the 2nd arrival.

Address comparator 4019 confirms whether the access of two ports of entering points to same storage block in requiring.Detailed says, the piece that address comparator 4019 relatively is included in the address that gets into two ports is selected the address.If they are identical, then matched signal is added to arbiter 4015.

When A port 4011 or B port 4012 are in state of activation, from A port 4011 and B port 4012 input refreshing instructions.

If the same storage block of refreshing instruction access that gets into a port in two ports as be input to two another ports in the port read instruction or write command did, then arbiter 4015 was confirmed the order that instruction arrives.If refreshing instruction is more late than other instruction, then cancel refreshing instruction.In this situation, arbiter 4015 produces the BUSY signal, and it is added to the device outside.When detecting the BUSY signal, peripheral control unit provides refreshing instruction to multiport memory 4010 once more after cutting off the BUSY signal.

If refreshing instruction is more Zao than other instruction, perhaps the self-refresh instruction is provided from self-refresh circuit 4013, then arbiter 4015 produces count signal, and it is added to refresh address counter 4016.

Refresh address counter 4016 response count signals are counted the address, thereby produce refresh address.Need provide the reason of count signal to be because refreshing instruction can be cancelled as stated from arbiter 4015, carry out from the arbiter 4015 actual refreshing instructions that send so counting operation should only respond.Here, implementing to implement counting operation behind the refresh operation.

If be input to the instruction of A port 4011 and be Read instruction (sense order) or Write instruction (writing instruction), then address modification circuit 4017 will be input to A port 4011 from the outside address transfer to bus A 4020-1.If being input to the instruction of A port 4011 is refreshing instructions, then will give bus A 4020-1 by the address transfer that refresh address counter 4016 produces.

If be input to the instruction of B port 4012 and be Read instruction (sense order) or Write instruction (writing instruction), then address modification circuit 4018 will be input to B port 4012 from the outside address transfer to bus B 4020-2.On the other hand, are refreshing instructions if be input to the instruction of B port 4012, then will give bus B 4020-2 by the address transfer that refresh address counter 4016 produces.

As stated, if A port 4011 is in base state alive with B port 4012 boths, then self-refresh circuit 4013 is according to the timing signal for generating refreshing instruction of the refresh timer that provides as internal circuit 4046.In this embodiment, through bus A 4020-1 self-refresh instruction and refresh address are transferred to storage block 4014-1 to 4014-n.Because self-refresh not with the instruction conflict of A port 4011 and B port 4012, so do not need arbiter 4015 priority resolutions.Yet,, also the self-refresh instruction is offered arbiter 4015 because need produce count signal by arbiter 4015.

Figure 102 is the timing diagram of expression according to an example of multiport memory 4010 operations of the present invention.

Instruction Read-x is the Read instruction of pointing to storage block 4014-(x+1).At first Read-0 is input to A port 4011, then Read-3 is input to B port 4012.In this situation, the storage block of access is different, makes storage block 4014-1 and storage block 4014-4 operate concurrently.

After this, Read-1 is input to A port 4011, then Read-1 is input to B port 4012.Because the storage block of access is identical in this situation, so produce matched signal, cancellation is input to the instruction of B port 4012.And, from the BUSY signal I/O device 4046 output BUSY-B (negative logic value) of B port 4012.

The peripheral control unit of B port 4012 detects BUSY-B, after cutting off this signal, to multiport memory 4010 Read-1 is provided once more.

Figure 103 is the timing diagram of expression according to another example of multiport memory 4010 operations of the present invention.

Operation shown in Figure 103 is up to the 2nd instruction Read-1 input A port 4011 and B port 4012, produces till the BUSY-B all identical with Figure 102.In this example, after BUSY-B takes place in the Read-1 that response is input to B port 4012, for another storage block entering of access before BUSY-B finishes Read-2 that reads instruction.In this mode, if next instruction be point to another storage block in addition in the cycle of assert BUSY, also can import next instruction.

Figure 104 is the timing diagram of expression according to another example of multiport memory 4010 operations of the present invention.

The example of Figure 104 representes to import the situation of Write instruction.With Read instruction input A port 4011, then with Write instruction input B port 4012.

In this embodiment, I/O data are pulse serial types.That is, through reading parallel data, and when data are exported, in data I/ O circuit 4033 and 4043, it is transformed into serial data and obtains data output from a plurality of column addresss.The input of serial ground input data is transformed into parallel data with it then in data I/ O circuit 4033 and 4043, then parallel data is write in a plurality of column addresss of associated storage piece.Use this train of impulses operation can increase message transmission rate.In this example, burst length is 4, makes 4 data item of output/input continuously.

In the situation of Write operation,, otherwise can not begin the Write operation only if import 4 all data item.So arbiter 4015 can confirm that the timing of the right of priority of Write operation is last the timing that provides a series of serial datas inputs.

In Figure 104, the 2nd the same storage block of instruction input Write-3 attempt access of Read-3 and B port 4012 imported in the 3rd instruction of A port 4011.Though the Write-3 of B port 4012 has provided the Read-3 of A port 4011 according to instructing the incoming timing of each port to import the front in other instruction before last entering of write data.Therefore, the instruction that arbiter 4015 is confirmed A port 4011 is in the front of other instruction, and the instruction of cancellation B port 4012.

Shown in Figure 101, A port 4011 has CLK impact damper 4032 and 4042 respectively with B port 4012, and from the outside different clock signals that receives of device.Each clock signal can have identical or different phase place and frequency.

Figure 105 is the block scheme of presentation directives's code translator register 4034 and 4044.

Command decoder register 4034 comprises input buffer 4061, command decoder 4062 and (n-1) clock delay circuit 4063.Command decoder register 4044 comprises input buffer 4071, command decoder 4072 and (n-1) clock delay circuit 4073.

If be input to the instruction of input buffer 4061 or 4071 and be the Read instruction (RA1, RB1) or refreshing instruction (REFA REFB), is transferred to arbiter 4015 and without any need for fixed cycle operator through command decoder 4062 or 4072 with input instruction.(input instruction is postponed (n-1) individual clock period by (n-1) clock delay circuit 4063 or 4073 for WA1, situation WB1), writes the timing of n the last data item of input and is transferred to arbiter 4015 providing a series of train of impulses in Write instruction.

Figure 106 is the block scheme of arbiter 4015 according to an embodiment of the invention.

Arbiter 4015 comprises register 4081, delay circuit 4082, transmission gate 4083; Register 4084, register 4085, delay circuit 4086; Transmission gate 4087, register 4088, NOR circuit 4091 and 4092; NAND circuit 4093 to 4096, phase inverter 4097 to 4101 is with NOR circuit 4102 and 4103.

To be stored in respectively register 4081 or 4085 from the instruction that instruction decode register 4034 or 4044 transmits.In the time will instructing input to give A port 4011, produce the HIGH signal at the node N1 that is the output terminal of phase inverter 4097.In the time will instructing input to give B port 4012, produce the HIGH signal at the node N2 that is the output terminal of phase inverter 4100.Early one in the signal of the signal of N1 or N2 is latched among node N3 or the N4.

If piece selects the address not match between A port 4011 and B port 4012, then address comparator 4019 is produced as the matched signal of LOW.So, in this situation, N5 and N6 are arranged on HIGH.Respond these HIGH signals, transmission gate A 4083 and transmission gate B 4087 boths open, and the instruction with register 4081 and 4085 is transferred to register 4084 and 4088 unlimitedly.

If piece is selected matching addresses between A port 4011 and B port 4012, then address comparator 4019 is produced as the matched signal of HIGH.So, in this situation, receive control in the signal level of node N3 and N4 in the signal level of node N5 and N6.If A port 4011 early then is arranged on HIGH with N5, N6 is arranged on LOW.The HIGH state of response N5, transmission gate A 4083 opens, and the instruction of A port 4011 is transferred to register 4084.Further, the LOW state of N6 is closed transmission gate B 4087, and the instruction with B port 4012 is not transferred to register 4088.

And, according to the signal level of N5 and N6, produce reset signal BUSY1-A and BUSY1-B, each register 4081 and 4085 is resetted.For example, if select the instruction of A port 4011, then produce BUSY1-B and register 4085 is resetted.

Need not confirm the right of priority of self-refresh instruction, the self-refresh instruction and the refreshing instruction REFA of A port 4011 combined in the output stage of register 4084.The refreshing instruction signal REFA2 that in this mode, produces for A port 4011 and the refreshing instruction signal REFB2 of B port 4012 combine so that produce count signal.The generation of response refreshing instruction offers refresh address counter 4016 from arbiter 4015 with count signal.

Figure 107 is the timing diagram of expression arbiter 4015 operations.

Figure 107 is illustrated in piece between A port 4011 and the B port 4012 and selects the Read instruction RB1 Zao situation of the Read instruction RA1 of matching addresses and A port 4011 than B port 4012.In mode same as described above, the signal level of node N5 and N6 receives the control of the signal level of node N3 and N4, and the signal level of node N3 and N4 reflects the signal level of node N1 and N2, and transfers out Read instruction RA2 from arbiter 4015.The Read of cancellation B port 4012 instructs and does not export, and produces the BUSY1-B signal.

Figure 108 is the block scheme of address buffer/register and address modification circuit.

In Figure 108, the not end that has at signal name (for example RA1) adds that the signal of the signal name (for example RA1P) of letter " P " is to produce pulse through the lead edge timing at the signal with back signal name (for example RA1) to produce.

Address buffer/the register 4035 of A port 4011 comprises input buffer 4035-1, transmission gate 4035-2 and OR circuit 4035-3.The signal RA1 that reads instruction for from 4062 outputs of the command decoder shown in Figure 105 changes the forward position into pulse, produces pulse signal RA1P, then it is added to the input end of OR circuit 4035-3.Write command signal WA1 for from 4062 outputs of the command decoder shown in Figure 105 changes the forward position into pulse, produces pulse signal WA1P, then it is added to another input end of OR circuit 4035-3.The output of OR circuit 4035-3 is added to transmission gate 4035-2 as the transmission phasing signal that sends the instruction of carrying out data transmission.

Address buffer/the register 4045 of B port 4012 comprises input buffer 4045-1, transmission gate 4045-2 and OR circuit 4045-3.Identical for the configuration of the address buffer/register 4045 of B port 4012 with configuration for the address buffer/register 4035 of A port 4011.

Address modification circuit 4017 comprises address latch 4017-1, transmission gate 4017-2 and 4017-3, and address latch 4017-4 is with OR circuit 4017-5 and 4017-6.OR circuit 4017-5 receives signal RA1P and WAD1P, and its output is added to transmission gate 4017-2 as the transmission indicator signal.OR circuit 4017-6 receives signal REFAP and SR-AP, and its output is added to transmission gate 4017-3 as the transmission indicator signal.

Address modification circuit 4018 comprises address latch 4018-1, transmission gate 4018-2 and 4018-3, and address latch 4018-4 is with OR circuit 4018-5.OR circuit 4018-5 receives signal RB1P and WBD1P, and its output is added to transmission gate 4018-3 as the transmission indicator signal.Again signal REFBP is added to transmission gate 4018-2 as the transmission indicator signal.

When from the outside input of device Read instruction or Write instruction, give address modification circuit 4017 or 4018 with the address transfer that and instruction is imported together.In the situation of Read instruction, instruction is transferred to address latch 4017-4 or 4018-4 and without any need for fixed cycle operator.In the situation of Write instruction, instruction is transferred to address latch 4017-4 or 4018-4 in last the timing that obtains a series of write datas inputs.

In the situation of refreshing instruction, at signal REFA, the timing of REFB or ER-A will be transferred to address latch 4017-4 or 4018-4 by the refresh address that refresh address counter 4016 produces.

Figure 109 is the block scheme of storage block.

Figure 109 representes that storage block 4014-1 is as the example of storage block 4014-1 to 4014-n.Storage block 4014-1 has identical configuration to 4014-n.

Storage block 4014-1 comprises memory array 4111, control circuit 4112, bus selector 4113 and 4114, sensor amplifier impact damper 4115 and write amplifier 4116.Memory array 4111 comprises the DRAM storage unit, the gate memory cell transistor, and word line, bit line, sensor amplifier, alignment, row door etc., and storage is used for the data of read operation and write operation.The operation of control circuit 4112 control store piece 4014-1.The data that write amplifier 4116 amplifies write store array 4111.Sense buffer 4115 amplifies the data of reading from memory array 4111.

Control circuit 4112 is connected with bus B 4020-2 with bus A 4020-1, and response selects the address to be selected with the corresponding relevant storage block of its storage block.When selecting, control circuit 4112 selects a bus of address to get instruction from sending relevant storage block.If obtained bus A 4020-1 instruction, then control bus selector switch 4113 makes it send the address signal of bus A 4020-1 to memory array 4111.Further, control bus selector switch 4114 makes it that the data line of sense buffer 4115 or write amplifier 4116 and bus A 4020-1 is coupled together.If obtained bus B 4020-2 instruction, then control bus selector switch 4113 makes it send the address signal of bus B 4020-2 to memory array 4111.Further, control bus selector switch 4114 makes it that the data line of sense buffer 4115 or write amplifier 4116 and bus B 4020-2 is coupled together.If the instruction that control circuit 4112 is obtained is a refreshing instruction, then bus selector 4114 does not need operation.

Select a bus as stated, then, as a series of continued operation, implement word line continuously and select, memory cell data is amplified, perhaps Read, Write or Refresh (refreshing), and precharge operation.

Figure 110 A and 110B are the timing diagrams of expression storage block operation.

Figure 110 A representes the situation of read operation, and Figure 110 B representes the situation of write operation.In operation timing shown in Figure 110 A and the 110B, respond single instruction and implement the word line selection, data are amplified, and perhaps read operation or write operation write back (data recovery) operation and precharge operation, thereby accomplish the operation that requires.

In the present invention (aspect the 4th), if from the same storage block of the instruction of device external input port attempt access, then arbiter confirm that in each instruction which will be performed and each instruction in which be not performed.For example, comparison order is regularly carried out instruction early, and does not carry out (respectively) other instruction.When having an instruction that is not performed, generation BUSY signal etc. also output to the device outside.This makes even when instruction accessing clashes each other in the multiport memory that is the basis with the DRAM core, also can implement suitable accessing operation and realize suitable BUSY control.

Further, the present invention has and is used to respond from device outside instruction and implements the operator scheme of refresh operation and be used to respond the operator scheme of implementing refresh operation from the instruction of internal refresh circuitry.This makes in a kind of like this mode; Predetermined outside port specifies as being used for receiving at constant interval the port that refreshing instruction refreshes management and becomes possibility with multiport memory; Make perhaps that in a kind of like this mode promptly internal refresh circuitry begins to become possibility with multiport memory in the refresh operation when all outside ring portion ports all are in deactivation status.Therefore, the present invention provides the foundation for the management that refreshes flexibly that compliance system requires.

[the 5th aspect of the present invention]

Below we describe the 5th aspect of the present invention.

Multiport memory has two or more sets input/output terminals (that is, a plurality of input/output end ports), and the corresponding storage operation of signal of implementing and receiving.Different with common storer, can carry out read operation and write operation simultaneously.For example, if there is multiple bus in the system,, then, the input/output end port of multiport memory and each bar bus can process this system through being coupled together if a plurality of controller (CPU etc.) needs with each bar bus.This has just eliminated the needs of the control logic circuit (fifo logic circuit etc.) with particular design.

And we also are developed to video memory (being generally the dual-port reporting memory) with a plurality of port stores.Video memory has random-access port, through these ports can be implemented to any storage unit access and with the serial access port of display device swap data.

The a plurality of port stores of this type adopt SRAM storage core or DRAM storage core in memory cell region.

Yet we also must the such multiport memory of exploitation, they be received in each input/output end port the different clocks signal and with clock signal memory cell region of access randomly synchronously.That is our multiport memory of also not knowing how to process the details of circuit and how to control this clock synchronization.

And conventional multiport memory (dual-ported memory particularly) has bit line and the sensor amplifier of organizing input/output end port respectively for each.Because this reason exists the layout dimension of storage core to become big, thereby undesirably increases the problem of the chip size of multiport memory.

Therefore, the purpose of this invention is to provide the multiport memory that permission can be carried out random-access clock synchronization.

The objective of the invention is further to be provided at and respectively organize input/output end port and receive mutual different clock signals, and the multiport memory of operating with reliable mode.

And the purpose of this invention is to provide and irrespectively to be received in the multiport memory that command signal any time drives the storage core through the state of input/output end port with other.

And the purpose of this invention is to provide the little multiport memory of chip size with minimizing.

According to the present invention (the 5th aspect), some in a plurality of storage cores are at the basic enterprising line operate of clock signal that is added to a plurality of input/output end ports and address signal.Each input/output end port comprises the clock terminal that is used for the receive clock signal, is used to the data input/output end port terminal that receives the address terminal of the address signal that synchronously provides with clock signal and be used for the I/O data-signal.For each storage core provides control circuit.

If address signal indication is added to two or more input/output end ports with same storage core, then control circuit address signal that the response of storage core is at first received is operated.That is, implement storage operation for the input/output end port of receiver address signal at first.Can so define the storage core, make it suitable with each sense amplifier region, wherein sense amplifier region is the zone that each sense amplifier region is operated therein together.Select the storage core by the top of address signal.Select the storage unit of storage core by the lower part of address signal.Through inputing or outputing and the corresponding input/output end port of at first receiving in address signal top with the corresponding input/output end port of at first receiving in address signal top, it is outside or from the outside output of device that the data-signal of the storage unit that will be selected by the lower part of address signal is input to device.

Because the whole things that will do be exactly the compare address signal, so can control circuit be processed simple circuit.This reduces chip size.

Because each input/output end port all has clock terminal, so for each input/output end port frequency of control clock signal respectively.That is, a plurality of controllers and multiport memory with different operating frequency are coupled together.

In multiport memory of the present invention, arrange address signal along preceding predetermined set time in the certain edges thereof of the clock signal that is used to obtain address signal.Control circuit is used in this certain edges thereof of clock signal and confirms the order that address signal arrives along the address signal of preceding arrangement.Therefore, can confirm the order that address signal arrives in enough at first edges of the clock signal of reception.This makes before the storage core begins to operate can discern the input/output end port with right of priority, thereby realizes the high speed storing operation.Because at predetermined regularly (being the clock edges of signals) compare address signal, thus can prevent with the mistake of the irrelevant address signal of storage operation relatively.

According to the present invention, some in a plurality of storage cores are at the basic enterprising line operate of clock signal that is added to a plurality of input/output end ports and address signal.Each input/output end port comprises the clock terminal that is used for the receive clock signal, is used to the data input/output end port terminal that receives the address terminal of the address signal that synchronously provides with clock signal and be used for the I/O data-signal.For each storage core provides control circuit.

If will indicate the address signal of same storage core to be added to two or more input/output end ports, then control circuit address signal that storage core response is at first received is operated.After this, control circuit makes storage core response address signal operate with the order of receiver address signal.Select the storage core by the top of address signal.Select the storage unit of storage core by the lower part of address signal.Through the input/output end port corresponding with each address signal, the data-signal of the data-signal of the storage unit of being selected by the address signal lower part from the outside input of device continuously or the storage unit that will be selected by the address signal lower part outputs to the device outside.Therefore, the input/output end port that requires for all reception storage operations is not implemented storage operation exceptionally.

That is, multiport memory all is in stand-by state in institute is free.The controller that is connected with multiport memory not necessarily will detect the busy condition of multiport memory.This has simplified the operation of controller through hardware and software.Because the whole things that will do be exactly the compare address signal, so can control circuit be processed simple circuit.This reduces chip size.

Because each input/output end port all has clock terminal, so for each input/output end port frequency of control clock signal respectively.That is, a plurality of controllers and multiport memory with different operating frequency are coupled together.

In multiport memory of the present invention, each input/output end port all has the instruction terminal, is used for synchronously receiving command signal with the clock signal of control store core operation.In each input/output end port, on the interval of operating cycles two double-length that is the storage core that needs of read operation and write operation at least, be provided for activating the command signal of storage core.If multiport memory has 2 input/output end ports or 4 input/output end ports, then can be respectively the interval of command signal be arranged on 2 times of the operating cycle or operating cycle 4 times.Had these to be provided with, multiport memory is in the stand-by state of response external controller.

If on than the short interval of predetermined space, command signal is provided, then command signal is preventing that aspect the fault be invalid.If command signal is offered different input/output end ports, even if then at interval unlike short these command signals that also receive of predetermined space.

According to the present invention, further, read or the data of write storage unit are transmitted between data input/output end port and storage unit through impact damper from storage unit.The impact damper storing therein has the data that are predefined in the figure place that quantitatively equals two or more storage unit.

When beginning read operation and write operation, for example, will have the data that ascertain the number in advance and be transferred to impact damper from storage unit.In read operation, read the data corresponding from impact damper, and output to external device (ED) from the data input/output end port with each address signal.In write operation, data storage that will be corresponding with each address signal in impact damper, and when write operation finishes immediately with the data write storage unit of impact damper.

In this mode, implement page operation easily.Generally, storage core (sensor amplifier etc.) must remain on state of activation when page operation.If impact damper of the present invention is not provided, then when the page operation implemented for input/output end port, can not implement storage operation for another input/output end port.In the present invention, when beginning to operate, give impact damper, make after this, to make the deactivation of storage core immediately the data transmission of storage unit.As a result, in addition the controller that when page operation, is connected with multiport memory also not necessarily to detect the busy condition of multiport memory.

Below we describe the present invention's (the 5th aspect) embodiment with reference to appended each figure.

Figure 111 representes the 1st embodiment of the multiport memory of (the 5th aspect) according to the present invention.On silicon chip, form multiport memory M with CMOS technology.

Multiport memory M comprises two input/output end port PPRT-A and PORT-B, I/O circuit 5010, and it is to port PPRT-A and PORT-B output signal with from port PPRT-A and PORT-B input signal and a plurality of storage block MB.Each storage block MB comprises DRAM storage core (comprising storage unit, sensor amplifier line SA etc.), and further comprises the control circuit that does not draw among the figure, code translator etc.Each storage unit comprises the capacitor of storage and data value signal corresponding charge.Select a storage core according to the row address signal that provides through port PPRT-A and PORT-B.The selection that responds given storage core activates all sensor amplifiers of the sensor amplifier line SA in given storage core simultaneously.That is, response activation instruction ACT activates the storage core, and we will describe this in the back, and is chosen in all memory cell region in this storage core.Read read data or write write data on the storage core according to the column address signal that provides after the sensor amplifier activation.

Figure 112 representes the I/O circuit 5010 of multiport memory M and the details of storage block MB.In the drawings, every signal wire of being represented by thick line all is made up of many lines.

I/O circuit 5010 comprises mould register 5012a and 5012b, clock buffer 5014a and 5014b,

Data input/output (i/o) buffer 5016a and 5016b, address buffer/ register 5018a and 5018b, instruction buffer 5020a and 5020b are with busy impact damper 5022a and 5022b, corresponding with input/output end port PPRT-A and PORT-B respectively.Mould register 5012a and 5012b are the registers that is used for from the operator scheme of device outer setting multiport memory M.

Clock buffer 5014a, address buffer/register 5018a and instruction buffer 5020a are respectively with clock signal clk A, and address signal ADDA and command signal CMDA are added on the storage block MB, just as adding from the device outside.Data input/output (i/o) buffer 5016a is used for from storage block MB outputting data signals DQA with data-signal DQA input storage block MB.Busy impact damper 5022a is to the outside output of device busy signal/BSYA.Clock buffer 5014b, address buffer/register 5018b and instruction buffer 5020b are respectively with clock signal clk B, and address signal ADDB and command signal CMDB are added on the storage block MB, just as adding from the device outside.Data input/output (i/o) buffer 5016b is used for from storage block MB outputting data signals DQB with data-signal DQB input storage block MB.Busy impact damper 5022b is to the outside output of device busy signal/BSYB.Clock signal clk A and CLKB, address signal ADDA and ADDB and command signal CMDA and CMDB, data-signal DQA and DQB; Pass through clock terminal respectively with busy signal/BSYA and/BSYB; Address terminal, the instruction terminal, data input/output terminal and busy terminal transmit.Provide the conducts such as (RD that for example reads instruction, write command WR) of activation instruction ACT and operational order to be used for the command signal CMDA and the CMDB of the operation of control store core.

Provide each address signal ADDA and ADDB as separated row address signal RA and column address signal CA.In input/output end port PPRT-A, row address signal RA synchronously is provided, column address signal CA and command signal CMDA with the forward position of clock signal clk A.In input/output end port PPRT-B, row address signal RB synchronously is provided, column address signal CB and command signal CMDB with the forward position of clock signal clk B.In this mode, multiport memory M receives special clock signal clk A and CLKB in input/output end port PPRT-A and PORT-B use respectively, and synchronously operates with clock signal clk A and CLKB.

Storage block MB comprises clock buffer 5024a and 5024b; Instruction latch 5026a and 5026b; Data latches 5028a and 5028b, row address latch 5030a and 5030b, column address latch 5031a and 5031b; With column address latch 5032a and 5032b, corresponding with input/output end port PPRT-A and PORT-B respectively.Storage block MB comprises arbiter 5034, control signal latch 5036, and column address counter 5038 and storage core 5040, they are public for input/output end port PPRT-A and PORT-B.Storage core 5040 has and the clock signal signal RAS that synchronously gets instruction, CAS and WE, the form of row address signal RA and column address signal CA.

When activating the enabling signal that provides from arbiter 5034/ENA, the mould register 5012a corresponding, clock buffer 5024a with input/output end port PPRT-A; Instruction latch 5026a; Data latches 5028a, row address latch 5031a and column address latch 5032a operate.When activating the enabling signal that provides from arbiter 5034/ENB, the mould register 5012b corresponding, clock buffer 5024b with input/output end port PPRT-B; Instruction latch 5026b; Data latches 5028b, row address latch 5031b and column address latch 5032b operate.

That is, when activating enabling signal/ENA, clock buffer 5024a provides clock signal clk A to the clock terminal CLK of storage core 5040.Further, instruction latch 5026a provides the command signal CMDA and the row address latch 5031a that latch to the row address terminal RA of storage core 5040 the row address signal RA that latchs (for example, corresponding with last address bit) to be provided to control signal latch 5036.And; Column address latch 5032a provides the column address signal CA that latchs (for example to column address counter 5038; Corresponding with following address bit) and data latches 5028a and the data input/output terminal DQ and the input/output (i/o) buffer 5016a exchange data signals of storing core 5040.

Similarly, when activating enabling signal/ENB, clock buffer 5024ba provides clock signal clk B to the clock terminal CLK of storage core 5040.Further, instruction latch 5026b provides the command signal CMDB and the row address latch 5031b that latch to the row address terminal RA of storage core 5040 column signal that latchs RA to be provided to control signal latch 5036.And column address latch 5032b provides column address signal CA and the data latches 5028b and the data input/output terminal DQ and the input/output (i/o) buffer 5016b exchange data signals of storing core 5040 that latchs to column address counter 5038.

Control signal latch 5036 produces the rwo address strobe signals RAS that is used to make 5040 operations of storage core according to command signal CMDA that receives and CMDB, column address gating signal CAS and write enabling signal WE, and the signal that produces is added to stores on the core 5040.And control signal latch 5036 provides one read/write instruction signal RWCMD in indication read operation and the write operation to arbiter 5034.

Column address counter 5038 produces column address signal CA according to information and the address signal ADDA about the burst length that provides from mould register 5012a and 5012b with ADDB, and exports column address signals to storing core 5040.

Arbiter 5034 comprises address comparison circuit 5042 and arbitration control circuit 5044.Address comparison circuit 5042 is relatively at address signal ADDA that provides from input/output end port PPRT-A and PORT-B and the row address signal RA between the ADDB, and determines that which early arrives in them.Arbitration control circuit 5044 produce busy signal/BSYA and/BSYB and enabling signal/ENA and/ENB, be used to make internal circuit to operate according to the comparative result of address comparison circuit 5042.

The details of Figure 113 presentation address comparator circuit 5042.

Address comparison circuit 5042 comprises two address matcher circuit 5042a and an address comparator 5042b, and address comparator 5042b detects the order that the address arrives.Address matcher circuit 5042a comprises a plurality of EOR circuit 5042c; Each EOR circuit 5042c is the corresponding position of the row address signal RA between address signal ADDA and address signal ADDB relatively; And further comprising a plurality of nMOS transistor 5042d, they are corresponding with each EOR circuit 5042c.The grid of each nMOS transistor 5042d all connects with the output terminal of corresponding EOR circuit 5042c, and their source ground and their drain electrode interconnect.Each EOR circuit 5042c, output low level signal when the place value of row address signal RA is mated between input/output end port PPRT-A and PORT-B each other, output high level signal when the place value of row address signal RA does not match.Response is cut off nMOS transistor 5042d from the low level signal of EOR circuit 5042c, and response is connected nMOS transistor 5042d from the high level signal of EOR circuit 5042c.Promptly; Unsteady from the matched signal/COIN1 of address matcher circuit 5042a output and/COIN2 when becoming during coupling between the position of all positions of row address signal RA in correspondence, and work as row address signal at least one correspondence between do not become low level signal simultaneously.The top and bottom that two address matcher circuit 5042a are arranged in storage block MB respectively (that is, are arranged near input/output circuitry 5010) shown in Figure 111.Address matcher circuit 5042a near the arrangement of input/output circuitry 5010 can shorten address signal ADDA and ADDB to the whole road of address matcher circuit 5042a through last propagation delay.Therefore, can be at early timing ratio than address signal ADDA and ADDB, thus obtain high speed operation.

Comparer 5042b receive matched signal/COIN1 with/COIN2 and clock signal clk A and CLKB, and export at first arriving signal/FSTA and/FSTB.

Figure 114 representes the details of comparer 5042b.

Comparer 5042b comprises pulse producer 5042e, and they synchronously produce positive pulse PLSA and PLSB with the forward position of clock signal clk A and CLKB respectively, and further comprise trigger 5042f, and it is at its input terminal received pulse PLSA and PLSB.Comparer 5042b receives matched signal/COIN1 with/COIN2 and be input to each phase inverter of exporting pulse PLSA and PLSB respectively.The NAND door that will in comparer 5042b, produce each pulse signal is processed undersized circuit component, make when the signal from the output of NAND door have with matched signal/COIN1 and/during signal level that COIN2 conflicts with right of priority give matched signal/COIN1 and/COIN2.Trigger 5042f makes at first that arriving signal/FSTA drops to low level when received pulse PLSA, when received pulse PLSB, making at first, arriving signal/FSTB drops to low level.

Figure 115 representes the operation of the comparer 5042b of enforcement when the row address signal that is added to input/output end port PORT-A and PORT-B matees each other.In this example, clock signal clk A has the identical cycle with CLKB.

Address matcher circuit 5042a shown in Figure 113 makes matched signal/COIN1 and/COIN2 be in quick condition (Hi-z) when row address signal RA matees.Accordingly, synchronously produce pulse PLSA and PLSB (Figure 115-(a)) with the forward position of clock signal clk A and CLKB respectively.The pulse PLSA that trigger 5042f response shown in Figure 114 received before other signal makes at first, and arriving signal/FSTA activates (Figure 115-(b)).After making at first arriving signal/FSTA deactivation, make the at first arriving signal corresponding/FSTB activation (Figure 115-(c)) with the pulse PLSB that receives later on.

Figure 116 representes the operation of comparer 5042b when row address signal RA does not match between input/output end port PORT-A and PORT-B.In this example, clock signal clk A has the identical cycle with CLKB.

Address matcher circuit 5042a makes each matched signal/COIN1 and/COIN2 drop to low level (Figure 116-(a)) when row address signal RA even a position all do not match.Accordingly, the pulse producer 5042e shown in Figure 114 force pulse signal PLSA and PLSB to drop to low level and with clock signal clk A and CLKB irrelevant (Figure 116-(b)).Therefore, at first arriving signal/FSTA and/FSTB remain on high level (Figure 115-(c)).

Figure 117 representes the operation as the row address signal RA that is added to input/output end port PORT-A and PORT-B comparer 5042b when clock signal clk A has coupling under the condition in a cycle different with the cycle of clock signal clk B.In this example, the cycle that clock signal clk B is set equals the twice in the cycle of clock signal clk A.Synchronously obtain row address signal RA with the forward position of clock signal clk A and CLKB respectively.In the drawings, the row address signal RA explanation that solid line is represented is added to the signal of input/output end port PORT-A and PORT-B, and the row address signal RA explanation that dotted line is represented is by each row address latch 5030a and the 5030b latched signal shown in Figure 112.

When row address signal RA matees, make matched signal/COIN1 and/COIN2 be in quick condition (Hi-z) with the mode identical with Figure 115.When matched signal/COIN1 with/when COIN2 is in quick condition (Hi-z); Pulse producer 5042e shown in Figure 114 plays a role, make respectively forward position with clock signal clk A and CLKB synchronously produce pulse signal PLSA and PLSB and at first arriving signal/FSTA and/FSTB.

Figure 118 representes to offer the arbitration control circuit 5044 of the arbiter shown in Figure 112.

Arbitration control circuit 5044 comprises control circuit 5044a and 5044b, and they are corresponding with input/output end port PPRT-A and PORT-B respectively.Control circuit 5044a receives reset signal RESETA, delay clock signals DCLKA, effective instruction signal ACTA, arriving signal/FSTA at first, busy signal/BSYA, and output enabling signal/ENA and busy signal/BSYB.Control circuit 5044b receives reset signal RESETB, delay clock signals DCLKB, effective instruction signal ACTB, arriving signal/FSTB at first, busy signal/BSYB, and output enabling signal/ENB and busy signal/BSYA.

When accomplishing the read or write corresponding, reset signal RESETA and RESETB are activated with input/output end port PPRT-A and PORT-B.Delay clock signals DCLKA and DCLKB are respectively through making clock signal clk A and CLKB postpone to obtain.Effective instruction signal ACTA and ACTB are activated.

Figure 119 representes the operation of the arbitration control circuit 5044 of enforcement when being added to the row address signal coupling of input/output end port PORT-A and PORT-B.In this example, the cycle of clock signal clk A and CLKB is identical.With clock signal clk A effective instruction ACT is provided synchronously, then effective instruction ACT synchronously is provided immediately with clock signal clk B.

Low level at first arriving signal/FSTA is synchronously obtained in the forward position of control circuit 5044a and delay clock signals DCLKA, and makes busy signal/BSYB activate (Figure 119-(a)).The activation of response effective instruction signal ACTA and the deactivation status of busy signal/BSYA, and control circuit 5044a activation enabling signal ENA (Figure 119-(b)).Because the at first arriving signal/FSTB of high level is synchronously obtained in the forward position of control circuit 5044b and delay clock signals DCLKB, so do not activate busy signal/BSYA (Figure 119-(c)).Though control circuit 5044b accepts the effective instruction signal ACTB of state of activation, because activated busy signal/BSYB, so control circuit 5044b does not activate enabling signal ENB (Figure 119-(d)).

The activation of response enabling signal ENA is transferred to storage core 5040 with the signal that is added to input/output end port PPRT-A.Activate storage core 5040, implement read operation according to the RD that reads instruction that is added to input/output end port PPRT-A.Accomplish read operation, the activation of control circuit 5044a response reset signal RESETA makes enabling signal ENA and busy signal/BSYB deactivation (Figure 119-(e)).

Below, further describe above-mentioned multiport memory M about its operation.

Figure 120 representes the operation of enforcement when the row address signal RA that is added to I/O PORT-A and PORT-B matees each other.In this example, clock signal clk A has the identical cycle with CLKB, the phase place of the leading a little clock signal clk B of the phase place of clock signal clk A.Be provided with the burst length both of input/output end port PORT-A and PORT-B to such an extent that equal 4 through each mould register 5012a and 5012b.Here, burst length is the number of data item of output and input when write or read is operated.

With the forward position of clock signal clk A synchronously, input/output end port PORT-A receives effective instruction ACT (command signal CMDA) and row address signal RA (address signal ADDA) (Figure 120-(a)).After input/output end port PORT-A receives signal immediately with the forward position of clock signal clk B synchronously, input/output end port PORT-B receives effective instruction ACT (command signal CMDB) and row address signal RA (address signal ADDB) (Figure 120-(b)).Here, before each forward position of clock signal clk A and CLKB one of command signal CMDA and CDMB and address signal ADDA and ADDB is provided with time ts (promptly according to regularly explanation) in advance their signal level is set.

Because it is identical with the row address signal RA that is added to port PO RT-A to be added to the row address signal RA of port PO RT-B, thus one then ground produce at first arriving signal/FSTA and/FSTB shown in Figure 115.Arbitration control circuit 5044 as combine the described response of Figure 119 at first arriving signal/FSTA and/FSTB activate enabling signal ENA and busy signal/BSYB (Figure 120-(c) and (d)).In this mode,, confirm in two address signals at first one of arrival through having the forward position of clock signals (being CLKA in this example) early with the row address signal RA that when time ts is set, provides with through utilization.After this, (Figure 120-(e)) operated in the activation of the storage core corresponding with row address signal RA 5040 response enabling signal ENA.

Response busy signal/BSYB, controller assert that like the CPU that is connected with input/output end port PORT-B the effective instruction ACT that is added to multiport memory M is invalid.

The next forward position of input/output end port PORT-A and clock signal clk A synchronously receives read instruction RD (being command signal CMDA) and column address signal CA (address signal ADDA) (Figure 120-(f)).The forward position of input/output end port PORT-B and clock signal clk B synchronously receives the RD that reads instruction (command signal CMDB) and column address signal CA (address signal ADDB) (Figure 120-(g)).With the next forward position of each clock signal clk A and CLKB (according to regularly explanation) synchronously, the RD that reads instruction is provided behind effective instruction ACT (or write command WR).Relevant with busy signal/BUSY, the controller that input/output end port PORT-B connects can not provide read instruction RD and column address signal CA.

Storage block MB output data continuously is from the corresponding storage unit of column address signal CA that is added to input/output end port PORT-A is read as data-signal DQA (Q0-Q3) (Figure 120-(h)) like them.2 time clock after reception reads instruction RD, outputting data signals DQA.Behind output and the as many data-signal DQA of burst length (=4), storage core 5040 enforcement precharge operations (Figure 120-(i)), thereby accomplish a memory cycle.The completion of response read operation makes enabling signal ENA deactivation (Figure 120-(j)).Here, precharge operation is used in bit lines charged that data transmission is transmitted out to storage unit with from storage unit to predetermined potential, makes the circuit deactivation relevant with the row address operation.In each storage operation, automatically implement precharge operation.According to the timing of a long definite precharge operation in the burst length of burst length that is stored in the input/output end port PORT-A in the corresponding mould register or input/output end port PORT-B.In this embodiment, if burst length is 4, then (being the time cycle that single read or write needs) is fixed on 4 clock period the memory cycle.That is, always the schedule time after receiving effective instruction is accomplished read operation and write operation.

With the clock signal clk A that is used for output data Q1 synchronously, next effective instruction ACT is added to input/output end port PORT-A (Figure 120-(k)).Because command signal CMDB is not added to input/output end port PORT-B,, produce the unmatched result of indication so compare row address signal RA with the address comparison circuit shown in Figure 113 5042 in this specific moment.Therefore, do not activate busy signal/BSYA and/BSYB, only activate enabling signal ENA (Figure 120-(l)).Will be at first arriving signal/FSTA be kept at high level with/FSTB, shown in Figure 116.

The row address signal RA that storage core 5040 bases are added to input/output end port PORT-A operates, and as described in the front (Figure 120-(m)).Storage block MB basis and following clock signal clk A synchronously provide the then ground outputting data signals DQA (Q0-Q3) (Figure 120-(n)) of of RD and column address signal CA that reads instruction.

After the operation of the storage core 5040 corresponding with input/output end port PORT-A is accomplished, the effective instruction ACT and the RD that reads instruction are added to input/output end port PORT-B (Figure 120-(O)) continuously.Because command signal CMDA is not added to input/output end port PORT-A in this specific moment, operate for input/output end port PORT-B so store core 5040, thus outputting data signals DQB (Figure 120-(p)).

Though do not draw in the drawings, row address signal RA that the forward position of response and clock signal synchronously provides and refreshing instruction implement to recover the refresh operation of electric charge in the capacitor of storage unit, and wherein row address signal RA confirms that storage core 5040 will be refreshed.Perhaps perhaps can require refresh operation through input/output end port PORT-B through input/output end port PORT-A.In this mode, implement refresh operation according to the address signal that provides from the device outside by the device of a storage core 5040.

Figure 121 represent when clock signal CLKA identical with CLKB, the operation that the phase place of the leading clock signal clk B of the phase place of clock signal clk A is implemented during more than half period.Identical in the command signal CMDA that is added to multiport memory M and CMDB and address signal ADDA and ADDB and Figure 120 situation.

In this example, when effective instruction ACT and row address signal RA are added to input/output end port PORT-A (Figure 121-(a)), also command signal CMDB and address signal ADDB are not added to input/output end port PORT-B.Therefore, activate enabling signal/ENA (Figure 121-(b)), storage core 5040 is operated (Figure 121-(c)) for input/output end port PORT-A.After this, effective instruction ACT and the row address signal RA identical with input/output end port PORT-A are added to input/output end port PORT-B (Figure 121-(d)).

Control circuit 5044b shown in Figure 118 is according to the at first activation of arriving signal/FSTA and the activation of enabling signal/ENA, and activation busy signal/BSYB (Figure 121-(e)).Response busy signal/BSYB, controller that is connected with input/output end port PORT-B such as CPU assert that the effective instruction ACT that is added to multiport memory M is invalid.Later operation is identical with above-mentioned Figure 120's.

Figure 122 representes almost to be added to simultaneously the mutual asynchronous operation of row address signal RA of input/output end port PORT-A and PORT-B.Clock signal C KLA has the identical clock period with CLKB, the phase place of the leading a little clock signal clk B of the phase place of clock signal clk A.Be provided with burst length to such an extent that equal 4 through mould register 5012 for input/output end port PORT-A and port PO RT-B both.

When row address signal RA not simultaneously, different storage cores 5040 are operated.So the comparer 5042b shown in Figure 114 makes at first arriving signal/FSTA and/FSTB deactivation.That is, do not carry out the address arbitration.Arbitration control circuit 5044 correspondences at first arriving signal/FSTA with/deactivation status of FSTB and the activation of effective instruction signal ACTA and ACTB, make enabling signal/ENA and/ENB activation (Figure 121-(a) and (b)).The result; Effective instruction ACT and the row address signal RA that relevant storage core 5040 responses are added to input/output end port PORT-A operates (Figure 121-(c)), and another storage core 5040 responds the effective instruction ACT and the row address signal RA that are added to input/output end port PORT-B and operates (Figure 121-(d)).That is, input/output end port PORT-BA and PORT-B operate independently of each other.Because row address signal RA is different each other, neither activates busy signal/BSYA and also do not activate busy signal/BSYB.

In the above embodiments; When input/output end port PORT-A and PORT-B receive two same storage cores 5040 of indication respectively with the synchronous row address signal RA of clock signal clk A and CLKB, storage core 5040 in two row address signal RA at first one of arrival operate.That is, we just can process the multiport memory M of clock synchronization type like this.

Arbiter 5034 is through relatively satisfied all requirements to its expection of row address signal RA, so can process through simple configuration.Therefore, the chip size of multiport memory M is reduced.

Because input/output end port PORT-A and PORT-B have separately clock terminal CLKA and CLKB, so can be respectively among input/output end port PORT-A and the PORT-B each be provided with the frequency of clock signal clk A and CLKB.That is a plurality of controllers that, operate on the different operating frequency can be connected with multiport memory M.

Further, determine in two addresses at first one of arrival with being arranged on row address signal RA before the relevant forward position of clock signal clk A and CLKB.That is, utilize the time that is provided with of address signal to discern one that at first arrives.Therefore, before 5040 its operations of beginning of storage core, can discern input/output end port, thereby realize the high speed storing operation accord priority.Further, because according to definite of at first arriving in the forward position with more preceding clock signals CLKA (or CLKB), so can further improve storage operation speed.

In arbiter 5034, address comparison circuit 5042 is row address signal RA relatively, and arbitration control circuit 5044 is synchronously checked matching addresses with the clock signal clk A and the CLKB that are used to obtain effective instruction ACT.Because always at predetermined regularly the edge of timing signal (promptly) row address signal RA relatively each other, so can prevent upset operation by the storage core 5040 that causes with the irrelevant address signal of storage operation.

The method that Figure 123 representes the 2nd embodiment of multiport memory and multiport memory is controlled in (the 5th aspect) according to the present invention.With the identical figure notation parts identical, and omit detailed description to them with the 1st embodiment.

In this embodiment, 1/4th sizes with the 1st embodiment form storage block MB (representing with bold box in the drawings).That is the number of the sensor amplifier that, is activated simultaneously is 1/4th of the 1st embodiment.Except the size of storage block MB, dispose identical with the 1st embodiment.Because the multiport memory M of Figure 123 has driven sensor amplifier less the time, so the power consumption when storage operation has reduced.

This embodiment can produce the identical advantage with above-mentioned the 1st embodiment.In addition, can reduce power consumption in the present embodiment.

The method that Figure 124 representes the 3rd embodiment of multiport memory and multiport memory is controlled in (the 5th aspect) according to the present invention.With the identical figure notation parts identical, and omit detailed description to them with the 1st embodiment.

In this embodiment, data register (impact damper) 5046a and 5046b are provided in each storage block MB, they temporarily are stored in each data-signal DQA and DQB between data latches 5028 and the storage core 5040.Among data register 5046a and 5046b and input/output end port PORT-A and the PORT-B any one combines operates.And the arbitration control circuit 5048 of arbiter 5034 is different from the arbitration control circuit 5044 of the 1st embodiment.Arbitration control circuit 5048 is not exported busy signal/BSYA and/BSYB, and busy impact damper is not provided in I/O circuit 5010.Other configuration is almost identical with the 1st embodiment.That is, in input/output end port PORT-A and PORT-B, respectively through clock terminal, address terminal; Instruction terminal and data input/output terminal, transmit clock signal CLKA and CLKB; Address signal ADDA and ADDB, command signal CMDA and CMDB are with data-signal DQA and DQB.Storage block MB comprises DRAM storage core 5040, and further comprises the control circuit that does not draw among the figure, code translator etc.Storage unit comprises the capacitor according to the data value signal stored charge.

Even receive simultaneously when carrying out requiring of storage operation as input/output end port PORT-A and PORT-B for same address signal RA; This multiport memory M also can implement storage operation to input/output end port PORT-A and PORT-B, and we will describe this in the back.Therefore, need be as the 1st embodiment to the outside output of device busy signal/BSYA and/BSYB.

In each input/output end port PORT-A and PORT-B, be provided with and add that effective instruction ACT equals to store more than 2 times of operating cycle of core 5040 (according to regularly explanation) at interval.If effective instruction ACT then cancels added effective instruction ACT at interval less than top definite cycle in same input/output end port PORT-A (or PORT-B).The interval of effective instruction ACT that is added to different input/output end ports is unrestricted.

Specific timing with the clock signal of following the timing that is used to receive effective instruction ACT as the 1st embodiment synchronously provides read instruction RD and write command WR.Storage core 5040 is along with its operation is automatically charged.In this embodiment, for example, the cycle tCLK of clock signal clk A and CLKB is arranged on 10ns, BL is arranged on 4 with burst length, and DL is arranged on 4 with the data stand-by period.Data stand-by period DL definition is from the input number of RD to the clock period of output data that read instruction.Burst length BL and data stand-by period DL are set in mould register 5012a and 5012b.

Figure 125 represent to arbitrate details of control circuit 5048.

Through control circuit 5044a and the 5044b structure arbitration control circuit 5048 that control circuit 5048a and 5048b is added to the 1st embodiment respectively.The control circuit 5048a corresponding with input/output end port PORT-A receives reset signal RESETA and reverse signal RVS and enabling signal/ENA0 and busy signal/BSYB from control circuit 5044a, and output enabling signal/ENA.The control circuit 5048b corresponding with input/output end port PORT-B receives reset signal RESETB and reverse signal RVS and enabling signal/ENB0 and busy signal/BSYA from control circuit 5044b, and output enabling signal/ENB.Producing enabling signal/ENA0 and/ENB0 with enabling signal/ENA of the 1st embodiment and/ timing that ENB is identical.

Figure 126 representes the operation of the arbitration control circuit 5048 of enforcement when the row address signal that is added to input/output end port PORT-A and PORT-B matees each other.In this example, the cycle of clock signal clk A and CLKB is identical.Synchronously effective instruction ACT is added to input/output end port PORT-A with clock signal clk A.After this synchronously effective instruction ACT is added to input/output end port PORT-B with clock signal clk B immediately.The controller that is connected with input/output end port PORT-A requires write operation, and the controller that is connected with input/output end port PORT-B requires read operation.

The operation of control circuit 5044a and 5044b almost (Figure 119) with above-mentioned the 1st embodiment is identical.Low level at first arriving signal/FSTA is synchronously obtained in control circuit 5044a and delay clock signals DCLKA forward position, and activation busy signal/BSYB (Figure 126-(a)).Because the at first arriving signal/FSTB of high level is synchronously obtained in control circuit 5044b and delay clock signals DCLKB forward position, do not activate busy signal/BSYA (Figure 126-(b)).The activation of control circuit 5048a response busy signal/BSYB and the low level of reverse signal RVS, and activation enabling signal/ENA (Figure 126-(c)).The activation of control circuit 5048b response busy signal/BSYA and the low level of reverse signal RVS make enabling signal/ENB deactivation (Figure 126-(d)).

With clock signal clk A and CLKB next regularly synchronously, write command WR and the RD that reads instruction are provided respectively (Figure 126-(e)).The response write command WR and the RD that reads instruction, and control circuit (not drawing among the figure) the activation reverse signal RVS of generation reverse signal RVS (Figure 126-(f)).

Control circuit 5048a and 5048b respond the activation of reverse signal RVS respectively, switch the level (Figure 126-(g)) of enabling signal/ENA and/ENB.Then, at first implement read operation (Figure 126-(h)) for input/output end port PORT-B.After accomplishing read operation, activate reset signal RESETB, and make reverse signal RVS deactivation (Figure 126-(i)).The deactivation of control circuit 5048a and 5048b response reverse signal RVS makes the level of enabling signal/ENA and/ENB be returned to their primary electric level (Figure 126-(j)) separately.Then, the read operation (Figure 126-(k)) for input/output end port PORT-A is implemented in the activation of response enabling signal/ENA.

After accomplishing read operation, activate reset signal RESETA (Figure 126-(l)), and make busy signal/BSYB deactivation (Figure 126-(m)).The deactivation of control circuit 5048a response busy signal/BSYB makes enabling signal/ENA deactivation (Figure 126-(n)).In this mode of present embodiment, when row address signal RA is identical and the command request write operation of 1 arrival of Dang Di, then during the command request read operation of the 2nd arrival, so control store core 5040 makes it at first implement read operation.At storer LSI, as have among the DRAM of multiport memory, store core through the data rear drive that will write in reception and carry out write operation and store core output data enforcement read operation then through at first driving.Therefore, when behind write operation, implementing read operation, all the operating cycle becomes the stand-by period usually.In this embodiment, when write operation is at first carried out read operation when reading to vie each other, thereby shorten whole operating cycles and the service efficiency of improving the data bus of transmission of data signals.

Below, we describe the operation according to the multiport memory M of the 3rd embodiment.

Figure 127 representes when input/output end port PORT-A and PORT-B receive effective instruction ACT with identical row address signal RA, to implement the method for read operation.The phase place of the leading a little clock signal clk B of the phase place of clock signal clk A.That is, effective instruction ACT gets into input/output end port PORT-B early than effective instruction ACT a little to the input of input/output end port PORT-A.

For input/output end port PORT-A, and response effective instruction ACT enforcement read operation READ (Figure 127-(a)).The data storage that to read from storage unit is among data register 5046a (or 5046b).Then, for input/output end port PORT-B, response effective instruction ACT enforcement read operation READ (Figure 127-(b)).After accomplishing read operation READA under the control of arbiter 5034, implement read operation READB (Figure 127-(c)) for input/output end port PORT-B.The data storage that to read from storage unit through read operation READB among data register 5046b (or 5046a) (Figure 127-(d)).In this mode; Even when effective instruction ACT is added to input/output end port PORT-A and PORT-B basically simultaneously with identical row address signal RA, also can implement read operation (or write operation) continuously among input/output end port PORT-A and the PORT-B each.Automatically implement precharge operation after storage core 4050 each in accomplishing read operation READA and READB, thereby accomplish the memory cycle.

After synchronously importing the RD that reads instruction with the 5th to the 8th clock signal clk A shown in the figure, output is stored in retrieve data among the register 5046a corresponding with input/output end port PORT-A as output data Q1-Q3 (Figure 127-(e)) continuously.After synchronously importing the RD that reads instruction with the 5th to the 8th clock signal clk B shown in the figure, output is stored in retrieve data among the register 5046b corresponding with input/output end port PORT-B as output data Q1-Q3 (Figure 127-(f)) continuously.

Input/output end port PORT-A and PORT-B 4 time clock behind the 1st effective instruction ACT receive next effective instruction ACT, further implement read operation READA and READB (Figure 127-(g) with (h)) respectively.When in per 4 clock period, adding effective instruction ACT one time, can export data retrieved continuously and have no gap (that is, read in no gap).And once obtain random access operation through in per 4 clock period, receiving effective instruction ACT.

Figure 128 representes when effective instruction ACT is added to input/output end port PORT-A and PORT-B with mutual different row address signal RA, to implement the method for read operation.

For the input/output end port PORT-A that at first receives effective instruction ACT and row address signal RA, and response effective instruction ACT enforcement read operation READA (Figure 128-(a)).The data storage that to read from storage unit among data register 5046a (Figure 128-(b)).Then, input/output end port PORT-B, the read operation READB of another storage core 5040 different with the storage core that is used for read operation READA of response effective instruction ACT enforcement sensing (Figure 128-(c)).That is, implement read operation READA and read operation READB independently of each other.The data storage that to read from storage unit through read operation READB among data register 5046b (Figure 128-(d)).

After synchronously importing the RD that reads instruction with the 5th to the 8th clock signal clk A shown in the figure, output is stored in retrieve data among the register 5046a as output data Q0-Q3 (Figure 128-(e)) continuously.After synchronously importing the RD that reads instruction with the 5th to the 8th clock signal clk B shown in the figure, output is stored in retrieve data among the register 5046b corresponding with input/output end port PORT-B as output data Q0-Q3 (Figure 128-(f)) continuously.

Input/output end port PORT-A and PORT-B 4 time clock behind the 1st effective instruction ACT receive next effective instruction ACT, further implement read operation READA and READB (Figure 128-(g) with (h)) respectively.

Figure 129 representes when input/output end port PORT-A and PORT-B receive effective instruction ACT with identical row address signal RA, to implement the method for write operation.

In input/output end port PORT-A and PORT-B; With each following clock signal clk A that follows the forward position that is used to receive effective instruction ACT and the forward position of CLKB write command WR is provided synchronously, column address signal CA and the 1st write data Q0 and Q0 (Figure 129-(a) with (b)).After this, with each clock signal clk A and CLKB write data Q1-Q3 and Q0-Q3 are provided synchronously (Figure 129-(c) with (d)).Write data Q0-Q3 and Q0-Q3 are stored in respectively among each data register 5046a and the 5046b (Figure 129-(e) with (f)).For the input/output end port PORT-A that at first receives effective instruction ACT and row address signal RA, synchronously implement write operation WRITEA (Figure 129-(g)) with the specific timing of the clock signal clk A that obtains write data Q3.After accomplishing write operation WRITEA, implement the write operation WRITEB corresponding (Figure 129-(h)) with input/output end port PORT-B.Through write operation WRITEA and WRITEB, the write data Q0-Q3 and the Q0-Q3 that are stored among each data register 5046a and the 5046b are write the storage unit corresponding with column address signal CA, thereby accomplish write operation.

In write operation, in per 4 clock period, one group of write data is provided once, make write data to get into continuously and have no gap (that is no space write).

Figure 130 representes to implement write operation and read operation continuously for input/output end port PORT-A; With the row address signal RA identical of write operation one after the other implement to point to to(for) input/output end port PORT-B, the situation of the write operation of the row address signal RA identical with the row address signal RA of the read operation of input/output end port PORT-A with sensing with the row address signal RA of the write operation of input/output end port PORT-A.The timing of the 1st write operation is identical with Figure 127, and omits the explanation to it.

At input/output end port PORT-B, the effective instruction ACT corresponding with the 2nd write operation is provided (Figure 130-(a)) in the timing identical with Figure 127.Because command signal is not added to input/output end port PORT-A, so after obtaining write data Q0-Q3, implement write operation WRITEB (Figure 130-(b)) immediately.

At input/output end port PORT-A, next effective instruction ACT synchronously is provided (Figure 130-(c)) with the 7th clock signal clk A shown in the figure.Though do not draw in the drawings, activate enabling signal/ENB for input/output end port PORT-B in this specific moment.As a result, after accomplishing write operation WRITEB, implement read operation READA (Figure 130-(d)).Because multiport memory M carries out write operation WRITEB and read operation READA with the order that receives each instruction, the data of the storage unit of before accomplishing write operation, being read are constant.

In addition; Because can exporting, input/output end port PORT-A is stored among the data register 5046b corresponding data as retrieve data, so can before the write operation WRITEB of input/output end port PORT-B, implement the read operation READA of input/output end port PORT-A with input/output end port PORT-B.

Figure 131 representes to implement write operation and read operation continuously for input/output end port PORT-A, the situation of the write operation of the row address signal RA identical with the row address signal RA of the read operation of the row address signal RA identical with the row address signal RA of the write operation of input/output end port PORT-A of read operation one after the other implement to point to to(for) input/output end port PORT-B and sensing and input/output end port PORT-A.For the timing of the 1st write operation of input/output end port PORT-A with identical with the read operation of the write operation of Figure 129 and Figure 128 respectively for the timing of the 1st read operation of input/output end port PORT-B.

At input/output end port PORT-A, effective instruction ACT synchronously is provided and reads instruction with the 7th and the 8th clock signal clk A shown in the figure (Figure 131-(a)).Because effective instruction ACT is not added to input/output end port PORT-B, so implement read operation READA (Figure 131-(b)) for input/output end port PORT-A in this specific moment.

Below, at input/output end port PORT-B, effective instruction ACT and write command WR synchronously are provided (Figure 131-(c)) with the 8th and the 9th clock signal clk B shown in the figure.After receiving data Q0-Q3, implement write operation (not drawing among the figure) for input/output end port PORT-B.

Figure 132 is illustrated in clock signal clk A and has the operation of when the row address signal that is added to input/output end port PORT-A and PORT-B matees each other, implementing in the situation of different clock period with CLKB.In this example, the Cycle Length of clock signal clk B equals the twice of the Cycle Length of clock signal clk A.

At input/output end port PORT-A,, implement read operation with the mode identical with Figure 127 when in per 4 clock period, adding one group of effective instruction ACT and reading instruction RD once.At input/output end port PORT-B, also when in per 4 clock period, adding one group of effective instruction ACT and reading instruction RD once.Time ratio from the 1st effective instruction ACT to input/output end port PORT-B that import is to time that input/output end port PORT-A imports the 1st effective instruction ACT a little later (Figure 132-(a)).Therefore, coexist mutually with the situation of Figure 127 and implement read operation READB (Figure 132-(b)) behind the read operation READA.Between two read operation READA, carry out the next read operation READB corresponding (Figure 132-(c)) with the effective instruction ACT that follows of input/output end port PORT-B.

Present embodiment can provide the advantage identical with the 1st above-mentioned embodiment.In addition, in each input/output end port PORT-A and PORT-B, present embodiment is with the interval (according to regularly explanation) of the effective instruction ACT more than 2 times in the operating cycle that equals to store core 5040.Therefore, even it is identical to work as the row address signal RA that is added to input/output end port PORT-A and PORT-B, also can implement read operation and write operation for each port certainly.Therefore, the controller of control multiport memory M need not detect the busy condition of multiport memory M.So just simplified the control (with hardware and software) of controller.

The method that Figure 133 representes the 4th embodiment of multiport memory and multiport memory is controlled in (the 5th aspect) according to the present invention.With identical figure notation and the identical parts of the 1st and the 3rd embodiment, and omit detailed description to them.

In this embodiment, the data register 5046a and the 5046b that provide page buffer 5050a and 5050b to replace above-mentioned the 3rd embodiment.Among page buffer 5050a and 5050b and input/output end port PORT-A and the PORT-B at least one combines operates.Other configuration is almost identical with the 3rd embodiment.

Each page buffer 5050a and 5050b comprise latch, wherein are stored in the data of all storage unit in the storage core 5040.When beginning read operation and write operation, the data in the storage unit that is stored in the storage core of selecting 5040 are read into page buffer 5050a (or 5050b).In read operation, the data of response column address signal CA output latch in page buffer 5050a are as data-signal.In write operation, at first data-signal is write page buffer 5050a according to column address signal CA.After this, when accomplishing write operation with the data write storage unit of page buffer 5050a.

Below, we describe the operation of the 4th embodiment multiport memory M.

Figure 134 representes when input/output end port PORT-A and PORT-B receive effective instruction ACT with identical row address signal RA, to implement the method for read operation.The phase place of the leading a little clock signal clk B of the phase place of clock signal clk A.That is the effective instruction ACT that, is input to I/O PORT-A than the effective instruction ACT that is input to I/O PORT-B a little earlier.

At input/output end port PORT-A, and response effective instruction ACT enforcement read operation READA (Figure 134-(a)).From all storage unit sense datas of the storage core 5040 selected by read operation READA, and retrieve data is stored among the page buffer 5050a (or 5050b) one (Figure 134-(b)).On the other hand, at input/output end port PORT-B, row address signal RA be added to the identical of input/output end port PORT-A, so unreally grant the corresponding read operation of effective instruction ACT.

At input/output end port PORT-A, synchronously add the RD that reads instruction (Figure 134-(c) with (d)) with the 1st and the 5th clock signal clk A as shown in the figure.After receiving the RD that respectively reads instruction with the 5th to the 12nd clock signal clk A synchronously continuously output be stored in data among the page buffer 5050a as output data Q0-Q7 (Figure 134-(e)).That is, implement page read operation.

By the same token, at input/output end port PORT-B, synchronously add the RD that reads instruction (Figure 134-(f) with (g)) with the 1st and the 5th clock signal clk B as shown in the figure.After receiving the RD that respectively reads instruction with the 5th to the 12nd clock signal clk B synchronously continuously output be stored in data among the page buffer 5050a as output data Q0-Q7 (Figure 134-(h)).In this mode, if row address signal RA is identical, the shared page buffer 5050a of input/output end port PORT-A and PORT-B (or 5050b) then.

Input/output end port PORT-A and PORT-B both 8 clock period behind the 1st effective instruction ACT, receive next effective instruction ACT (Figure 134-(i) with (j)).Because row address signal RA is identical, so only implement read operation READA (Figure 134-(k)).Do not implement read operation READB for input/output end port PORT-B.Through adding that in per 4 clock period the RD that reads instruction once can export read data continuously and have no gap (that is, read in no gap).

Figure 135 representes when effective instruction ACT is added to input/output end port PORT-A and PORT-B with different row address signal RA, to implement the method for read operation.Identical with timing and Figure 134 of the corresponding read operation of input/output end port PORT-A.

At the input/output end port PORT-A that at first receives effective instruction ACT and row address signal RA, and response effective instruction ACT enforcement read operation READA (Figure 135-(a)).Will be from all storage unit data storage of reading of storage core 5040 among page buffer 5050a (Figure 135-(b)).At input/output end port PORT-B, response effective instruction ACT is for implementing read operation READB (Figure 135-(c)) with the different storage core 5040 of read operation READA.That is, will be by read operation READB from all storage unit data storage of reading of storage core 5040 among page buffer 5050b (Figure 135-(d)).After this, to implement read operation with the same way as that combines Figure 134 to describe.In this mode, when row address signal RA each other not simultaneously, independently implement read operation READA and read operation READB, respectively retrieve data is stored among each page buffer 5050a and the 5050b.

Figure 136 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA, and implements write operation, then adds effective instruction ACT and different row address signal RA, causes implementing the situation of write operation.

At input/output end port PORT-A and PORT-B, synchronously add effective instruction ACT and identical row address signal RA with each forward position of clock signal clk A and CLKB.Arbiter 5034 shown in Figure 133 assert that input/output end port PORT-A at first receives effective instruction ACT, and enforcement read operation READA (Figure 136-(a)) so that data are transferred to page buffer 5050a (or 5050b) from storage unit.

From all storage unit sense datas of the storage core 5040 selected by read operation READA, and be stored among the page buffer 5050a (or 5050b) (Figure 136-(b)).On the other hand, at input/output end port PORT-B because row address signal RA be added to the identical of input/output end port PORT-A, so response effective instruction ACT does not implement read operation.

After this, at input/output end port PORT-A, synchronously add write command WD and column address signal CA (Figure 136-(c) with (d)) with the 1st and the 5th clock signal clk A as shown in the figure.To write with the write data Q0-Q7 that clock signal CLKA synchronously adds continuously among the page buffer 5050a (Figure 134-(e)).That is, implement page write operation.

At input/output end port PORT-B, synchronously add write command WR and column address signal CA (Figure 136-(f) with (g)) with the 1st and the 5th clock signal clk B as shown in the figure.To write with the write data Q0-Q7 that clock signal clk B synchronously adds one by one among the shared row page buffer 5050a (Figure 134-(h)).In this mode, if row address signal RA is identical, the shared same page buffer 5050a of input/output end port PORT-A and PORT-B (or 5050b) in write operation then.

At first receiving the input/output end port PORT-A of effective instruction ACT, synchronously implementing write operation WRITEA (Figure 136-(i)) with the specific timing of the clock signal clk A that obtains write data Q7.After accomplishing write operation WRITEA, implement the write operation WRITEB corresponding (Figure 136-(j)) with input/output end port PORT-B.

After this, at input/output end port PORT-A and PORT-B, synchronously add effective instruction ACT and mutual different row address signal RA with each forward position of clock signal clk A and CLKB.The identification of arbiter 5034 shown in Figure 133 at first is added to input/output end port PORT-A with effective instruction ACT, and one then ground implement read operation READA and READB (Figure 136-(k) and (l)).

From all storage unit sense datas of the storage core 5040 selected by read operation READA, and be stored among the page buffer 5050a (or 5050b) (Figure 136-(m)).Further, from all storage unit sense datas of the storage core 5040 selected by read operation READB, and be stored among another page buffer 5050b (or 5050a) (Figure 136-(n)).

At input/output end port PORT-A, synchronously add read instruction RD and column address signal CA (Figure 136-(o) with (p)) with the 13rd and the 17th clock signal clk A as shown in the figure.Will with clock signal CLKA synchronously one then write data Q0-Q7 who adds be stored among the page buffer 5050a (Figure 136-(q)).

Similarly, at input/output end port PORT-B, synchronously add write command WR and column address signal CA (Figure 136-(r) with (s)) with the 13rd and the 17th clock signal clk B as shown in the figure.Will with clock signal CLKB synchronously one then write data Q0-Q7 who adds write among the page buffer 5050b (Figure 136-(t)).In this mode, when row address signal RA does not use page buffer 5050a and 5050b simultaneously.

At the input/output end port PORT-A that at first receives effective instruction ACT and row address signal RA, synchronously implement write operation WRITEA (Figure 136-(u)) with the specific timing of the clock signal clk A that obtains write data Q7.After accomplishing write operation WRITEA, implement write operation WRITEB (Figure 136-(v)) corresponding with input/output end port PORT-B.Through write operation WRITEA and WRITEB, respectively the write data Q0-Q7 of storer in page buffer 5050a and 5050b write the storage unit corresponding with column address signal CA, thereby accomplish write operation.

Figure 137 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA; Implement write operation; Then add effective instruction ACT and identical row address signal RA, cause implementing the situation of write operation in input/output end port PORT-A enforcement read operation with at input/output end port PORT-B.The timing of the 1st write operation is identical with Figure 137, and we will omit the description to it.

At input/output end port PORT-A and PORT-B, effective instruction ACT and identical row address signal RA synchronously are provided (Figure 137-(a) and (b)) with each forward position of the 12nd clock signal clk A and the CLKB shown in the figure.Arbiter 5034 identifications shown in Figure 133 at first are added to input/output end port PORT-A with effective instruction ACT, and enforcement read operation READA (Figure 137-(c)).From all storage unit sense datas of the storage core 5040 selected by read operation READA, and be stored among the page buffer 5050a (or 5050b) (Figure 137-(d)).At input/output end port PORT-B, because row address signal RA is identical with the signal that is added to input/output end port PORT-A, so the unreal corresponding write operation of effective instruction ACT of granting.

After this, at input/output end port PORT-A, synchronously add the RD that reads instruction (Figure 137-(e) with (f)) with the 13rd and the 17th clock signal clk A as shown in the figure.After receiving the RD that respectively reads instruction with the 17th to the 24th clock signal clk A as shown in the figure synchronously continuously output be stored in data among the page buffer 5050a (Figure 137-(g)).

At input/output end port PORT-B, synchronously add write command WR (Figure 137-(h) with (i)) with the 13rd and the 17th clock signal clk B as shown in the figure.To be stored in the write data Q0-Q7 that clock signal CLKB synchronously adds continuously among the shared page buffer 5050a (Figure 137-(j)).

After this, at input/output end port PORT-B, synchronously implement write operation WRITEB (Figure 137-(k)) with the specific timing of the clock signal clk B that obtains write data Q7.

Figure 138 representes effective instruction ACT is added to input/output end port PORT-A and PORT-B with identical row address signal RA; Implement write operation and read operation; Then add effective instruction ACT and different row address signal RA, cause implementing the situation of write operation and read operation.

At input/output end port PORT-A and PORT-B, effective instruction ACT and identical row address signal RA synchronously are provided (Figure 138-(a) with (b)) with the forward position of clock signal clk A and CLKB.Arbiter 5034 is confirmed at first effective instruction ACT to be added to input/output end port PORT-A, and enforcement read operation READA (Figure 138-(c)).From all storage unit sense datas of the storage core 5040 selected by read operation READA, and sense data is stored among the page buffer 5050a (or 5050b) (Figure 137-(d)).On the other hand, at input/output end port PORT-B, row address signal RA is with to be added to those of input/output end port PORT-A identical, so unreally grant the corresponding read operation of effective instruction ACT.

After this, at input/output end port PORT-A, synchronously add write command WR (Figure 138-(e) with (f)) with the 1st and the 5th clock signal clk A.To be stored in the write data Q0-Q7 that clock signal clk A synchronously adds continuously among the page buffer 5050a (Figure 137-(g)).

At input/output end port PORT-B, synchronously add the RD that reads instruction (Figure 138-(h) with (i)) with the 1st and the 5th clock signal clk B.After receiving the RD that respectively reads instruction with the timing of the 5th to the 12nd clock signal clk B synchronously one then ground output be stored in data among the page buffer 5050a as output data Q0-Q7 (Figure 138-(j)).At input/output end port PORT-A, synchronously implement write operation WRITEA (Figure 138-(k)) with the specific timing of the clock signal clk A that obtains write data Q7.

Then, at input/output end port PORT-A and PORT-B, effective instruction ACT and each other different row address signal RA synchronously are provided (Figure 138-(l) with (m)) with the forward position of clock signal clk A and CLKB.Arbiter 5034 identification at first is added to input/output end port PORT-A with effective instruction ACT, and implements read operation READA and READB (Figure 138-(n) and (o)) continuously.From all storage unit sense datas of the storage core 5040 selected by read operation READA, and with the data storage of reading in page buffer 5050a (or 5050b) (Figure 138-(p)).Further, from all storage unit sense datas of the storage core 5040 selected by read operation READB, and with the data storage of reading another (Figure 138-(q)) in page buffer 5050b (or 5050a).

At input/output end port PORT-A, regularly synchronously add write command WR (Figure 138-(r) with (s)) with the 13rd and the 17th of clock signal clk A.Will with clock signal clk A synchronously one then write data Q0-Q7 who adds write among the page buffer 5050a (Figure 138-(t)).

Similarly, at input/output end port PORT-B, regularly synchronously add write command WR (Figure 138-(u) and (v)) with the 13rd and the 17th of clock signal clk A.Will with clock signal clk B synchronously one then write data Q0-Q7 who adds write among the page buffer 5050b (Figure 138-(w)).

Present embodiment can provide the advantage identical with the 3rd above-mentioned embodiment.Further, in the present embodiment, as for page buffer 5050a and the 5050b of the temporary transient data storage of all storage unit of storage core 5040 between data latches 5028 and storage core 5040.This makes multiport memory M can implement page read operation and page write operation.

When identical row address signal RA is added to input/output end port PORT-A and PORT-B, shared same page buffer 5050a.These data that prevent write storage unit are destroyed through overlapping operation.

When identical row address signal RA is added to input/output end port PORT-A and PORT-B, responds a port and only implement read operation.Therefore, the power consumption in the time of can reducing operation with the situation comparison of each read operation of implementing for two ports. Use page buffer 5050a and 5050b even when implementing page operation, also eliminated for control multiport memory M the needs of the controller of the busy condition of detection multiport memory M.Therefore, the control (with hardware and software) of controller etc. becomes and has been easier to.

Figure 139 representes according to the operation of the multiport memory of the 5th embodiment of multiport memory and controls the method for multiport memory of the present invention.With the identical figure notation parts identical, and omit detailed description to them with the 4th embodiment.

This embodiment has read instruction RD and the write command WR and read instruction PRD and the write command PWR that are used for page operation that is used for common train of impulses operation.The circuit arrangement of multiport memory M is identical with the 4th embodiment basically.

In Figure 139, effective instruction ACT and identical row address signal RA are added to input/output end port PORT-A and PORT-B (Figure 139-(a) with (b)).With the next cycle of clock signal clk A and CLKB synchronously, add the PRD that reads instruction (Figure 139-(c) with (d)), implement page read operation (Figure 139-(e)).The timing of page read operation is identical with Figure 134, and omits the detailed description to it.

After this, effective instruction ACT and identical row address signal RA are added to input/output end port PORT-A and PORT-B (Figure 139-(f) with (g)).With the next cycle of clock signal clk A and CLKB synchronously, add the RD that reads instruction (Figure 139-(h) with (i)).Implement read operation READA and READB (Figure 139-(j) with (k)) continuously for each input/output end port PORT-A and PORT-B.Promptly accomplish common read operation (being the train of impulses read operation).

This present embodiment can provide the advantage identical with the 4th above-mentioned embodiment.Because this embodiment has prepared to be used for the read instruction RD and the WR that read instruction PRD and PWR and be used for operation usually of page operation, so the added command signal of multiport memory M response not only can be implemented page operation and can implement common operation.

The foregoing description has pointed to the example of the multiport memory of a multiplexed type in address that the present invention is used for the multiplexed address signal.But the invention is not restricted to these certain embodiments.For example, also can the present invention be used for the multiport memory of the non-multiplexed type in address of receiver address signal simultaneously.

The foregoing description has pointed to an example that the present invention is used to have the multiport memory M of two input/output end port PORT-A and PORT-B.But the invention is not restricted to these embodiment.For example, also can the present invention be used to have the multiport memory of 4 input/output end ports.In this situation, be provided with to such an extent that be equal to or greater than 4 times of operating cycle of storage core with the interval of added effective instruction ACT (according to regularly explanation).

In the above-described embodiments, the example to the multiport memory that the present invention is used to have synchronous dram storage core is described.But the invention is not restricted to the embodiment of this form.For example, also can the present invention be used to have the multiport memory of synchronous SRAM storage core.

Further, in above-mentioned multiport memory, can be with importing as command signal for the requirement of storage core operation.Such command signal and clock signal synchronously are added to the instruction terminal of an input/output end port.Effective instruction and indication that can this command signal be divided into a particular memory region that is used for activating storage block is at this storage area or implement read operation or implement the action command of write operation, and can add these instructions continuously.By the same token, also can be on time division basis one then a ground add address signal.Add on cycle that through the predetermined clock after adding effective instruction action command is fixed on read operation cycle and write cycles on the constant cycle.

If the storage unit of storage block is made up of the DRAM unit then needs refresh operation.For implementing refresh operation by the refresh address that is added in the address signal indication on any one input/output end port.This configuration can make the size of the control circuit in multiport memory reduce to minimum, thereby can reduce chip size.

The bit line of behind read operation and write operation, automatically implementing to be connected with storage unit resets to the precharge operation of predetermined potential.This makes accomplishes read operation in predetermined period of time of each operation of beginning and write operation becomes possibility.That is, can be fixed as tead cycle time and write cycle time constant.

And, can busy terminal be provided so that the output busy signal for each input/output end port.When the address signal that is added to an input/output end port is identical with the address signal that is added to another input/output end port and when carrying out storage operation for a back input/output end port, the output busy signal.Use this configuration, the controller that is connected with multiport memory readily appreciates that does not also implement desired operation.

Further, the invention is not restricted to these embodiment, and can make different variations and modification and do not depart from scope of the present invention.

For example, we are with reference in order synchronously only to have described the 1st to the 5th aspect of the present invention with the configuration on edge behind a forward position or.Yet for those those skilled in the art, obviously can easily change above-mentioned any one configuration, make it with in order to mate along both DDR (double data rate) operations synchronously with forward position and back.We have a mind to make so tangible change place within the scope of the invention.

The No.2000-387891 that the application on Dec 20th, 2000 submitted based on the japanese priority patent application that proposes to Jap.P. office; The No.2001-034361 that submit February 9 calendar year 2001; The No.2000-037547 that submit February 14 calendar year 2001; The No.2000-399052 that the No.2000-398893 that on Dec 27th, 2000 submitted and on Dec 27th, 2000 submit, we are with the full content of these patented claims as a reference here.

Claims (10)

1. semiconductor storage unit comprises:

Quantity is a plurality of outside ports of N, and each outside port all receives instruction;

Quantity is the multiple bus of N, and they are corresponding with each outside port;

A plurality of storage blocks, they are connected with N bar bus, and said storage block comprises the DRAM memory cell array;

An address comparison circuit, it is relatively by the address that is input to N the instruction accessing in each outside port; With

An arbiter; It confirms when said address comparison circuit detects the access of same storage block according to the address comparative result, carry out in the instruction of the same storage block of access which or which and do not carry out in the instruction of the same storage block of access which or which.

2. the described semiconductor storage unit of claim 1, definite result of given instruction is not carried out in wherein said arbiter response, and the signal of given instruction is not carried out in the output indication.

3. the described semiconductor storage unit of claim 2 is wherein indicated the signal of not carrying out given instruction from the port output corresponding with given instruction.

4. the described semiconductor storage unit of claim 1; Wherein said semiconductor storage unit comprises a refresh circuit; It confirms the timing of refresh of memory cells, and wherein in first pattern, response is input to the refreshing instruction refresh of memory cells of N at least one port in the outside port; In second pattern, in the periodic refreshing storage unit of said refresh circuit indication.

5. the described semiconductor storage unit of claim 4 wherein carries out second pattern when all N outside port all is in the deactivation status.

6. the described semiconductor storage unit of claim 4 further comprises the refresh address counter of the address that a generation will be refreshed, and wherein said refresh address counter response is counted the address from the refreshing instruction that said arbiter sends.

7. the described semiconductor storage unit of claim 1; In the wherein said storage block each all comprises a control circuit; The address detected result in a said bus that the response of said control circuit is corresponding with the storage block of said control circuit is from this bus signal that gets instruction.

8. the described semiconductor storage unit of claim 7, each in the wherein said storage block all further comprises a bus selection device, said bus selection device makes said this bus be connected with memory cell array.

9. the described semiconductor storage unit of claim 1, wherein each in N outside port all comprises:

A circuit, it offers a corresponding bus in the N bar bus with the data of serial received as parallel data; With

A circuit, the parallel data that it will a corresponding bus from N bar bus provides outputs to the device outside as serial data.

10. the described semiconductor storage unit of claim 9; The instruction that wherein is input to N each outside port comprises and reading instruction and write command; Said arbiter; Response will be said read instruction the input outside port timing and will be for the timing of last data item input outside port of the serial input data of said write command, in confirming to instruct which or which in will being performed and instructing which or which be not performed.

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