CN101894583A - Memory unit capable of saving circuit area - Google Patents
Memory unit capable of saving circuit area Download PDFInfo
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- CN101894583A CN101894583A CN2010102265297A CN201010226529A CN101894583A CN 101894583 A CN101894583 A CN 101894583A CN 2010102265297 A CN2010102265297 A CN 2010102265297A CN 201010226529 A CN201010226529 A CN 201010226529A CN 101894583 A CN101894583 A CN 101894583A
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Abstract
The invention relates to a memory unit capable of saving circuit area. The memory unit is coupled with a read line through a first transistor, and is controlled by a character line, wherein a second transistor is coupled between the first transistor and a power supply end; a third transistor is coupled with the second transistor, is controlled by a bit line, and controls connection/cut-off of the second transistor; and a fourth transistor is coupled with the third transistor and a write line, and is controlled by the character line. Therefore, four transistors form the memory unit to achieve the aim of saving the circuit area.
Description
Technical field
The invention relates to a kind of mnemon, it refers to a kind of mnemon of saving circuit area especially.
Background technology
Development along with the many-core systems single-chip, increasing internal memory will be integrated in the System on Chip/SoC to help the computing of each core, therefore exist on following chip in and must occupy most area, and become and influence very important factor of System on Chip/SoC usefulness, and will consume lot of energy; So the area and the power consumption thereof that how to effectively reduce internal memory must become a very important problem.
See also Fig. 1, be the circuit diagram of the mnemon of prior art.As shown in the figure, the mnemon of prior art comprises one first phase inverter 10 ', one second phase inverter 20 ' and an access port 30 '.The input end of first phase inverter 10 ' couples the output terminal of second phase inverter 20 '; The output terminal of first phase inverter 10 ' couples the input end of second phase inverter 20 ', access port 30 ' is coupled to second phase inverter 20 ' and a bit line (Bitline, BL), and with a character line (Wordline WL) couples mutually, and this access port 30 ' is a N type metal-oxide half field effect transistor (NMOS), therefore when bit line is noble potential, open at access port 30 ', will have a threshold voltage on access port 30 ', makes bit-line voltage reduce the effective voltage of mnemon; Therefore, see also Fig. 2, circuit diagram for the mnemon of another prior art, as shown in the figure, access port 30 ' is replaced by a P type metal-oxide half field effect transistor (PMOS), therefore when bit line is noble potential, after open at access port 30 ', the voltage of bit line will import in the storage device under the situation of not having consume.
General bit line reads and writes logical value in single-ended mnemon " 1 " time, bit line all will remain on high levle (High) earlier, and character line will conducting, and so, single-ended mnemon can't be learnt how bit line and character line move and read or writing logical value " 1 ".Therefore, designing mnemon can be according to the bit line of different accurate positions, and write data or reading of data, when mnemon reads, bit line must change the voltage quasi position low a little than voltage quasi position into, reads first phase inverter 10 ' and the stored data of second phase inverter 20 ' to see through access port 30 '; Write fashionablely when mnemon, bit line must change the accurate position of high voltage into, writes first phase inverter 10 ' and second phase inverter, 20 ' formed mnemon to see through access port 30 '.
Moreover, see also Fig. 3, be the circuit diagram of the mnemon of prior art.As shown in the figure, the mnemon 40 ' of prior art comprises a first transistor 42 ', one the 3rd phase inverter 44 ', a transistor seconds 46 ' and one the 4th phase inverter 48 '.One end of the first transistor 42 ' couples a data line D, and be controlled by a character line W, the input end of the 3rd phase inverter 44 ' couples the other end of the first transistor 42 ', one end of transistor seconds 46 ' couples the output terminal of the 3rd phase inverter 44 ', and be controlled by character line W, the input end of the 4th phase inverter 48 ' couples the other end of two-transistor 46 and the output terminal of the 3rd phase inverter 44 ', and the output terminal of the 4th phase inverter 48 ' couples the input end of the first transistor 42 ' and the 3rd phase inverter 44 '.Wherein, the 3rd phase inverter 44 ' comprises one the 3rd transistor 440 ' and one the 4th transistor 442 ', and the 4th phase inverter 48 ' comprises one the 5th transistor 480 ' and one the 6th transistor 482 '.Because the technology that inverter structure is known the knowledgeable usually for this technical field has and all known will be so will no longer add with explanation at this.
Connect described, the mnemon 40 ' of Fig. 3 is not when writing data, it is the low level signal that its character line W goes up signal, and make the first transistor 42 ' and transistor seconds 44 ' close (ending), at this moment, because the 3rd phase inverter 44 ' dock with two output terminal input ends in the 4th phase inverter 48 ', the anti-phase each other pinning of data that the N2 of data that the N1 of the 3rd phase inverter 44 ' holds and the 4th phase inverter 48 ' is held.Mnemon 40 ' is if will write data, promptly write data when mnemon 40 ' " 1 " time, signal on the character line W is high levle signal (promptly " 1 "), make the first transistor 42 ' and transistor seconds 46 ' conducting, and the signal on the data line D is " 1 ", and the signal on the bit line DB is " 0 ".After mnemon 40 ' writes data and finishes, the signal on the character line W will change the low level signal into, and the first transistor 42 ' and transistor seconds 44 ', and data is pinned.
Only if, generation evolution along with sci-tech product, the dealer is more and more higher to the storage requirements of mnemon, the competitive pressure of price and unit capacity is also increasing, so, the less storage element of the unit area of mnemon is also just more and more important, so, use few more transistor make mnemon also as the dealer will towards one of target.
Therefore, how to propose a kind of novel mnemon of saving circuit area at the problems referred to above, it uses less transistor to be combined into mnemon, makes and can solve the above problems.
Summary of the invention
The objective of the invention is to, be to provide a kind of mnemon of saving circuit area, it uses four transistors can form a mnemon, to reach the purpose of saving circuit area.
To achieve the above object, the present invention is a kind of mnemon of saving circuit area, and it comprises:
One the first transistor couples a read line, and is controlled by a character line;
One transistor seconds couples between this first transistor and the power end;
One the 3rd transistor couples this transistor seconds, and is controlled by a bit line, this transistor seconds conduction and cut-off of the 3rd transistor controls; And
One the 4th transistor couples the 3rd transistor AND gate one writing line, and is controlled by this character line.
Among the present invention, more comprise:
One the 5th transistor couples this read line and a power end, and is controlled by a reading signal.
Among the present invention, wherein the 5th transistor is a P type field-effect transistor.
Among the present invention, more comprise:
One the 5th transistor couples this read line and a low power end, and is controlled by a reading signal.
Among the present invention, wherein the 5th transistor is a N type field-effect transistor.
Among the present invention, wherein this character line and this bit line are this first transistor of conducting, the 3rd transistor AND gate the 4th transistor, to write data between this second switch and the 3rd switch.
Among the present invention, this first switch of this character line conducting wherein is to read stored data between this transistor seconds and the 3rd transistor.
Among the present invention, it couples a control circuit, and this control circuit couples this character line, this bit line, this read line and this writing line, writes data or reading of data with control mnemon.
Among the present invention, wherein this control circuit comprises:
One column decoder couples this character line, to control this mnemon conduction and cut-off;
One line decoder couples this bit line, this read line and this writing line; And
One control module couples this column decoder and this line decoder, and produces a controlling signal, and transmits this controlling signal to this column decoder and this line decoder, reads or write data to control this mnemon.
Among the present invention, wherein this first transistor, this transistor seconds, the 3rd transistor AND gate the 4th transistor are a N type field-effect transistor.
Among the present invention, wherein this first transistor, this transistor seconds, the 4th transistorized substrate of the 3rd transistor AND gate couple this power end.
The beneficial effect that the present invention has: the present invention can form a mnemon by using four transistors, to reach the purpose of saving circuit area.
Description of drawings
Fig. 1 is the circuit diagram of the mnemon of prior art;
Fig. 2 is the circuit diagram of the mnemon of another prior art;
Fig. 3 is the circuit diagram of the mnemon of another prior art;
Fig. 4 is the circuit diagram of the mnemon of a preferred embodiment of the present invention;
Fig. 5 A is the action synoptic diagram that the mnemon of a preferred embodiment of the present invention writes data;
Fig. 5 B is the sequential chart of Fig. 4 A figure of a preferred embodiment of the present invention;
Fig. 6 A is the action synoptic diagram of the mnemon reading of data of another preferred embodiment of the present invention;
Fig. 6 B is the sequential chart of Fig. 5 A of a preferred embodiment of the present invention;
Fig. 7 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention;
Fig. 7 B is the sequential chart of Fig. 7 A of a preferred embodiment of the present invention;
Fig. 8 is the circuit diagram of the chip array mnemon of a preferred embodiment of the present invention;
Fig. 9 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention;
Fig. 9 B is the sequential chart of Fig. 9 A of a preferred embodiment of the present invention;
Figure 10 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention; And
Figure 10 B is the sequential chart of Fig. 9 A of a preferred embodiment of the present invention.
[figure number is to as directed]
Prior art:
10 ' first phase inverter, 20 ' second phase inverter
30 ' access port, 40 ' mnemon
42 ' the first transistor 44 ' the 3rd phase inverter
440 ' the 3rd transistor 442 ' the 4th transistor
46 ' transistor seconds 48 ' the 4th phase inverter
480 ' the 5th transistor 482 ' the 6th transistor
The present invention:
1 mnemon, 10 the first transistors
12 transistor secondses 13 the 6th transistor
14 the 3rd transistors 16 the 4th transistor
18 the 5th transistors, 20 control circuits
22 column decoders, 24 line decoders
26 control modules, 3 mnemons
30 the 7th transistors 32 the 8th transistor
33 the tenth two-transistors 34 the 9th transistor
36 the tenth transistor 38 the 11 transistors
Embodiment
Further understand and understanding for making architectural feature of the present invention and the effect reached had, cooperate detailed explanation, be described as follows in order to preferred embodiment and accompanying drawing:
See also Fig. 4, the circuit diagram of the mnemon of a preferred embodiment of the present invention.As shown in the figure, the mnemon 1 of saving circuit area of the present invention comprises a first transistor 10, a transistor seconds 12, one the 3rd transistor 14 and one the 4th transistor 16.The first transistor 10 couples a read line DR, and be controlled by a character line W, transistor seconds 12 is coupled to a first transistor 10 and a low power end VSS, the 3rd transistor 14 is coupled to transistor seconds 12, and be controlled by a bit line B, the 3rd transistor 14 control transistor secondses 12 conduction and cut-off, the 4th transistor 16 couples the 3rd transistor 14 and a writing line DW, and is controlled by character line W.So, the present invention is by using four transistors can form mnemon 1, to reach the purpose of saving circuit area.Wherein, the first transistor 10, transistor seconds 12, the 3rd transistor 14 and the 4th transistor 16 are a N type field-effect transistor (NMOS).Below can how to carry out reading or write and describing of data, so this part is not described earlier in this at mnemon 1 of the present invention.
Moreover the mnemon 1 of saving circuit area of the present invention more comprises a control circuit 20.Control circuit 20 couples character line W, bit line B, read line DR and writing line DW, writes data or reading of data with control mnemon 1.Below how to control at control circuit 20 that mnemon 1 writes data or reading of data describes.
See also Fig. 5 A and Fig. 5 B, write the action synoptic diagram and the sequential chart of data for the mnemon of a preferred embodiment of the present invention.As shown in the figure, mnemon 1 is fashionable as if carrying out writing of data, control circuit 20 meeting conducting character line W and bit line B, even the signal of character line W and bit line B is the high levle signal, make the first transistor 10, the 3rd transistor 14 and 16 conductings of the 4th transistor, at this moment, control circuit 20 can be gone up in writing line DW and transmit a storage data to the storage end SD between transistor seconds 20 and the 3rd transistor 14, to finish the storage of data.
See also Fig. 6 A and Fig. 6 B, be the action synoptic diagram and the sequential chart of mnemon 1 reading of data of a preferred embodiment of the present invention.As shown in the figure, the mnemon 1 of saving circuit area of the present invention has more comprised one the 5th transistor 18.The 5th transistor 18 couples a read line DR and a power end VDD, and is controlled by a reading signal XPC, and in this embodiment, the 5th transistor 18 is a P type field-effect transistor (PMOS).Certainly can also be a N type field-effect transistor (NMOS), but its control method is described opposite in present embodiment, this knows usually that for knowing to have in this technical field the knowledgeable all knows, so no longer given unnecessary details.If mnemon 1 is will carry out the reading of data the time, control circuit 20 transmits reading signal XPC to the five transistors 18, making 18 conductings of the 5th transistor and being positioned at signal on the read line DR is high levle signal (be digital signal " 1 "), be the reading signal XPC that control circuit 20 produces the low level signal, and reading signal XPC to the five transistors 18 of transmission low level signal, and conducting the 5th transistor 18, make power end VDD that the high levle signal is provided, and transmit the high levle signal to read line DR, make the signal that is positioned at read line DR change into high levle signal (be digital signal " 1 "), afterwards, control circuit 20 conducting character line W, the signal that is about to be positioned on the character line W is changed into the high levle signal, but not conducting bit line B, at this moment, be positioned at the signal (being the stored storage data of mnemon) that stores end SD and with the first transistor 10 storage data be sent to control circuit 20, to finish reading of data via transistor seconds 12.
When being positioned at the storage data that stores end SD is digital signal " 1 " time, the signal that reads end DR will be changed into low level signal (be digital signal " 0 "); When being positioned at the storage data that stores end SD is digital signal " 0 " time, the signal that reads end DR will remain high levle signal (be digital signal " 1 "), and so, mnemon 1 of the present invention can read out and be positioned at the storage data that stores end SD.
See also Fig. 7 A and Fig. 7 B, be the circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of present embodiment and Fig. 4 is that the control circuit 20 of present embodiment has comprised a read/write end DR/DW, integration is read end DR and is write end DW, with the pin count of minimizing control circuit 20, and the area of saving control circuit 20, and then escapable cost.Moreover one the 6th transistor 13 of present embodiment replaces transistor seconds 12, and the 6th transistor 13 is a P type field-effect transistor (PMOS).Among this embodiment, how mnemon 1 carries out reading and writing of data, shown in Fig. 7 B, it in like manner writes and reads in the data shown in above-mentioned Fig. 5 B and Fig. 6 B, and should under technical field have and know that usually the knowledgeable is easily in the sequential chart of Fig. 5 B and Fig. 6 B, and learn the sequential chart shown in Fig. 7 B, so, no longer be described in detail in this applicant at the sequential chart of Fig. 7 B.
See also Fig. 8, be the circuit diagram of the chip array mnemon 1 of a preferred embodiment of the present invention.As shown in the figure, the control circuit 20 in the mnemon 1 of saving circuit area of the present invention comprises a column decoder 22, a line decoder 24 and a control module 26.Present embodiment uses a plurality of mnemons.Column decoder 22 couples character line W, and to control those mnemon 1 conduction and cut-off, promptly column decoder 22 couples the character line W of those mnemons 1, to control mnemon 1 conduction and cut-off by control character line W conduction and cut-off.Line decoder 24 couples bit line B, read line DR and writing line DW, and control bit line B, read line DR and writing line DW conduction and cut-off, and cooperation control character line W conduction and cut-off and control mnemon 1 and carry out writing or reading of data.Control module 26 couples column decoder 22 and line decoder 24, and produces a controlling signal, and transmits controlling signal to column decoder 22 and line decoder 24, reads or writes with control mnemon 1.
In addition, the controlling signal that produced of the control module 26 of present embodiment comprises one and writes signal WP, and write data XDI, a reading signal XPC, a reading of data DRO and a bit line controlling signal BP.Desire to carry out data when mnemon 1 and write fashionablely, control module 26 produces earlier and transmits and writes signal WP to the plural row decoding unit 240 of line decoder 24, will write data XDI again and see through those row decoding unit 240 and be sent in those mnemons 1.When mnemon 1 is desired to carry out data read, control module 26 produces earlier and transmits reading signal XPC to those row decoding unit 240 of line decoder 24, those row decoding unit 240 read the reading of data DRO of those mnemons 1 according to reading signal XPC, and reading of data DRO is back to control module 26.Wherein, control module 26 generations and traffic bit line traffic control signal BP are to those row decoding unit 240 of line decoder 24, to control the bit line B conduction and cut-off of those mnemons 1.
See also Fig. 9 A and Fig. 9 B, be the circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of present embodiment and Fig. 3 is that one the 7th transistor 30, one the 8th transistor 32, one the 9th transistor 34 and 1 the tenth transistor 36 of present embodiment is a P type field-effect transistor.And that the mnemon 3 of present embodiment desires to carry out the method for the control of reading with writing the 7th transistor 30, the 8th transistor 32, the 9th transistor 34 and the tenth transistor 36 of data is opposite with Fig. 5 B with the 4th B figure, its control method is roughly the same, so no longer add to state to praise at this.In addition, present embodiment comprises 1 the 11 transistor 38, and its control mnemon 3 is carried out the usefulness of reading of data, and it can be P type field-effect transistor or N type field-effect transistor.
In addition, see also Figure 10 A and Figure 10 B, be the circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of present embodiment and Fig. 9 A is that the control circuit 20 of present embodiment has comprised a read/write end DR/DW, integration is read end DR and is write end DW, with the pin count of minimizing control circuit 20, and the area of saving control circuit 20, and then escapable cost.Moreover 1 the tenth two-transistor 33 of present embodiment replaces the 8th transistor 32, and the tenth two-transistor 33 is a N type field-effect transistor (NMOS).Among this embodiment, how mnemon 3 carries out reading and writing of data, shown in Figure 10 B, it in like manner writes and reads in the data shown in above-mentioned Fig. 9 B, and should under technical field have and know that usually the knowledgeable is easily in the sequential chart of Fig. 9 B, and learn the sequential chart shown in Figure 10 B, so, no longer be described in detail in this applicant at the sequential chart of Figure 10 B.
In sum, the mnemon of saving circuit area of the present invention, it couples a read line by a first transistor, and be controlled by a character line, and a transistor seconds couples between a first transistor and the power end, and one the 3rd transistor couples transistor seconds, and be controlled by a bit line, this transistor seconds conduction and cut-off of the 3rd transistor controls, one the 4th transistor couple the 3rd transistor AND gate one writing line, and are controlled by character line.So, the present invention uses four transistors can form a mnemon, to reach the purpose of saving circuit area.
In sum, it only is a preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, all equalizations of doing according to the described shape of claim scope of the present invention, structure, feature and spirit change and modify, and all should be included in the claim scope of the present invention.
Claims (11)
1. mnemon of saving circuit area is characterized in that it comprises:
One the first transistor couples a read line, and is controlled by a character line;
One transistor seconds couples between this first transistor and the power end;
One the 3rd transistor couples this transistor seconds, and is controlled by a bit line, this transistor seconds conduction and cut-off of the 3rd transistor controls; And
One the 4th transistor couples the 3rd transistor AND gate one writing line, and is controlled by this character line.
2. mnemon as claimed in claim 1 is characterized in that, more comprises:
One the 5th transistor couples this read line and a power end, and is controlled by a reading signal.
3. mnemon as claimed in claim 2 is characterized in that, wherein the 5th transistor is a P type field-effect transistor.
4. mnemon as claimed in claim 1 is characterized in that, more comprises:
One the 5th transistor couples this read line and a low power end, and is controlled by a reading signal.
5. mnemon as claimed in claim 4 is characterized in that, wherein the 5th transistor is a N type field-effect transistor.
6. mnemon as claimed in claim 1 is characterized in that, wherein this character line and this bit line are this first transistor of conducting, the 3rd transistor AND gate the 4th transistor, to write data between this second switch and the 3rd switch.
7. mnemon as claimed in claim 1 is characterized in that, this first switch of this character line conducting wherein is to read stored data between this transistor seconds and the 3rd transistor.
8. mnemon as claimed in claim 1 is characterized in that it couples a control circuit, and this control circuit couples this character line, this bit line, this read line and this writing line, writes data or reading of data with control mnemon.
9. mnemon as claimed in claim 8 is characterized in that, wherein this control circuit comprises:
One column decoder couples this character line, to control this mnemon conduction and cut-off;
One line decoder couples this bit line, this read line and this writing line; And
One control module couples this column decoder and this line decoder, and produces a controlling signal, and transmits this controlling signal to this column decoder and this line decoder, reads or write data to control this mnemon.
10. mnemon as claimed in claim 1 is characterized in that, wherein this first transistor, this transistor seconds, the 3rd transistor AND gate the 4th transistor are a N type field-effect transistor.
11. mnemon as claimed in claim 10 is characterized in that, wherein this first transistor, this transistor seconds, the 4th transistorized substrate of the 3rd transistor AND gate couple this power end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010226529.7A CN101894583B (en) | 2010-07-08 | 2010-07-08 | Save the mnemon of circuit area |
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| CN201010226529.7A CN101894583B (en) | 2010-07-08 | 2010-07-08 | Save the mnemon of circuit area |
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| CN101894583B CN101894583B (en) | 2016-03-02 |
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| US20020024873A1 (en) * | 1994-05-11 | 2002-02-28 | Shigeki Tomishima | Dynamic semiconductor memory device having excellent charge retention characteristics |
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