CN101894583B - Save the mnemon of circuit area - Google Patents

Save the mnemon of circuit area Download PDF

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Publication number
CN101894583B
CN101894583B CN201010226529.7A CN201010226529A CN101894583B CN 101894583 B CN101894583 B CN 101894583B CN 201010226529 A CN201010226529 A CN 201010226529A CN 101894583 B CN101894583 B CN 101894583B
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transistor
mnemon
line
couples
reading
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CN101894583A (en
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廖敏男
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Sitronix Technology Corp
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Sitronix Technology Corp
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Abstract

The present invention relates to a kind of mnemon of saving circuit area, it couples a reading line by a first transistor, and be controlled by a character line, one transistor seconds couples between the first transistor and a power end, one third transistor couples transistor seconds, and is controlled by a bit line, and this third transistor controls this transistor seconds conduction and cut-off, one the 4th transistor couples third transistor and one writes line, and is controlled by character line.So, the present invention uses four transistors can form a mnemon, to reach the object of saving circuit area.

Description

Save the mnemon of circuit area
Technical field
The invention relates to a kind of mnemon, its espespecially a kind of mnemon of saving circuit area.
Background technology
Along with the development of many-core systems single-chip, increasing internal memory will be integrated in System on Chip/SoC to help the computing of each core, therefore exist on following chip and must occupy most area, and become the very important factor of influential system chip usefulness one, and a large amount of energy will be consumed; So how effectively reducing the area of internal memory and power consumption thereof must become a very important problem.
Referring to Fig. 1, is the circuit diagram of the mnemon of prior art.As shown in the figure, the mnemon of prior art comprises one first phase inverter 10 ', one second phase inverter 20 ' and accesses port 30 '.The input end of the first phase inverter 10 ' couples the output terminal of the second phase inverter 20 '; The output terminal of the first phase inverter 10 ' couples the input end of the second phase inverter 20 ', access port 30 ' is coupled to the second phase inverter 20 ' and a bit line (Bitline, BL), and with a character line (Wordline, WL) couple mutually, this access port 30 ' is a N-type metal-oxide half field effect transistor (NMOS), therefore when bit line is noble potential, access port 30 ' is opened, a threshold voltage will be had across on access port 30 ', bit-line voltage is reduced the effective voltage of mnemon; Therefore, see also Fig. 2, for the circuit diagram of the mnemon of another prior art, as shown in the figure, access port 30 ' replace by the P type metal-oxide half field effect transistor (PMOS), therefore, when bit line is noble potential, after access port 30 ' is opened, the voltage of bit line imports into when nothing is consumed in storage device.
General bit line carries out reading and writing logical value in single-ended mnemon " 1 " time, bit line all will first remain on high levle (High), and character line will conducting, so, single-ended mnemon cannot learn how action is carrying out reading or writing logical value for bit line and character line " 1 ".Therefore, designing mnemon can according to the bit line of different level, and carry out write data or read data, when mnemon reads, bit line must change the voltage quasi position low a little compared with voltage quasi position into, to read the data stored by the first phase inverter 10 ' and the second phase inverter 20 ' through access port 30 '; When mnemon writes, bit line must change high voltage level into, to write the mnemon that the first phase inverter 10 ' and the second phase inverter 20 ' are formed through access port 30 '.
Moreover referring to Fig. 3, is the circuit diagram of the mnemon of prior art.As shown in the figure, the mnemon 40 ' of prior art comprises a first transistor 42 ', one the 3rd phase inverter 44 ', a transistor seconds 46 ' and one the 4th phase inverter 48 '.One end of the first transistor 42 ' couples a data line D, and be controlled by a character line W, the input end of the 3rd phase inverter 44 ' couples the other end of the first transistor 42 ', one end of transistor seconds 46 ' couples the output terminal of the 3rd phase inverter 44 ', and be controlled by character line W, the input end of the 4th phase inverter 48 ' couples the other end of two-transistor 46 and the output terminal of the 3rd phase inverter 44 ', and the output terminal of the 4th phase inverter 48 ' couples the input end of the first transistor 42 ' and the 3rd phase inverter 44 '.Wherein, the 3rd phase inverter 44 ' comprises a third transistor 440 ' and one the 4th transistor 442 ', and the 4th phase inverter 48 ' comprises one the 5th transistor 480 ' and one the 6th transistor 482 '.Due to for this technical field has, technology that inverter structure knows that the knowledgeable all knows usually, so will no longer be illustrated at this more.
Described in connecting, the mnemon 40 ' of Fig. 3 is not when writing data, on its character line W, signal is low level signal, and make the first transistor 42 ' and transistor seconds 44 ' close (cut-off), now, because the 3rd phase inverter 44 ' docks with two output terminal input ends in the 4th phase inverter 48 ', the data anti-phase pinning each other that the data that the N1 of the 3rd phase inverter 44 ' is held and the N2 of the 4th phase inverter 48 ' hold.Mnemon 40 ' is to write data, namely when mnemon 40 ' writes data " 1 " time, signal on character line W is high levle signal (namely " 1 "), make the first transistor 42 ' and transistor seconds 46 ' conducting, and the signal on data line D is " 1 ", and the signal on bit line DB is " 0 ".After mnemon 40 ' write data complete, the signal on character line W will change low level signal into, and the first transistor 42 ' and transistor seconds 44 ', and data is pinned.
If only, along with the generation evolution of sci-tech product, the storage requirements of dealer to mnemon is more and more higher, the competitive pressure of price and unit capacity is also increasing, so, the storage element that the unit area of mnemon is less is also just more and more important, so, use fewer transistor make mnemon also for dealer will towards one of target.
Therefore, how proposing for the problems referred to above the mnemon that a kind of novelty saves circuit area, it uses less transistor combination to become mnemon, makes to solve the above problems.
Summary of the invention
The object of the invention is to, be to provide a kind of mnemon of saving circuit area, it uses four transistors can form a mnemon, to reach the object of saving circuit area.
To achieve the above object, the present invention is a kind of mnemon of saving circuit area, and it comprises:
One the first transistor, couples a reading line, and is controlled by a character line;
One transistor seconds, couples between this first transistor and a power end;
One third transistor, couples this transistor seconds, and is controlled by a bit line, and this third transistor controls this transistor seconds conduction and cut-off; And
One the 4th transistor, couples this third transistor and and writes line, and be controlled by this character line;
Wherein, this the first transistor, this transistor seconds, this third transistor and the 4th transistor are a N-type field-effect transistor or a P type field-effect transistor, when this first transistor, this transistor seconds, this third transistor and the 4th transistor are this N-type field-effect transistor, this power end is a low power end, when this first transistor, this transistor seconds, this third transistor and the 4th transistor are this P type field-effect transistor, this power end is a high power end.
In the present invention, more comprise:
One the 5th transistor, couples this reading line and a power end, and is controlled by a reading signal.
In the present invention, wherein the 5th transistor is a P type field-effect transistor.
In the present invention, more comprise:
One the 5th transistor, couples this reading line and a low power end, and is controlled by a reading signal.
In the present invention, wherein the 5th transistor is a N-type field-effect transistor.
In the present invention, wherein this character line and this bit line are this first transistor of conducting, this third transistor and the 4th transistor, to write data between this transistor seconds and this third transistor.
In the present invention, wherein this this first transistor of character line conducting, to read data stored between this transistor seconds and this third transistor.
In the present invention, it couples a control circuit, and this control circuit couples this character line, this bit line, this reading line and this write line, to control mnemon write data or to read data.
In the present invention, wherein this control circuit comprises:
One column decoder, couples this character line, to control this mnemon conduction and cut-off;
One line decoder, couples this bit line, this reading line and this write line; And
One control module, couples this column decoder and this line decoder, and produces a control signal, and transmits this control signal to this column decoder and this line decoder, carries out reading or writing data to control this mnemon.
In the present invention, wherein the substrate of this first transistor, this transistor seconds, this third transistor and the 4th transistor couples this power end.
The beneficial effect that the present invention has: the present invention can form a mnemon by use four transistors, to reach the object of saving circuit area.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the mnemon of prior art;
Fig. 2 is the circuit diagram of the mnemon of another prior art;
Fig. 3 is the circuit diagram of the mnemon of another prior art;
Fig. 4 is the circuit diagram of the mnemon of a preferred embodiment of the present invention;
Fig. 5 A is the action schematic diagram of the mnemon write data of a preferred embodiment of the present invention;
Fig. 5 B is the sequential chart of Fig. 4 A figure of a preferred embodiment of the present invention;
Fig. 6 A is the action schematic diagram of the mnemon reading data of another preferred embodiment of the present invention;
Fig. 6 B is the sequential chart of Fig. 5 A of a preferred embodiment of the present invention;
Fig. 7 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention;
Fig. 7 B is the sequential chart of Fig. 7 A of a preferred embodiment of the present invention;
Fig. 8 is the circuit diagram of the chip array mnemon of a preferred embodiment of the present invention;
Fig. 9 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention;
Fig. 9 B is the sequential chart of Fig. 9 A of a preferred embodiment of the present invention;
Figure 10 A is the circuit diagram of the mnemon of another preferred embodiment of the present invention; And
Figure 10 B is the sequential chart of Fig. 9 A of a preferred embodiment of the present invention.
[figure number is to as directed]
Prior art:
10 ' first phase inverter 20 ' second phase inverter
30 ' access port 40 ' mnemon
42 ' the first transistor 44 ' the 3rd phase inverter
440 ' third transistor 442 ' the 4th transistor
46 ' transistor seconds 48 ' the 4th phase inverter
480 ' the 5th transistor 482 ' the 6th transistor
The present invention:
1 mnemon 10 the first transistor
12 transistor secondses 13 the 6th transistor
14 third transistor 16 the 4th transistor
18 the 5th transistor 20 control circuits
22 column decoder 24 line decoders
26 control module 3 mnemons
30 the 7th transistor 32 the 8th transistors
33 the tenth two-transistor 34 the 9th transistors
36 the tenth transistor 38 the 11 transistors
Embodiment
For making to have a better understanding and awareness architectural feature of the present invention and effect of reaching, coordinating detailed description in order to preferred embodiment and accompanying drawing, being described as follows:
Refer to Fig. 4, the circuit diagram of the mnemon of a preferred embodiment of the present invention.As shown in the figure, the mnemon 1 of saving circuit area of the present invention comprises the first transistor 10, transistor seconds 12, third transistor 14 and one the 4th transistor 16.The first transistor 10 couples a reading line DR, and be controlled by a character line W, transistor seconds 12 is coupled to the first transistor 10 and a low power end VSS, third transistor 14 is coupled to transistor seconds 12, and be controlled by a bit line B, third transistor 14 controls transistor seconds 12 conduction and cut-off, and the 4th transistor 16 couples third transistor 14 and and writes line DW, and is controlled by character line W.So, the present invention can form mnemon 1 by use four transistors, to reach the object of saving circuit area.Wherein, the first transistor 10, transistor seconds 12, third transistor 14 and the 4th transistor 16 are a N-type field-effect transistor (NMOS).Below how carry out the reading of data for mnemon 1 of the present invention or write is described, therefore first this part is not described in this.
Moreover the mnemon 1 of saving circuit area of the present invention more comprises a control circuit 20.Control circuit 20 couples character line W, bit line B, reads line DR and write line DW, carries out write data to control mnemon 1 or reads data.How to control mnemon 1 for control circuit 20 below to carry out write data or read data being described.
Seeing also Fig. 5 A and Fig. 5 B, is action schematic diagram and the sequential chart of the mnemon write data of a preferred embodiment of the present invention.As shown in the figure, when mnemon 1 is to carry out the write of data, control circuit 20 meeting conducting character line W and bit line B, even if the signal of character line W and bit line B is high levle signal, make the first transistor 10, third transistor 14 and the 4th transistor 16 conducting, now, control circuit 20 can on write line DW transmission one storage data to the storage end SD between transistor seconds 12 and third transistor 14, to complete the storage of data.
See also Fig. 6 A and Fig. 6 B, the mnemon 1 for a preferred embodiment of the present invention reads action schematic diagram and the sequential chart of data.As shown in the figure, the mnemon 1 of saving circuit area of the present invention more contains one the 5th transistor 18.5th transistor 18 couples and reads a line DR and power end VDD, and is controlled by a reading signal XPC, and in this embodiment, the 5th transistor 18 is a P type field-effect transistor (PMOS).Certainly can also be a N-type field-effect transistor (NMOS), but its control method is in contrary described in the present embodiment, for knowing in this technical field to have, this knows that the knowledgeable all knows usually, therefore no longer repeated.When mnemon 1 is to carry out the reading of data, control circuit 20 transmits reading signal XPC to the 5th transistor 18, making the 5th transistor 18 conducting and being positioned at the signal read on line DR is high levle signal (i.e. digital signal " 1 "), namely control circuit 20 produces the reading signal XPC of low level signal, and the reading signal XPC transmitting low level signal is to the 5th transistor 18, and conducting the 5th transistor 18, power end VDD is made to provide high levle signal, and transmit high levle signal to reading line DR, make to be positioned at the signal reading line DR and change into high levle signal (i.e. digital signal " 1 "), afterwards, control circuit 20 conducting character line W, be about to the signal be positioned on character line W and change into high levle signal, but not conducting bit line B, now, be positioned at the signal (storage data namely stored by mnemon) storing end SD and storage data be sent to control circuit 20 via transistor seconds 12 and the first transistor 10, to complete the reading of data.
When the storage data being positioned at storage end SD is digital signal " 1 " time, the signal reading end DR will change into low level signal (i.e. digital signal " 0 "); When the storage data being positioned at storage end SD is digital signal " 0 " time, the signal reading end DR will remain high levle signal (i.e. digital signal " 1 "), so, mnemon 1 of the present invention can read out the storage data being positioned at and storing and hold SD.
Seeing also Fig. 7 A and Fig. 7 B, is circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of the present embodiment and Fig. 4, is that the control circuit 20 of the present embodiment contains a read/write end DR/DW, integrate to read end DR and write and hold DW, to reduce the pin count of control circuit 20, and save the area of control circuit 20, and then escapable cost.Moreover one the 6th transistor 13 of the present embodiment replaces transistor seconds 12, and the 6th transistor 13 is a P type field-effect transistor (PMOS).In this embodiment, how mnemon 1 carries out reading and the write of data, as shown in Figure 7 B, it in like manner writes in the data shown in above-mentioned Fig. 5 B and Fig. 6 B and reads, and this art has and usually knows the knowledgeable easily in the sequential chart of Fig. 5 B and Fig. 6 B, and learn the sequential chart shown in Fig. 7 B, therefore, be no longer described in detail for the sequential chart of Fig. 7 B in this applicant.
Seeing also Fig. 8, is the circuit diagram of the chip array mnemon 1 of a preferred embodiment of the present invention.As shown in the figure, the control circuit 20 in the mnemon 1 of saving circuit area of the present invention comprises column decoder 22, line decoder 24 and a control module 26.The present embodiment uses a plurality of mnemon.Column decoder 22 couples character line W, and to control those mnemon 1 conduction and cut-off, namely column decoder 22 couples the character line W of those mnemons 1, to control mnemon 1 conduction and cut-off by control character line W conduction and cut-off.Line decoder 24 couples bit line B, reads line DR and write line DW, and controls bit line B, reading line DR and write line DW conduction and cut-off, and coordinates control character line W conduction and cut-off and control write or the reading that mnemon 1 carries out data.Control module 26 couples column decoder 22 and line decoder 24, and produces a control signal, and transfer control signal is to column decoder 22 and line decoder 24, carries out reading or writing to control mnemon 1.
In addition, the control signal that the control module 26 of the present embodiment produces comprises a write signal WP, write data XDI, a reading signal XPC, reads data DRO and a bit line controls signal BP.When mnemon 1 is for carrying out data write, control module 26 first produces and after transmitting and writing signal WP to the plural row decoding unit 240 of line decoder 24, then is sent in those mnemons 1 through those row decoding unit 240 by write data XDI.When mnemon 1 is for carrying out digital independent, control module 26 first produces and after transmitting reading signal XPC to those row decoding unit 240 of line decoder 24, those row decoding unit 240 read the reading data DRO of those mnemons 1 according to reading signal XPC, and reading data DRO is back to control module 26.Wherein, control module 26 produce and traffic bit line traffic control signal BP to those row decoding unit 240 of line decoder 24, to control the bit line B conduction and cut-off of those mnemons 1.
Seeing also Fig. 9 A and Fig. 9 B, is circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of the present embodiment and Fig. 3, is that one the 7th transistor 30, the 8th transistor 32, the 9th transistor 34 of the present embodiment and 1 the tenth transistor 36 are a P type field-effect transistor.And the mnemon 3 of the present embodiment is schemed contrary with Fig. 5 B for the method for control the 7th transistor 30 of the reading with write of carrying out data, the 8th transistor 32, the 9th transistor 34 and the tenth transistor 36 and the 4th B, its control method is roughly the same, therefore no longer adds to praise to state at this.In addition, the present embodiment comprises 1 the 11 transistor 38, and it controls the use that mnemon 3 carries out reading data, and it can be P type field-effect transistor or N-type field-effect transistor.
In addition, seeing also Figure 10 A and Figure 10 B, is circuit diagram and the sequential chart of the mnemon of another preferred embodiment of the present invention.As shown in the figure, the embodiment difference of the present embodiment and Fig. 9 A, is that the control circuit 20 of the present embodiment contains a read/write end DR/DW, integrate to read end DR and write and hold DW, to reduce the pin count of control circuit 20, and save the area of control circuit 20, and then escapable cost.Moreover 1 the tenth two-transistor 33 of the present embodiment replaces the 8th transistor 32, and the tenth two-transistor 33 is a N-type field-effect transistor (NMOS).In this embodiment, how mnemon 3 carries out reading and the write of data, as shown in Figure 10 B, it is in like manner in the data write shown in above-mentioned Fig. 9 B and reading, and this art has and usually knows the knowledgeable easily in the sequential chart of Fig. 9 B, and learn the sequential chart shown in Figure 10 B, therefore, be no longer described in detail for the sequential chart of Figure 10 B in this applicant.
In sum, the mnemon of saving circuit area of the present invention, it couples a reading line by a first transistor, and being controlled by a character line, a transistor seconds couples between the first transistor and a power end, and a third transistor couples transistor seconds, and be controlled by a bit line, this third transistor controls this transistor seconds conduction and cut-off, and one the 4th transistor couples third transistor and writes line, and is controlled by character line.So, the present invention uses four transistors can form a mnemon, to reach the object of saving circuit area.
In sum, be only a preferred embodiment of the present invention, not be used for limiting scope of the invention process, all equalizations of doing according to shape, structure, feature and the spirit described in the claims in the present invention scope change and modify, and all should be included in right of the present invention.

Claims (10)

1. save a mnemon for circuit area, it is characterized in that, it comprises:
One the first transistor, couples a reading line, and is controlled by a character line;
One transistor seconds, couples between this first transistor and a power end;
One third transistor, couples this transistor seconds, and is controlled by a bit line, and this third transistor controls this transistor seconds conduction and cut-off; And
One the 4th transistor, couples this third transistor and and writes line, and be controlled by this character line;
Wherein, this the first transistor, this transistor seconds, this third transistor and the 4th transistor are a N-type field-effect transistor or a P type field-effect transistor, when this first transistor, this transistor seconds, this third transistor and the 4th transistor are this N-type field-effect transistor, this power end is a low power end, when this first transistor, this transistor seconds, this third transistor and the 4th transistor are this P type field-effect transistor, this power end is a high power end.
2. mnemon as claimed in claim 1, is characterized in that, more comprise:
One the 5th transistor, couples this reading line and a power end, and is controlled by a reading signal.
3. mnemon as claimed in claim 2, it is characterized in that, wherein the 5th transistor is a P type field-effect transistor.
4. mnemon as claimed in claim 1, is characterized in that, more comprise:
One the 5th transistor, couples this reading line and a low power end, and is controlled by a reading signal.
5. mnemon as claimed in claim 4, it is characterized in that, wherein the 5th transistor is a N-type field-effect transistor.
6. mnemon as claimed in claim 1, it is characterized in that, wherein this character line and this bit line are this first transistor of conducting, this third transistor and the 4th transistor, to write data between this transistor seconds and this third transistor.
7. mnemon as claimed in claim 1, is characterized in that, wherein this this first transistor of character line conducting, to read data stored between this transistor seconds and this third transistor.
8. mnemon as claimed in claim 1, it is characterized in that, it couples a control circuit, and this control circuit couples this character line, this bit line, this reading line and this write line, to control mnemon write data or to read data.
9. mnemon as claimed in claim 8, it is characterized in that, wherein this control circuit comprises:
One column decoder, couples this character line, to control this mnemon conduction and cut-off;
One line decoder, couples this bit line, this reading line and this write line; And
One control module, couples this column decoder and this line decoder, and produces a control signal, and transmits this control signal to this column decoder and this line decoder, carries out reading or writing data to control this mnemon.
10. mnemon as claimed in claim 1, it is characterized in that, wherein the substrate of this first transistor, this transistor seconds, this third transistor and the 4th transistor couples this power end.
CN201010226529.7A 2010-07-08 2010-07-08 Save the mnemon of circuit area Active CN101894583B (en)

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