CN102033823B - Method and device for storing data - Google Patents
Method and device for storing data Download PDFInfo
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- CN102033823B CN102033823B CN200910173969.8A CN200910173969A CN102033823B CN 102033823 B CN102033823 B CN 102033823B CN 200910173969 A CN200910173969 A CN 200910173969A CN 102033823 B CN102033823 B CN 102033823B
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Abstract
The invention discloses a method for storing data, which is used for ensuring that data in a memory is not lost after a system is restarted. The method is realized by a system single plate, a conversion module, the memory and a permanent memory, wherein the system single plate comprises a central processing unit (CPU). The method comprises the following steps that: the CPU operates an application software program; after an abnormal condition occurs, the CPU writes the data in the memory into the conversion module, so that the data is written into the permanent memory by the conversion module; the CPU executes a restarting instruction, and triggers the system single plate to restart; after the system single plate is restarted, the CPU sends a read instruction to the conversion module; the conversion module reads the data in the memory out from the permanent memory according to the read instruction; and the CPU reads the data out from the conversion module and writes the data into the memory. The invention also discloses a device for realizing the method.
Description
Technical field
The present invention relates to computer realm, particularly relate to method and the device of save data.
Background technology
Along with the development of computer technology, all trades and professions are all utilizing computing machine to improve office efficiency.Various application software also emerge in an endless stream.Yet can not guarantee all normal operations very of all software, time and there is big and small problem.
Wherein, as long as some problem may be restarted software, some problem may cause system to be restarted.When restarting system because of fault, the data in internal memory cannot retain, and that is to say that the relevant information of fault in-situ cannot be recorded and analyze, and follow the tracks of, locate and get rid of and bring very large difficulty to follow-up fault.And, may cause the loss of significant data.
Prior art is by adopting internal memory self-refresh mode to solve this problem.This needs chipset on hardware, to support internal memory self-refresh, when needs system is restarted, triggers memory bar and enters self-refresh mode.After restarting, the memory headroom in Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) not initialization reservation paragraph.Like this, important data can be stored in reservation paragraph, can not restart obliterated data because of system, thus and can be to this part data analysis location fault.This Technology Need chipset, BIOS and the support of memory bar on hardware.
Yet, only have at present a small amount of chipset, BIOS and memory bar can support this technology, for the equipment of not supporting this technology, because of fault, restart after system, still cannot preserve the data in internal memory.
Summary of the invention
The embodiment of the present invention provides a kind of method and device of save data, and for realizing after system is restarted, the data in internal memory are not lost.
A method for save data, the method is realized by system single board, modular converter, internal memory and permanent memory, and wherein system single board comprises CPU; Said method comprising the steps of:
CPU moves Application Software Program;
After occurring extremely, CPU writes modular converter by the data in internal memory, by modular converter, data is write to permanent memory;
CPU carries out reset command, and triggering system veneer is restarted;
After restarting, CPU sends read command to modular converter;
Modular converter is read the former data that belong to internal memory according to reading instruction from storer; CPU reads these data write memory from modular converter;
Wherein, described CPU writes modular converter by the data in internal memory, by modular converter, data are write to permanent memory, be specially: described modular converter is according to the LPC clock signal from described system single board, generate and to described permanent memory tranmitting data register signal, make described permanent memory and described modular converter keep sequential consistent, described CPU writes described modular converter according to the sequential of described system single board and the quantity of bus by the data in described internal memory, by described modular converter, according to the address wire of described permanent memory and the width of data line, data are write to described permanent memory.
A computer equipment, comprising:
Storer, for save data;
Memory modules, for save data;
CPU in system single board, for moving Application Software Program, after occurring extremely, writes modular converter by the data in internal memory; Carry out reset command, triggering system veneer is restarted, and after restarting, to modular converter, sends read command, and from modular converter sense data write memory;
Modular converter, for writing permanent memory by data; And from storer, read the former data that belong to internal memory according to reading instruction;
Wherein, described CPU writes modular converter by the data in internal memory, by modular converter, data are write to permanent memory, be specially: described modular converter is according to the LPC clock signal from described system single board, generate and to described permanent memory tranmitting data register signal, make described permanent memory and described modular converter keep sequential consistent, described CPU writes described modular converter according to the sequential of described system single board and the quantity of bus by the data in described internal memory, by described modular converter, according to the address wire of described permanent memory and the width of data line, data are write to described permanent memory.
In the embodiment of the present invention, application software occurs abnormal, before system single board is restarted, the significant data in internal memory is write to plug-in permanent memory, after system single board is restarted, then the data in storer is read to internal memory.Avoided because restarting the loss of data in the internal memory causing.
Accompanying drawing explanation
Fig. 1 is the structural drawing of embodiment of the present invention Computer equipment;
Fig. 2 is the structural drawing of modular converter in the embodiment of the present invention;
Fig. 3 A is the main method process flow diagram of save data in the embodiment of the present invention;
Fig. 3 B is the detailed method process flow diagram of save data in the embodiment of the present invention;
Fig. 4 be in the embodiment of the present invention from internal memory the method flow diagram of sense data;
Fig. 5 is that the memory module of LPC in the embodiment of the present invention is write sequential chart;
Fig. 6 is that the memory module of fireware in the embodiment of the present invention is write sequential chart;
Fig. 7 in the embodiment of the present invention writes back data the method flow diagram of internal memory;
Fig. 8 is that the memory module of LPC in the embodiment of the present invention is read sequential chart;
Fig. 9 is that the memory module of fireware in the embodiment of the present invention is read sequential chart.
Embodiment
In the embodiment of the present invention, application software occurs abnormal, before system single board is restarted, the significant data in internal memory is write to plug-in permanent memory, after system single board is restarted, then the data in storer is read to internal memory.Avoided because restarting the loss of data in the internal memory causing.
Referring to Fig. 1, the computer equipment in the present embodiment comprises application software module 101, detection module 102, writing module 103, modular converter 104, system single board 105, read through model 106, storer 107 and memory modules 108.Wherein, system single board 105 is connected with modular converter 104, and modular converter 104 is connected with storer 107.System single board 105 comprises CPU and chipset.Application software module 101, detection module 102, writing module 103 and read through model 106 are to operate in CPU and the module being realized by software.Modular converter 104 can be specially field programmable gate array (Field-Programmable Gate Array, FPGA) or CPLD (Complex Programmable Logic Device, CPLD) etc.Storer 107 can be synchronous static RAM (Synchronous static random access memory, SSRAM) etc.Memory modules 108 is realized by memory bar.
System single board 105 is restarted after occurring extremely in Application Software Program.System single board 105 is restarted rear generation reset signal, triggers modular converter and resets.
Read through model 106 is for automatically starting after restarting at system single board 105, and sends read commands to modular converter 104; And from modular converter 104 sense data write memory 108.Wherein, read through model 106 sends read command by the frame signal between system single board 105 and modular converter 104 to modular converter 104.
System single board 105 transmits address and data, normally 4 of this address date multiplex buss by address date multiplex bus and other module.And storer 107 transmits address by address wire and other module, by data line and other module, transmit data, address and data are transmitted by different circuits.And generally, the address wire of storer 107 and the figure place of data line are higher than 4.This needs modular converter 104 to carry out sequential conversion between system single board 105 and storer 107.Below structure of modular converter 104 etc. is introduced.
Referring to Fig. 2, in the present embodiment, modular converter 104 comprises bus interface 201, address location 202, write data unit 203, reading data unit 204, clock unit 205, control module 206 and reseting interface 207.
Write data unit 203 is for receiving from the data of bus interface 201 and preserving, when the data of receiving meet the width of data line, by data line by writing data into memory 107.
Reading data unit 204 for by data line from storer 107 sense datas and preserve, according to the width of address date multiplex bus, send the data to bus interface 201.
The clock signal that clock unit 205 produces for receiving system veneer 105, and according to this clock signal, control the sequential of address location 202, write data unit 203 and reading data unit 204, and to storer 107 tranmitting data register signals, make storer 107 keep sequential consistent.
The frame signal that control module 206 produces for receiving system veneer 105, frame signal comprises write order and read command etc.Control module 206 generates corresponding control signal and sends to storer 107 according to frame signal.
The reset signal that reseting interface 207 produces for receiving system veneer 105, and be subject to the triggering of this reset signal, reset modular converter 104.
Inner structure and the function of more than having introduced computer equipment, describe in detail to the process of save data below.
Referring to Fig. 3 A, in the present embodiment, the main method flow process of save data is as follows:
Step 31:CPU moves Application Software Program.
Step 32: after Application Software Program occurs extremely, CPU writes modular converter by the data in internal memory, by modular converter, data is write to permanent memory.
Step 33:CPU carries out reset command extremely because of Application Software Program appearance, and triggering system veneer is restarted.
Step 34: after restarting, CPU sends read command to modular converter.
Step 35: modular converter is read the former data that belong to internal memory according to reading instruction from storer.
Step 36:CPU reads these data write memory from modular converter.
Because CPU carrys out practical function by working procedure, these programs can be divided into a plurality of modules, describe the process of save data below by these modules.
Referring to Fig. 3 B, in the present embodiment, the detailed method flow process of save data is as follows:
Step 301: Application Software Program generates and sends abnormal signal after occurring extremely.
Step 302: detection module, after abnormal signal being detected, triggers writing module.
Step 303: writing module writes modular converter by the data in internal memory, by modular converter, data is write to permanent memory.
Step 304: the system single board that extremely causes of Application Software Program is restarted, and after restarting, automatically start read through model.
Step 305: read through model sends read command to modular converter.
Step 306: modular converter is read the former data that belong to internal memory according to reading instruction from storer; Read through model is read these data write memory from modular converter.
Referring to Fig. 4, in the present embodiment, from internal memory, the method flow of sense data is as follows:
Step 401: Application Software Program occurs abnormal, application software module 101 generates abnormal signal and sends.
Step 402: detection module 102 detects abnormal signal and triggers writing module 103.
Step 403: writing module 103 sends write order by system single board 105 to modular converter 104.
Step 404: modular converter 104 sends write order to storer 107.
Step 405: writing module 103 passes through according to the sequential of system single board the data that system single board 105 sends in addresses and memory modules 108 to modular converter 104.For example the width of address date multiplex bus is 4.The address wire width of storer 107 is 20, and data line width is 8.
Step 406: modular converter 104 is according to the address wire of storer 107 and width buffer memory multiframe address and the data of data line, until meet address wire width and the data line width of storer 107.For example, modular converter 104 buffer memory 5 frame address and 2 frame data.
Step 407: modular converter 104 sends address and data to storer 107.
Step 408: application software module 101 triggering system veneers 105 are restarted.
In step 405, system single board 105 has multiple-working mode, as storage (memory) pattern of low pin number (Low Pin Count, LPC) and the memory module of hardware (fireware) etc.Different mode of operations has different sequential.Referring to the memory module of the LPC shown in Fig. 5 and Fig. 6, write the memory module of sequential chart and fireware and write sequential chart, in the memory module of LPC, after start signal (Start), first transmit 32 bit address (A[31]～A[0]), transmit again 8 bit data (D[7]～D[0]), then through 2 clock period (TAR) and a synchronizing cycle (Sync), then pass next address and data, repeat this process until all significant data end of transmissions.In the memory module of firmware, Preamble has partly comprised start bit and address bit, then first passes low data (Data Lo) and passes high position data (Data Hi) again, passes next address and data through 1 clock period again.LCK represents lpc bus clock; LFRAME represents the frame signal of lpc bus; LAD represents the data address multiplex bus of lpc bus; Start represents beginning flag; CYCTYPE indication cycle type; TAR represents to turn to (Turn-Around), and the control of lpc bus can be delivered during this period; Sync represents synchronously, can add latent period to reach the synchronous of peripheral hardware and main frame in this period.Wherein, significant data can be all data in memory modules 108, can be also the data in default storage space in memory modules 108.In step 406, modular converter 104 buffer memory multiframe address and data.For example the width of address date multiplex bus is 4, and the address wire width of storer 107 is 20, and the length of an address is 32.Every buffer memory 5 frame address of modular converter 104 send once to storer 107, but an address only accounts for 8 frames, also remain 3 frames after buffer memory 5 frames, and less than 5 frames now just can send addresses to storer 107 after buffer memory 3 frames.For example, the length of data is 8, and the width of data line is also 8, and every buffer memory 2 frame data of modular converter 104 send once to storer 107.Because writing module 103 is first to send 32 bit address to modular converter 104, then send 8 bit data, so modular converter 104 is also first to send address to storer 107, then send data.
Can predetermine one section of storage space in storer 107 for the data of stored memory, the address that writing module 103 sends is exactly the address of this section of storage space.The address that read through model 106 sends to modular converter 104 is also the address of this section of storage space.Then modular converter 104 sense data return to read through model 106 from this section of storage space of storer 107, by read through model 106 by data write memory module 108.To data being write back after restarting to the process of internal memory, be introduced below.
Referring to Fig. 7, the method flow that in the present embodiment, data is write back to internal memory is as follows:
Step 701: system single board 105 is restarted, and automatically start read through model 106.
Step 702: system single board 105 produces reset signal, triggers modular converter 104 and resets.The process that produces reset signal can be carried out with the process that starts read through model 106 simultaneously.
Step 703: read through model 106 sends read command by the frame signal between system single board 105 and modular converter 104 to modular converter 104.
Step 704: modular converter 104 by and storer 107 between control signal will read instruction and send to storer 107.
Step 705: read through model 106 sends to modular converter 104 by system single board 105 by address.
Step 706: modular converter 104 is read the former data that belong to internal memory according to the address of receiving from storer 107.
Step 707: modular converter 104 sends to read through model 106 by data by system single board 105 according to the width of address date multiplex bus.
Step 708: read through model 106 by system single board 105 by the data write memory of receiving.
In step 705-707, referring to the memory module of the LPC shown in Fig. 8 and Fig. 9, read the memory module of sequential chart and fireware and read sequential chart, in the memory module of LPC, after start signal (Start), read through model 106 first transmits 32 bit address (A[31]～A[0]), through 2 clock period (TAR) and a synchronizing cycle (Sync), modular converter 104 transmission 8 bit data (D[7]～D[0]) to read through model 106, pass again next address and data through 1 clock period, repeat this process until all significant data end of transmissions.In the memory module of firmware, Preamble has partly comprised start bit and address bit, read through model 106 first transmits 32 bit address (A[31]～A[0]) to modular converter 104, through 1 clock period (TAR) and a synchronizing cycle (Sync), modular converter 104 transmission 8 bit data (D[7]～D[0]) to read through model 106, pass again next address and data through 1 clock period, repeat this process until all significant data end of transmissions.Modular converter 104 receives from the process of the address of read through model 106 and writes together the description in sequential.Process about read data, for example, the width of address date multiplex bus is 4, the width of data line is 8, the length of data is also 8, and modular converter 104 is read after 8 bit data, according to the width of address date multiplex bus from storer 107, these data are divided into two frames and send to read through model 106, send after first sending low 4 high 4.
For realizing the software of the embodiment of the present invention, can be stored in the storage mediums such as floppy disk, hard disk, CD and flash memory.
In the embodiment of the present invention, application software occurs abnormal, before system single board is restarted, the significant data in internal memory is write to plug-in permanent memory, after system single board is restarted, then the data in storer is read to internal memory.Avoided because restarting the loss of data in the internal memory causing, and be convenient to fault occurrence cause to position.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (6)
1. a method for save data, is characterized in that, the method is realized by system single board, modular converter, internal memory and permanent memory, and wherein system single board comprises CPU; Said method comprising the steps of:
CPU moves Application Software Program;
After Application Software Program occurs extremely, CPU writes modular converter by the data in internal memory, by modular converter, data is write to permanent memory;
CPU carries out reset command extremely because of Application Software Program appearance, and triggering system veneer is restarted;
After restarting, CPU sends read command to modular converter;
Modular converter is read the former data that belong to internal memory from permanent memory according to read command; CPU reads these data write memory from modular converter;
Wherein, described CPU writes modular converter by the data in internal memory, by modular converter, data are write to permanent memory, be specially: modular converter is according to the clock signal from system single board, generate and to permanent memory tranmitting data register signal, make permanent memory and modular converter keep sequential consistent, CPU writes modular converter according to the sequential of system single board and the quantity of bus by the data in internal memory, by modular converter, according to the address wire of permanent memory and the width of data line, data is write to permanent memory.
2. the method for claim 1, is characterized in that, before CPU sends read command to modular converter, system single board is restarted rear generation reset signal, triggers modular converter and resets.
3. the method for claim 1, is characterized in that, the step that CPU sends read command to modular converter comprises: CPU sends read command by the frame signal between system single board and modular converter to modular converter;
Modular converter is read the former data that belong to internal memory from permanent memory according to read command before, by and permanent memory between control signal read command is sent to permanent memory.
4. a computer equipment, is characterized in that, comprising:
Permanent memory, for save data;
Internal memory, for save data;
CPU in system single board, for moving Application Software Program, after often occurring confering, writes modular converter by the data in internal memory; Carry out reset command, triggering system veneer is restarted, and after restarting, to modular converter, sends read command, and from modular converter sense data write memory;
Modular converter, for writing permanent memory by data; And according to read command, from permanent memory, read the former data that belong to internal memory;
Wherein, described CPU writes modular converter by the data in internal memory, by modular converter, data are write to permanent memory, be specially: modular converter is according to the clock signal from system single board, generate and to permanent memory tranmitting data register signal, make permanent memory and modular converter keep sequential consistent, CPU writes modular converter according to the sequential of system single board and the quantity of bus by the data in internal memory, by modular converter, according to the address wire of permanent memory and the width of data line, data is write to permanent memory.
5. computer equipment as claimed in claim 4, is characterized in that, system single board is restarted rear generation reset signal, triggers modular converter and resets.
6. computer equipment as claimed in claim 4, is characterized in that, CPU sends read command by the frame signal between system single board and modular converter to modular converter;
Modular converter by and permanent memory between control signal read command is sent to permanent memory.
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| CN102184145B (en) * | 2011-05-13 | 2013-04-17 | 杭州华三通信技术有限公司 | Zero restart-data loss method and device |
| CN102193847B (en) * | 2011-06-24 | 2013-04-10 | 杭州华三通信技术有限公司 | No-lose method of restart data and reserved memory management module |
| CN108549591B (en) * | 2018-03-02 | 2021-06-15 | 烽火通信科技股份有限公司 | Black box device of embedded system and implementation method thereof |
| CN109471758A (en) * | 2018-11-22 | 2019-03-15 | 北京同有飞骥科技股份有限公司 | Storing data power-off protection method and system |
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| JPH07175728A (en) * | 1993-12-20 | 1995-07-14 | Hokkaido Nippon Denki Software Kk | Disk cache data maintenance system |
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| CN1530795A (en) * | 2003-03-12 | 2004-09-22 | 联想(北京)有限公司 | Method for saving and restoring computer system operation state |
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