CN102402491A - Electronic device, controller for accessing multiple chips through at least one bus and method for accessing multiple chips through at least one bus - Google Patents
Electronic device, controller for accessing multiple chips through at least one bus and method for accessing multiple chips through at least one bus Download PDFInfo
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- CN102402491A CN102402491A CN2010102890796A CN201010289079A CN102402491A CN 102402491 A CN102402491 A CN 102402491A CN 2010102890796 A CN2010102890796 A CN 2010102890796A CN 201010289079 A CN201010289079 A CN 201010289079A CN 102402491 A CN102402491 A CN 102402491A
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Abstract
The invention discloses an electronic device which comprises a plurality of chips, at least one bus and a controller, wherein the plurality of chips comprise a first chip and a second chip; the bus comprises a plurality of data lines; and the controller is coupled to the chips through the bus and used for storing the plurality of chips. The controller determines a data transmission configuration used when an external datum is transmitted through the plurality of data lines according to information on which chip of the plurality of chips is the external datum to be written to, wherein the data transmission configuration is an arrangement sequence of a plurality of bits of the external datum on the plurality of data lines, and a first data transmission configuration corresponding to the first chip is different from a second data transmission configuration corresponding to the second chip.
Description
[technical field]
The invention relates to a kind of electric memory mechanism, refer to a kind of electronic installation with several data transmission configuration especially, come the controller of a plurality of chips of access and via the method for at least one bus with a plurality of chips of access via at least one bus.
[background technology]
In traditional flash memory; The data that flash controller transmits command signal, address signal and required storage simultaneously through bus are to flash chip; And flash chip carried out access; Yet, because bus requirements transmits the data of command signal, address signal and required storage simultaneously, so many data lines in the bus and the random clearing house signal that need transmit.In detail, please refer to Fig. 1, Fig. 1 is connected to the synoptic diagram of a plurality of flash chips 104,106 through a bus 103 for existing flash controller 102.As shown in Figure 1, the pin D of flash controller 102
0～D
7Must be connected to the pin D of flash chip 104,106 respectively
0～D
7, flash chip 104,106 could correctly receive the signal from flash controller 102, and can not the data line in the bus 103 arbitrarily be exchanged connection (for example with the pin D of flash controller 102
0Be connected to the pin D of flash chip 104
4, and with the pin D of flash controller 102
4Be connected to the pin D of flash chip 104
0Or the like).Thus, because the pin D of flash controller 102
0～D
7Pin D with flash chip 104,106
0～D
7Must connect one to one really, can cause the inconvenience on circuit-board laying-out, that is possibly need to use, cause design and make the upward increase of cost than the circuit board of multilayer or the coiling that connects hole (via hole) and complicacy that need be more on circuit board.
[summary of the invention]
Therefore; One of the object of the invention is to provide a kind of electronic installation with several data transmission configuration, comes the controller of a plurality of chips of access and via the method for at least one bus with a plurality of chips of access via at least one bus; It can reduce the complexity on the circuit-board laying-out effectively; And reduce circuit board at design and the cost of making, to solve the above problems.
According to one embodiment of the invention; One electronic installation includes a plurality of chips, at least one bus and a controller; Wherein these a plurality of chips include one first chip and one second chip; This bus packet contains many data lines, and this controller is coupled to this a plurality of chips via this bus, and is used for these a plurality of chips of access.The data transmission configuration when information that this controller desires to write to which chip in these a plurality of chips according to an external data decides this external data to transmit through these many data lines; Wherein this data transmission is configured to a plurality of position the putting in order on these many data lines of this external data, and one first data transmission configuration that should first chip is differed from one second data transmission configuration that should second chip.
According to another embodiment of the present invention, it discloses and a kind ofly to come the controller of a plurality of chips of access via at least one bus, and wherein this bus packet contains many data lines, and this controller includes a storage element and a microprocessor.This storage element is used for storing the several data transmission configuration that corresponds to a plurality of chips, and each data transmission was configured to a plurality of positions putting in order on these many data lines of an external data during wherein these a plurality of data transmission disposed; This microprocessor is used for these a plurality of chips of access, and the information of desiring to write to which chip in these a plurality of chips according to this external data is from selecting one of which in this several data transmission configuration, and according to this with this external data be sent to the chip desiring to write.
According to another embodiment of the present invention; Its exposure is a kind of via the method for at least one bus with a plurality of chips of access; Wherein these a plurality of chips include one first chip and one second chip, and this bus packet contains many data lines, and this method includes: receive an external data; And the data transmission configuration when deciding this external data to transmit through these many data lines according to the information that this external data desires to write to which chip in these a plurality of chips; Wherein this data transmission is configured to a plurality of position the putting in order on these many data lines of this external data, and one first data transmission configuration that should first chip is differed from one second data transmission configuration that should second chip.
[description of drawings]
Fig. 1 is connected to the synoptic diagram of a plurality of flash chips through a bus for existing flash controller.
Fig. 2 is the synoptic diagram according to the flash memory devices of one embodiment of the invention.
Fig. 3 is the synoptic diagram of flash controller shown in Figure 2, a plurality of data bus and flash memory chip set.
Fig. 4 is flash controller, bus 228_1 and flash chip 230_1 shown in Figure 3, the synoptic diagram of 230_2.
Fig. 5 is a kind of via the process flow diagram of at least one bus with the method for a plurality of chips of access according to one embodiment of the invention.
[primary clustering symbol description]
| 102、226 | Flash |
| 103 | |
| 104、106、230_1～230_8 | Flash |
| 200 | Flash |
| 210 | |
| 221 | The physical |
| 222 | |
| 223 | |
| 224 | |
| 225 | Processor |
| 228_1～228_4 | |
| 230 | Flash |
| 310 | |
| 320 | Storage element |
[0014]
| 330 | The data bus input-output unit |
| 500,502 | Step |
[embodiment]
Please refer to Fig. 2, Fig. 2 is the synoptic diagram according to the flash memory devices 200 of one embodiment of the invention.As shown in Figure 2; Flash memory devices 200 includes an interface circuit 210, a physical layer (physicallayer) treating apparatus 221, an interface controller 222, a local bus 223, an internal memory 224, a processor 225 and a flash controller 226, a plurality of data bus 228 and a memory chip group (being example with flash memory chip set 230 in the present embodiment); Wherein interface circuit 210 can be serial advanced technology attachment device (Serial Advanced Technology Attachment; SATA) interface, USB (Universal Serial Bus; USB) interface or periphery component interconnection (Peripheral Component Interconnect Express; PCIE) interface one of them, also can be to combine USB and SATA interface, or the combination in any of USB, SATA and PCIE interface; In addition, physical layer treating apparatus 221 can adopt SATA, USB or PCIE physical layer treating apparatus according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE physical layer treating apparatus; And interface controller 222 can also adopt SATA, USB or PCIE interface controller according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE interface controller; Flash memory devices 200 can be a portable memory device, and can link with the interface socket 250 in the main frame 240.
Please refer to Fig. 3, Fig. 3 is the synoptic diagram of flash controller 226, a plurality of data bus 228 and flash memory chip set 230 according to one embodiment of the invention.As shown in Figure 3, flash controller 226 includes a microprocessor 310, a storage element 320 and a data bus input-output unit 330, and flash controller 226 is connected to flash chip 230_1～230_8 respectively through data bus 228_1～228_4.In addition, each data bus 228_1～228_4 all includes many data lines (in present embodiment, each data bus 228_1～228_4 includes 8 data line L
1～L
8), and storage element 320 is used for storing the several data transmission configuration that corresponds to flash chip 230_1～230_8, wherein each data transmission is configured to a plurality of positions putting in order on many data lines of an external data in these a plurality of data transmission configurations.For instance, flash chip 230_1 corresponds to one first data transmission configuration, wherein from the data D of main frame 240
0～D
7Respectively through 8 data line L
1～L
8Be sent to flash chip 230_1; In addition, flash chip 230_2 corresponds to one second data transmission configuration, wherein from the data D of main frame 240
0～D
7Respectively through 8 data line L
8, L
7, L
6, L
5, L
4, L
3, L
2, L
1Be sent to flash chip 230_2 ... Or the like.
Specify the flash controller 226 shown in Fig. 3, bus 228_1 and flash chip 230_1,230_2 and relevant operating process for example; Please refer to Fig. 4; Microprocessor 310 at first can receive the external data from main frame 240, and decides this external data through many data line L according to the information that this external data desires to write to which chip among a plurality of flash chip 230_1～230_8
1～L
8Data transmission configuration during transmission.Suppose that this external data desires to write flash chip 230_1 shown in Figure 4; Then microprocessor 310 is selected in storage element 320 corresponding to the configuration of one first data transmission of flash chip 230_1, and according to this control data bus input-output unit 330 with the position D in this external data
0～D
7In regular turn through data line L
1～L
8Be sent to flash chip 230_1; On the other hand; Suppose that this external data desires to write flash chip 230_2; Then microprocessor 310 is selected in storage element 320 corresponding to the configuration of one second data transmission of flash chip 230_2, and according to this control data bus input-output unit 330 with the position D in this external data
0～D
7In regular turn through data line L
8～L
1Be sent to flash chip 230_1.As stated, (for example flash chip 230_1 is from data line L because flash chip 230_1 need not receive identical data with 230_2 via identical data line
1Receive the position D of this external data
0, and flash chip 230_2 can be from data line L
8Receive the position D of this external data
0), and data bus input-output unit 330 can dynamically switch the position D of this external data
0～D
7Which by bar data line be sent in the flash chip respectively; Thus; Circuit layout between flash chip 230_1 and 230_2 and flash controller 226 can be more flexible; And the deviser also can reduce the complexity on the circuit-board laying-out efficiently, and reduces circuit board at design and the cost of making.
Be noted that, among the embodiment of Fig. 2 to Fig. 4, be used as explanation with flash memory devices, yet the present invention be not as limit again.In other embodiments of the invention; Flash memory devices 200 can be other any type of storage device; And flash chip 230_1～230_8 can also be other storage chip; Particularly to the data bus in the storage device be not simple data signal situation (for example data bus can transmit command signal, address signal and required storage simultaneously data to storage chip), the present invention can reduce the complexity on the circuit-board laying-out really.And the variation in above-mentioned these designs all should be under the jurisdiction of category of the present invention.
Please refer to Fig. 5, Fig. 5 is a kind of via the process flow diagram of at least one bus with the method for a plurality of chips of access according to one embodiment of the invention, and wherein these a plurality of chips include one first chip and one second chip, and this bus packet contains many data lines.With reference to figure 5, flow process is narrated as follows:
Step 500: receive an external data.
Step 502: the data transmission configuration the when information of desiring to write to which chip in these a plurality of chips according to this external data decides this external data to transmit through these many data lines; Wherein this data transmission is configured to a plurality of position the putting in order on these many data lines of this external data, and one first data transmission configuration that should first chip is differed from one second data transmission configuration that should second chip.
Concise and to the point conclusion the present invention; Come the controller of a plurality of chips of access in electronic installation of the present invention, via at least one bus and via the method for at least one bus with a plurality of chips of access in, the data transmission configuration the when information of desiring to write to which chip in a plurality of chips according to an external data decides many data lines of this external data through this bus to transmit.Thus, just can increase the elasticity of layout on the circuit board, to reduce circuit board at design and the cost of making.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. electronic installation includes:
A plurality of chips include one first chip and one second chip;
At least one bus, wherein this bus packet contains many data lines; And
One controller; Be coupled to this a plurality of chips via this bus; Be used for these a plurality of chips of access; And the data transmission configuration when deciding this external data to transmit through these many data lines according to the information that an external data desires to write to which chip in these a plurality of chips; Wherein this data transmission is configured to a plurality of position the putting in order on these many data lines of this external data, and one first data transmission configuration that should first chip is differed from one second data transmission configuration that should second chip.
2. electronic installation according to claim 1 is characterized in that, each chip is a memory chip in these a plurality of chips, and this controller is a Memory Controller Hub.
3. electronic installation according to claim 2 is characterized in that, this memory chip is a flash memory (Flash Memory) chip.
4. storage device according to claim 1 is characterized in that, this controller decides this data transmission configuration through the mode of tabling look-up.
5. one kind is come the controller of a plurality of chips of access via at least one bus, and this bus packet contains many data lines, and this controller includes:
One storage element is used for storing the several data transmission configuration that corresponds to a plurality of chips, and each data transmission was configured to a plurality of positions putting in order on these many data lines of an external data during wherein these a plurality of data transmission disposed; And
One microprocessor is used for these a plurality of chips of access, and the information of desiring to write to which chip in these a plurality of chips according to this external data is from selecting one of which in this several data transmission configuration, and according to this with this external data be sent to the chip desiring to write.
6. controller according to claim 5 is characterized in that, each chip is a memory chip in these a plurality of chips, and this controller is a Memory Controller Hub.
7. controller according to claim 6 is characterized in that, this memory chip is a flash memory (Flash Memory) chip.
8. controller according to claim 5 is characterized in that, this several data transmission configuration has at least two kinds of different data transmission configurations, and it corresponds to the different chips in these a plurality of chips respectively.
9. one kind via the method for at least one bus with a plurality of chips of access, and wherein these a plurality of chips include one first chip and one second chip, and this bus packet contains many data lines, and this method includes:
Receive an external data; And
The data transmission configuration when information of desiring to write to which chip in these a plurality of chips according to this external data decides this external data to transmit through these many data lines; Wherein this data transmission is configured to a plurality of position the putting in order on these many data lines of this external data, and one first data transmission configuration that should first chip is differed from one second data transmission configuration that should second chip.
10. method according to claim 9 is characterized in that, each chip is a memory chip in these a plurality of chips, and this controller is a Memory Controller Hub.
11. method according to claim 10 is characterized in that, this memory chip is a flash memory (Flash Memory) chip.
12. method according to claim 9 is characterized in that, determines the step of this data transmission configuration when this external data transmits through these many data lines to include:
Decide this data transmission configuration through the mode of tabling look-up.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102890796A CN102402491A (en) | 2010-09-13 | 2010-09-13 | Electronic device, controller for accessing multiple chips through at least one bus and method for accessing multiple chips through at least one bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102890796A CN102402491A (en) | 2010-09-13 | 2010-09-13 | Electronic device, controller for accessing multiple chips through at least one bus and method for accessing multiple chips through at least one bus |
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| CN2010102890796A Pending CN102402491A (en) | 2010-09-13 | 2010-09-13 | Electronic device, controller for accessing multiple chips through at least one bus and method for accessing multiple chips through at least one bus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615555A (en) * | 2015-01-26 | 2015-05-13 | 北京海尔集成电路设计有限公司 | Communicator for master chip and subordinate chip sharing high-capacity off-chip storage unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060184721A1 (en) * | 2005-02-16 | 2006-08-17 | Chen Ben W | Configurable flash memory controller and method of use |
| CN101359317A (en) * | 2007-08-01 | 2009-02-04 | 英业达股份有限公司 | Parallel programming system and method |
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2010
- 2010-09-13 CN CN2010102890796A patent/CN102402491A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060184721A1 (en) * | 2005-02-16 | 2006-08-17 | Chen Ben W | Configurable flash memory controller and method of use |
| US20100262768A1 (en) * | 2005-02-16 | 2010-10-14 | Kingston Technology Corporation | Configurable flash memory controller and method of use |
| CN101359317A (en) * | 2007-08-01 | 2009-02-04 | 英业达股份有限公司 | Parallel programming system and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104615555A (en) * | 2015-01-26 | 2015-05-13 | 北京海尔集成电路设计有限公司 | Communicator for master chip and subordinate chip sharing high-capacity off-chip storage unit |
| CN104615555B (en) * | 2015-01-26 | 2018-02-02 | 北京海尔集成电路设计有限公司 | A kind of principal and subordinate's chip shares the communicator of the outer memory cell of Large Copacity piece |
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Application publication date: 20120404 |