CN103123806A - Control circuit of DRAM (dynamic random access memory) column selection signal and access memory comprising same - Google Patents
Control circuit of DRAM (dynamic random access memory) column selection signal and access memory comprising same Download PDFInfo
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- CN103123806A CN103123806A CN2011103699796A CN201110369979A CN103123806A CN 103123806 A CN103123806 A CN 103123806A CN 2011103699796 A CN2011103699796 A CN 2011103699796A CN 201110369979 A CN201110369979 A CN 201110369979A CN 103123806 A CN103123806 A CN 103123806A
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Abstract
The invention belongs to the technical field of a DRAM (dynamic random access memory) and relates to a control circuit of a DARM column selection signal. The control circuit comprises a column selection signal generation circuit, a redundancy unit corresponding to a memory unit of the DARM and a redundant word line drive module, wherein the column selection signal generation circuit generates a column selection signal when the amplification read-out voltage of the redundancy unit is matched with a preset voltage threshold. The DARM comprises a memory array and a read path of the memory unit in the memory array, and is characterized in that the memory array also comprises the redundancy unit. The DARM also comprises the control circuit of the column selection signal. The DARM can increase the speed of read operation while guaranteeing the reliability of reading.
Description
Technical field
The invention belongs to DRAM (Dynamic Random Access Memory, dynamic RAM) technical field, relate to the control circuit of the array selecting signal of DRAM, relate in particular to a kind of control circuit that comprises the array selecting signal of redundancy unit.
Background technology
DRAM has been widely used in the electronic product such as computing machine, and its technical development cycle is longer, and is relatively ripe.But because DRAM is based on the storer that electric charge is stored information, its read operation is relatively slow.Along with the requirement to the speed of DRAM is more and more higher, current Main Means be by to DRAM constantly scaled (scaling down) improve read rate.
Normally, DRAM comprises storage array and peripheral circuit (being used for the control of operations such as realizing reading and writing and refresh), storage array is to be rearranged by the form of a plurality of storage unit by row and column equally, and each storage unit is arranged at the bit line of corresponding coupling and the infall between the word line.Particularly, storage unit generally includes an access transistor T (having gate action) and is used for the capacitor C of stored charge.Peripheral circuit is according to external command, by bit line and word line biasing corresponding electric signal to choosing, to realize the wherein operation of the storage unit of a certain address.
Wherein, the peripheral circuit of DRAM comprises code translator (for example line decoder and column decoder), bit-line drive module, bit-line drive module, Logic control module and sensor amplifier (sense amplifier for example, SA), sensor amplifier is coupled on storage array, its be used for to carry out from/to selecteed storage unit read/write operation.The output of sensor amplifier also is coupled in the I/O impact damper of DRAM simultaneously.In the read operation process, whether sensor amplifier starts working, and enables control signal by it and controls; When sensor amplifier is coupled to its output in the I/O impact damper of DRAM, and the array selecting signal YL by correspondence controls.
Figure 1 shows that the logical control mode schematic diagram of DRAM column selection of prior art.In this example, sensor amplifier is conventional SA (Sense Amplifier, sense amplifier), array selecting signal YL provides separately, in order to read correct information, YL sensor amplifier enable be activated after control signal SA_en activates, the output of sensor amplifier is coupled in the I/O impact damper MA of DRAM.The logical control mode of DRAM column selection shown in Figure 1 mainly contains following shortcoming: if YL activates too early, may make the voltage on bit line be dragged down rapidly by the large electric capacity on the IO line, and low to can't again being amplified by SA, cause read error.Therefore, in the prior art, usually adopt delay required under worst case, namely YL is more late is activated, but this brings extra read latency, has affected read rate.
In view of this, be necessary to propose a kind of novel control circuit producing array selecting signal for the logical mode of the column selection of DRAM, with guarantee DRAM read reliability in, improve its read operation speed.
Summary of the invention
The technical problem to be solved in the present invention is to improve the read operation speed of DRAM.
According to an aspect of of the present present invention, a kind of control circuit of array selecting signal of dynamic RAM is provided, described control circuit comprises the array selecting signal generative circuit, it is characterized in that, described control circuit also comprises: with the corresponding redundancy unit of the storage unit of described dynamic RAM and redundant word line driver module;
Wherein, when the amplification read-out voltage of described redundancy unit was complementary with the voltage threshold that presets, described array selecting signal generative circuit generated array selecting signal.
According to the preferred embodiment of the control circuit that the invention provides sensor amplifier, wherein, described array selecting signal generative circuit also comprises comparer, and described comparer is used for amplification read-out voltage and the described voltage threshold that presets of more described redundancy unit.
Preferably, during less than the minimum sensitive volume of described comparer, the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets are complementary when the difference of the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets.
According to the another preferred embodiment of the control circuit that the invention provides sensor amplifier, wherein, described control circuit also comprises be used to the voltage generation circuit that generates the described voltage threshold that presets.
Preferably, described voltage generation circuit is used for generating adjustable described voltage threshold that presets.
According to a preferred embodiment again of the control circuit that the invention provides sensor amplifier, wherein, described redundancy unit is storage " 0 " all the time or storage " 1 " all the time in the read operation process.
According to another aspect of the present invention, a kind of dynamic RAM is provided, it comprises the read path of the storage unit in storage array, storage array, it is characterized in that, also comprise redundancy unit in described storage array, described dynamic RAM also comprises the control circuit as the described array selecting signal of any one in claim 1 to 10.
Preferably, the preparation simultaneously in the storage array of described dynamic RAM of described storage unit and described redundancy unit forms.
Technique effect of the present invention is, by increase redundancy unit in the control circuit of the array selecting signal of storage unit, thereby, amplification read-out voltage by redundancy unit is matched with the voltage threshold that presets, and the delay of the peripheral circuit of the read path of control array selecting signal and storage unit is complementary.Therefore, on the one hand, the delay of control circuit is the delay of the read path of tracking memory cell effectively, and can follow the tracks of at any time the variation of the delay of the read path that technological fluctuation causes; On the other hand, in case the amplification read-out voltage of storage unit reaches degree (certain predetermined voltage that can correctly be read, can be VDD or certain voltage Vini a little less than VDD), can generate immediately the row control signal, be coupled to the output with sensor amplifier in the I/O impact damper MA of DRAM.Thereby, guarantee DRAM read reliability in, improve its read operation speed.
Description of drawings
From following detailed description by reference to the accompanying drawings, will make above and other objects of the present invention and advantage more fully clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the logical control mode schematic diagram of DRAM column selection in prior art;
Fig. 2 is the basic structure schematic diagram of control circuit of the array selecting signal of the DRAM that provides according to one embodiment of the invention;
Fig. 3 is the another example signal sequential schematic diagram of control circuit of the array selecting signal of DRAM shown in Figure 2.
Embodiment
The below introduces is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementation that one of ordinary skill in the art can propose mutually to replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or restriction to technical solution of the present invention.
Fig. 2 is the basic structure schematic diagram of control circuit of the array selecting signal of the DRAM that provides according to one embodiment of the invention.As shown in Figure 2, the control circuit of this array selecting signal, described control circuit comprises the array selecting signal generative circuit, and wherein, described control circuit also comprises and the corresponding redundancy unit 208 of the storage unit of described dynamic RAM and redundant word line driver module 209; Wherein, when the amplification read-out voltage of described redundancy unit was complementary with the voltage threshold Vref that presets, described array selecting signal generative circuit generated array selecting signal.For example, suppose to deposit 1 in redundancy unit 208.WL also activates redundancy unit 208 when drive activating storage unit 202.The potential rise of redundant bit line BLd, after the right voltage difference of bit line is amplified by SA207, output is added to comparator C OM's 205 "-" end, "+" end of comparator C OM is connected to reference voltage Vref, is provided by reference voltage maker Vref_gen 206.The output signal of comparer 205 is YL, activates column select switch, the memory contents of storage unit 202 is outputed on I/O line and I/O ' line through BL and SA203, then amplify through main amplifier MA 204, finally exports data.At this, the present embodiment is followed the tracks of the physical memory location read path with the redundancy unit read path, making the SA output voltage of physical memory location in a single day reach a predetermined value Vref (can be VDD, or certain voltage Vini that can correctly be read) again through the process of a comparer, namely activate YL after.Thereby can in time open YL, when guaranteeing to read reliability, improve read rate.Preferably, SA 203 and SA 207 structures are identical, and start simultaneously.Redundancy unit 208, redundant bit line are to BLd and BLd ', and be with physical memory location 202 and actual bit line BL and BL ', identical.
Preferably, this array selecting signal generative circuit also comprises comparator C OM205, and described comparer is used for amplification read-out voltage and the described voltage threshold Vref that presets of more described redundancy unit.Particularly, comparator C OM205 is the amplification read-out voltage and the voltage threshold Vref that presets of redundancy unit 208 relatively, when the amplification read-out voltage of described redundancy unit is complementary with the voltage threshold Vref that presets, as both equate or difference less than certain voltage difference scope, described array selecting signal generative circuit generates array selecting signal.Connect example, after the right voltage difference of the current potential bit line of redundancy unit 208 is amplified by SA207, output is added to comparator C OM's 205 "-" end, "+" end of comparator C OM is connected to reference voltage Vref, is provided by reference voltage maker Vref_gen 206.The output signal of comparer 205 is YL, activates column select switch, the memory contents of storage unit 202 is outputed on I/O line and I/O ' line through BL and SA203, then amplify through main amplifier MA 204, finally exports data.
More preferably, during less than the minimum sensitive volume of described comparer, the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets are complementary when the difference of the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets.For example, when Vref is VDD-deltV (deltV is the minimum sensitive volume of comparator C OM 205, namely makes phase inverter in comparer that the minimum voltage amplitude of upset can occur), in case the voltage of BLd is amplified to VDD, comparator C OM 205 work produce the YL activation signal.This moment physical memory location 202 the storage data after BL and SA203 amplify, through YL be output to the I/O line to (I/O and I/O ') on.Total delay time wherein: SA 207 amplifies BLd to the delay of the delay of VDD+comparator C OM 205.Because the delay of comparator C OM 205 is arranged, this moment, read rate was still slightly slow.For another example, when Vref is VDD-deltV-Vx, Vx is small voltage difference, can make BLd just begin to allow comparer work when reaching VDD-Vx, the setting of Vx should make: the delay that SA is amplified to VDD-Vx adds the delay of comparator C OM 205, is just in time that SA is amplified to the BL voltage difference delay of VDD.Consider in advance the delay of comparer this moment, can so that in a single day the voltage of BL be amplified to VDD, can activate YL output data.And for example, can not be transferred on the IO line and not through YL and read error can occur if actual storage does not need BL to reach VDD, after available required bit line amplifies, voltage Vini replaces VDD, be that reference voltage is made as Vbl-deltV, perhaps Vbl-deltV-Vx, can activate YL when the voltage of BLd reaches Vbl or Vbl-Vx.
Preferably, the control circuit of this array selecting signal also comprises be used to the voltage generation circuit 206 that generates the described voltage threshold that presets.Particularly, this voltage generation circuit 206 generates the voltage threshold Vref that presets, and provides it to this control circuit, with the comparison that is complementary for the amplification read-out voltage with described redundancy unit, when both mated, described array selecting signal generative circuit generated array selecting signal.
More preferably, this voltage generation circuit is used for generating adjustable described voltage threshold that presets, and as Vdd-deltV or Vdd-deltV-x, wherein x is very small.At this, deltV is the minimum sensitive voltage range of SA (perhaps comparator C OM), and such COM makes and only has when reaching Vdd to the voltage of BLd, and YL just opens.DRAM for design, BL voltage can not surpass Vdd, so the BL that voltage is Vdd necessarily can correctly be read out, so only need to guarantee that BL voltage is Vdd herein, in case but YL opens, BL voltage can reduce, can YL also open? as long as also satisfy the sensitive volume of SA, just can be amplified to VDD.But after just now opening, the voltage of YL has arrived the degree that MA can read, and does not need BL to repeat to have amplified again.Further instruction: Vref can be Vdd-deltV.Can be Vdd-deltV-x, x be very small, to consider the delays in work of COM.Perhaps to shift to an earlier date a bit, consider further to reduce Vref.The size of Vref depends on the electric capacity of IO line and the actual size of dummy BL electric capacity.
Fig. 3 is the another example signal sequential schematic diagram of control circuit of the array selecting signal of DRAM shown in Figure 2.In conjunction with Fig. 3, the principle of work of further setting forth the present embodiment is as follows:
1) in conjunction with structure in Fig. 2, when the voltage difference of BL and BL ' reached the amplitude that SA can work, SA_en was effective, and SA 203 starts working, and when the voltage on BL and BL ' in a single day was amplified to VDD and 0V, YL opened at once, and data are outputed to the I/O line to upper.(situation when this figure correspondence Vref=VDD-deltV-Vx)
2) when Vref=VDD-deltV, the unlatching of YL equals the delay of comparator C OM 205 during this period of time than late a period of time in Fig. 3.
3) when Vref=Vini-deltV-Vx, wherein Vini is less than or equal to VDD, in case BL is amplified to Vini (also not reaching VDD), YL namely is unlocked.
4) when Vref=Vini-deltV, wherein Vini is less than or equal to VDD, in case BL is amplified to Vini (also not reaching VDD), in the delay through one section comparator C OM 205, YL namely is unlocked.
Preferably, described redundancy unit 208 storage " 0 " all the time or storage " 1 " all the time in the read operation process.
A kind of dynamic RAM, it comprises the read path of the storage unit in storage array, storage array, it is characterized in that, also comprise redundancy unit in described storage array, described dynamic RAM also comprises the control circuit as the described array selecting signal of previous embodiment.The DRAM of this embodiment comprises storage array, and the specific constructive form of each storage unit in storage array is not restrictive, and for example, it can be the storage unit of 1T1C structure.A plurality of storage unit are pressed the form of row and column and are arranged, and in this example, several storage unit are pressed the form of row and column and arranged formation storage block (block), then arrange for a plurality of and form storage array.In this embodiment, also comprise redundancy unit in storage array, redundancy unit and storage unit comprise same device cell, are both identical unit and can prepare simultaneously and arrange together and form storage array.In concrete the application, the storage unit that also can specify a certain row or certain delegation is redundancy unit.In example shown in Figure 2, only schematically provided one of them storage unit 202 and the corresponding redundancy unit 208 of this storage unit 202 in the storage array, need to prove that each redundancy unit does not need corresponding one by one with each concrete storage unit, a plurality of storage unit can be corresponding to a redundancy unit.The concrete quantity of storage unit 202, redundancy unit 208 is not restrictive, and in other words, the memory capacity size of storage array is not restrictive; Simultaneously, only schematically provided 202 corresponding bit lines that connect or couple of storage unit in storage array to BL and BL ', word line WL, 208 corresponding redundant word line WLr that connect or couple of redundancy unit, redundant bit line are to BLr and BLr '.
The DRAM of this embodiment similarly comprises peripheral circuit, peripheral circuit can be according to outside input command, by bit line and word line biasing corresponding electric signal to choosing, to realize the wherein operation of the storage unit of a certain address (write operation, read operation and refresh operation etc.).In this invention, because its purpose is mainly in order to improve the speed of read operation, for making those skilled in the art understand the improvements of this invention,, parts or circuit module known in those skilled in the art peripheral circuit corresponding to other operation are listed no longer one by one.Peripheral circuit comprises sensor amplifier 203 at least, take the read operation of storage unit 202 as example, its bit line can input to sensor amplifier 203 to the voltage differential signal of BL and BL ', then export the I/O buffer of peripheral circuit to through sensor amplifier 203.The stored charge of storage unit 203 makes its bit line that couples reach the voltage difference of BL and BL ' and can allow the amplitude (being Δ V) of SA normal operation need certain hour, also namely exist to postpone, and it normally is expressed as the bitline delays of storage unit.In this embodiment, sensor amplifier 203 is in particular sense amplifier (Sense Amplifier, SA), and whether SA starts working and enable control signal by it and control.Preferably, SA is cross-couplings type SA.
Above example has mainly illustrated the control circuit of array selecting signal of the present invention and has comprised the DRAM of this control circuit.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and embodiment are regarded as illustrative and not restrictive, in the situation that do not break away from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (8)
1. the control circuit of the array selecting signal of a dynamic RAM, described control circuit comprises the array selecting signal generative circuit, it is characterized in that, described control circuit also comprises: with the corresponding redundancy unit of the storage unit of described dynamic RAM and redundant word line driver module;
Wherein, when the amplification read-out voltage of described redundancy unit was complementary with the voltage threshold that presets, described array selecting signal generative circuit generated array selecting signal.
2. the control circuit of array selecting signal as claimed in claim 1, is characterized in that, described array selecting signal generative circuit also comprises comparer, and described comparer is used for amplification read-out voltage and the described voltage threshold that presets of more described redundancy unit.
3. the control circuit of array selecting signal as claimed in claim 2, it is characterized in that, during less than the minimum sensitive volume of described comparer, the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets are complementary when the difference of the amplification read-out voltage of described redundancy unit and the described voltage threshold that presets.
4. as the control circuit of claim 1,2 or 3 described array selecting signals, it is characterized in that, described control circuit also comprises be used to the voltage generation circuit that generates the described voltage threshold that presets.
5. the control circuit of array selecting signal as claimed in claim 4, is characterized in that, described voltage generation circuit is used for generating adjustable described voltage threshold that presets.
6. the control circuit of column selection as claimed in claim 1, is characterized in that, described redundancy unit is storage " 0 " all the time or storage " 1 " all the time in the read operation process.
7. dynamic RAM, it comprises the read path of the storage unit in storage array, storage array, it is characterized in that, also comprise redundancy unit in described storage array, described dynamic RAM also comprises the control circuit as the described array selecting signal of any one in claim 1 to 10.
8. dynamic RAM as claimed in claim 7, is characterized in that, the preparation simultaneously in the storage array of described dynamic RAM of described storage unit and described redundancy unit forms.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110427171A (en) * | 2019-08-09 | 2019-11-08 | 复旦大学 | Expansible fixed-point number matrix multiply-add operation deposits interior calculating structures and methods |
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| CN101523500A (en) * | 2006-10-25 | 2009-09-02 | 高通股份有限公司 | Memory device with configurable delay tracking |
| CN101874271A (en) * | 2007-10-11 | 2010-10-27 | 莫塞德技术公司 | Interlock of read column select and read databus precharge control signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5596539A (en) * | 1995-12-28 | 1997-01-21 | Lsi Logic Corporation | Method and apparatus for a low power self-timed memory control system |
| CN101523500A (en) * | 2006-10-25 | 2009-09-02 | 高通股份有限公司 | Memory device with configurable delay tracking |
| CN101874271A (en) * | 2007-10-11 | 2010-10-27 | 莫塞德技术公司 | Interlock of read column select and read databus precharge control signals |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110427171A (en) * | 2019-08-09 | 2019-11-08 | 复旦大学 | Expansible fixed-point number matrix multiply-add operation deposits interior calculating structures and methods |
| CN110427171B (en) * | 2019-08-09 | 2022-10-18 | 复旦大学 | In-memory computing device and method for expandable fixed-point matrix multiply-add operation |
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