DE3686436T2 - Speichersystem mit hoher leistung. - Google Patents
Speichersystem mit hoher leistung.Info
- Publication number
- DE3686436T2 DE3686436T2 DE8686104221T DE3686436T DE3686436T2 DE 3686436 T2 DE3686436 T2 DE 3686436T2 DE 8686104221 T DE8686104221 T DE 8686104221T DE 3686436 T DE3686436 T DE 3686436T DE 3686436 T2 DE3686436 T2 DE 3686436T2
- Authority
- DE
- Germany
- Prior art keywords
- storage system
- high performance
- performance
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/722,920 US4685088A (en) | 1985-04-15 | 1985-04-15 | High performance memory system utilizing pipelining techniques |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3686436D1 DE3686436D1 (de) | 1992-09-24 |
DE3686436T2 true DE3686436T2 (de) | 1993-03-18 |
Family
ID=24903985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686104221T Expired - Fee Related DE3686436T2 (de) | 1985-04-15 | 1986-03-27 | Speichersystem mit hoher leistung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4685088A (de) |
EP (1) | EP0199134B1 (de) |
JP (1) | JPS61237289A (de) |
CA (1) | CA1233259A (de) |
DE (1) | DE3686436T2 (de) |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4817054A (en) * | 1985-12-04 | 1989-03-28 | Advanced Micro Devices, Inc. | High speed RAM based data serializers |
US4825416A (en) * | 1986-05-07 | 1989-04-25 | Advanced Micro Devices, Inc. | Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems |
US5237532A (en) * | 1986-06-30 | 1993-08-17 | Kabushiki Kaisha Toshiba | Serially-accessed type memory device for providing an interleaved data read operation |
JPS63129451A (ja) * | 1986-11-19 | 1988-06-01 | Matsushita Graphic Commun Syst Inc | メモリ制御回路 |
JPS63239675A (ja) * | 1986-11-27 | 1988-10-05 | Toshiba Corp | 半導体記憶装置 |
US4851990A (en) * | 1987-02-09 | 1989-07-25 | Advanced Micro Devices, Inc. | High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure |
JP2560020B2 (ja) * | 1987-02-18 | 1996-12-04 | 株式会社日立製作所 | 半導体記憶装置 |
JPH0612609B2 (ja) * | 1987-03-27 | 1994-02-16 | 株式会社東芝 | 半導体メモリ |
US4852061A (en) * | 1987-04-30 | 1989-07-25 | International Business Machines Corporation | High density, high performance register file having improved clocking means |
JPS63276138A (ja) * | 1987-04-30 | 1988-11-14 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | レジスタ・フアイル |
US4845677A (en) * | 1987-08-17 | 1989-07-04 | International Business Machines Corporation | Pipelined memory chip structure having improved cycle time |
US4937736A (en) * | 1987-11-30 | 1990-06-26 | International Business Machines Corporation | Memory controller for protected memory with automatic access granting capability |
JP2501344B2 (ja) * | 1987-12-26 | 1996-05-29 | 株式会社東芝 | デ―タ転送回路 |
JP2618422B2 (ja) * | 1988-02-08 | 1997-06-11 | 富士通株式会社 | 半導体記憶装置 |
US5107507A (en) * | 1988-05-26 | 1992-04-21 | International Business Machines | Bidirectional buffer with latch and parity capability |
JPH0214492A (ja) * | 1988-06-30 | 1990-01-18 | Toshiba Corp | 半導体メモリ |
JPH0267976A (ja) * | 1988-09-02 | 1990-03-07 | Advantest Corp | メモリ試験装置 |
JPH02116088A (ja) * | 1988-10-25 | 1990-04-27 | Nec Corp | 半導体記憶装置 |
JP2760431B2 (ja) * | 1988-12-21 | 1998-05-28 | 株式会社日立製作所 | メモリ |
US5086414A (en) * | 1988-11-17 | 1992-02-04 | Hitachi, Ltd. | Semiconductor device having latch means |
JPH02141993A (ja) * | 1988-11-21 | 1990-05-31 | Toshiba Corp | 半導体記憶装置 |
DE68928341T2 (de) * | 1988-12-05 | 1998-01-29 | Texas Instruments Inc | Integrierte Schaltungskonfiguration mit schneller örtlicher Zugriffszeit |
US5237670A (en) * | 1989-01-30 | 1993-08-17 | Alantec, Inc. | Method and apparatus for data transfer between source and destination modules |
US5093809A (en) * | 1989-04-21 | 1992-03-03 | Siemens Aktiengesellschaft | Static memory having pipeline registers |
GB2232797B (en) * | 1989-06-16 | 1993-12-08 | Samsung Semiconductor Inc | RAM based serial memory with pipelined look-ahead reading |
JPH0778989B2 (ja) * | 1989-06-21 | 1995-08-23 | 株式会社東芝 | 半導体メモリ装置 |
US5001671A (en) * | 1989-06-27 | 1991-03-19 | Vitelic Corporation | Controller for dual ported memory |
US4970690A (en) * | 1989-07-31 | 1990-11-13 | Atari Games Corporation | Memory cell arrangement supporting bit-serial arithmetic |
US4967398A (en) * | 1989-08-09 | 1990-10-30 | Ford Motor Company | Read/write random access memory with data prefetch |
US5107465A (en) * | 1989-09-13 | 1992-04-21 | Advanced Micro Devices, Inc. | Asynchronous/synchronous pipeline dual mode memory access circuit and method |
US5117428A (en) * | 1989-11-22 | 1992-05-26 | Unisys Corporation | System for memory data integrity |
US5311471A (en) * | 1989-11-27 | 1994-05-10 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US5261068A (en) * | 1990-05-25 | 1993-11-09 | Dell Usa L.P. | Dual path memory retrieval system for an interleaved dynamic RAM memory unit |
JPH04176094A (ja) * | 1990-11-08 | 1992-06-23 | Nec Ic Microcomput Syst Ltd | メモリic |
JP3179788B2 (ja) * | 1991-01-17 | 2001-06-25 | 三菱電機株式会社 | 半導体記憶装置 |
US5430677A (en) * | 1991-02-11 | 1995-07-04 | Intel Corporation | Architecture for reading information from a memory array |
US5295255A (en) * | 1991-02-22 | 1994-03-15 | Electronic Professional Services, Inc. | Method and apparatus for programming a solid state processor with overleaved array memory modules |
JP3178859B2 (ja) * | 1991-06-05 | 2001-06-25 | 株式会社東芝 | ランダムアクセスメモリ装置およびそのパイプライン・ページモード制御方法 |
JP2932790B2 (ja) * | 1991-09-27 | 1999-08-09 | 日本電気株式会社 | ダイナミック型ランダムアクセスメモリ装置 |
JPH05266652A (ja) * | 1992-03-23 | 1993-10-15 | Hitachi Ltd | パイプライン動作型メモリシステム |
US5471607A (en) * | 1993-04-22 | 1995-11-28 | Analog Devices, Inc. | Multi-phase multi-access pipeline memory system |
US5410670A (en) * | 1993-06-02 | 1995-04-25 | Microunity Systems Engineering, Inc. | Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory |
US5794026A (en) * | 1993-10-18 | 1998-08-11 | National Semiconductor | Microprocessor having expedited execution of condition dependent instructions |
US5644741A (en) * | 1993-10-18 | 1997-07-01 | Cyrix Corporation | Processor with single clock decode architecture employing single microROM |
EP0649083B1 (de) * | 1993-10-18 | 2000-07-19 | National Semiconductor Corporation | Mikrosteuereinheit für einen superpipeline-superskalaren Mikroprozessor |
US5544101A (en) * | 1994-03-28 | 1996-08-06 | Texas Instruments Inc. | Memory device having a latching multiplexer and a multiplexer block therefor |
US5630096A (en) * | 1995-05-10 | 1997-05-13 | Microunity Systems Engineering, Inc. | Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order |
US5644387A (en) * | 1995-06-07 | 1997-07-01 | Hughes Electronics | High-speed data register for laser range finders |
TW301747B (de) * | 1995-06-08 | 1997-04-01 | Matsushita Electric Ind Co Ltd | |
US5691956A (en) * | 1996-07-17 | 1997-11-25 | Chang; Edward C. M. | Memory with fast decoding |
US5737262A (en) * | 1996-08-08 | 1998-04-07 | Micron Technology, Inc. | Method and apparatus for avoiding back-to-back data rewrites to a memory array |
JP4059951B2 (ja) * | 1997-04-11 | 2008-03-12 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
US7796464B1 (en) | 2003-06-27 | 2010-09-14 | Cypress Semiconductor Corporation | Synchronous memory with a shadow-cycle counter |
JP4214978B2 (ja) * | 2004-05-18 | 2009-01-28 | ソニー株式会社 | 半導体記憶装置および信号処理システム |
US8745016B2 (en) * | 2011-06-17 | 2014-06-03 | International Business Machines Corporation | Managing concurrent access to data in database system |
KR102354680B1 (ko) * | 2018-02-23 | 2022-01-25 | 에스케이하이닉스 주식회사 | 메모리 장치 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3900836A (en) * | 1973-11-30 | 1975-08-19 | Ibm | Interleaved memory control signal handling apparatus using pipelining techniques |
US4156905A (en) * | 1974-02-28 | 1979-05-29 | Ncr Corporation | Method and apparatus for improving access speed in a random access memory |
US4057846A (en) * | 1976-06-07 | 1977-11-08 | International Business Machines Corporation | Bus steering structure for low cost pipelined processor system |
US4110842A (en) * | 1976-11-15 | 1978-08-29 | Advanced Micro Devices, Inc. | Random access memory with memory status for improved access and cycle times |
US4106109A (en) * | 1977-02-01 | 1978-08-08 | Ncr Corporation | Random access memory system providing high-speed digital data output |
US4253147A (en) * | 1979-04-09 | 1981-02-24 | Rockwell International Corporation | Memory unit with pipelined cycle of operations |
JPS6012718B2 (ja) * | 1980-03-28 | 1985-04-03 | 富士通株式会社 | 半導体ダイナミックメモリ |
JPS57135489A (en) * | 1981-02-16 | 1982-08-21 | Nippon Telegr & Teleph Corp <Ntt> | Storage device |
JPS58128097A (ja) * | 1981-12-29 | 1983-07-30 | Fujitsu Ltd | 半導体記憶装置 |
US4509142A (en) * | 1982-12-15 | 1985-04-02 | Texas Instruments Incorporated | Semiconductor memory device with pipeline access |
GB2138230B (en) * | 1983-04-12 | 1986-12-03 | Sony Corp | Dynamic random access memory arrangements |
JPS6059462A (ja) * | 1983-09-12 | 1985-04-05 | Nec Corp | 双方向デ−タ・バスのパイプライン・アクセス・メモリ |
JPS61148692A (ja) * | 1984-12-24 | 1986-07-07 | Nippon Telegr & Teleph Corp <Ntt> | 記憶装置 |
-
1985
- 1985-04-15 US US06/722,920 patent/US4685088A/en not_active Expired - Lifetime
- 1985-09-20 CA CA000491265A patent/CA1233259A/en not_active Expired
-
1986
- 1986-02-18 JP JP61032055A patent/JPS61237289A/ja active Granted
- 1986-03-27 EP EP86104221A patent/EP0199134B1/de not_active Expired - Lifetime
- 1986-03-27 DE DE8686104221T patent/DE3686436T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4685088A (en) | 1987-08-04 |
EP0199134A3 (en) | 1990-03-14 |
JPS61237289A (ja) | 1986-10-22 |
JPH0368476B2 (de) | 1991-10-28 |
EP0199134A2 (de) | 1986-10-29 |
EP0199134B1 (de) | 1992-08-19 |
CA1233259A (en) | 1988-02-23 |
DE3686436D1 (de) | 1992-09-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |