DE69608125T2 - Verfahren und vorrichtung für selbstgetaktetes speichersteuerungssystem mit niedrigem stromverbrauch - Google Patents

Verfahren und vorrichtung für selbstgetaktetes speichersteuerungssystem mit niedrigem stromverbrauch

Info

Publication number
DE69608125T2
DE69608125T2 DE69608125T DE69608125T DE69608125T2 DE 69608125 T2 DE69608125 T2 DE 69608125T2 DE 69608125 T DE69608125 T DE 69608125T DE 69608125 T DE69608125 T DE 69608125T DE 69608125 T2 DE69608125 T2 DE 69608125T2
Authority
DE
Germany
Prior art keywords
self
control system
power consumption
low power
storage control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69608125T
Other languages
English (en)
Other versions
DE69608125D1 (de
Inventor
W Passow
W Priebe
D Isliefson
Ross Mactaggart
R Leclair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69608125D1 publication Critical patent/DE69608125D1/de
Publication of DE69608125T2 publication Critical patent/DE69608125T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08Control thereof
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/227Timing of memory operations based on dummy memory elements or replica circuits
DE69608125T 1995-12-28 1996-12-06 Verfahren und vorrichtung für selbstgetaktetes speichersteuerungssystem mit niedrigem stromverbrauch Expired - Lifetime DE69608125T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/579,792 US5596539A (en) 1995-12-28 1995-12-28 Method and apparatus for a low power self-timed memory control system
PCT/US1996/020259 WO1997024726A1 (en) 1995-12-28 1996-12-06 Method and apparatus for a low power self-timed memory control system

Publications (2)

Publication Number Publication Date
DE69608125D1 DE69608125D1 (de) 2000-06-08
DE69608125T2 true DE69608125T2 (de) 2001-01-11

Family

ID=24318383

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69608125T Expired - Lifetime DE69608125T2 (de) 1995-12-28 1996-12-06 Verfahren und vorrichtung für selbstgetaktetes speichersteuerungssystem mit niedrigem stromverbrauch

Country Status (5)

Country Link
US (1) US5596539A (de)
EP (1) EP0871956B1 (de)
JP (1) JP2000516008A (de)
DE (1) DE69608125T2 (de)
WO (1) WO1997024726A1 (de)

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EP1122735B1 (de) 2000-01-31 2010-09-01 STMicroelectronics Srl Verschachtelter Datenpfad und Ausgabesteuerungsarchitektur für einen verschachtelten Speicher sowie Impulsgeber zum Ausgeben von gelesenen Daten
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EP1122736B1 (de) 2000-01-31 2009-10-28 STMicroelectronics S.r.l. Erzeugung eines Addressenübergangssignals (ATD) für eine synchrone Speicheranordnung
EP1122737A1 (de) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Schaltung zur Steuerung von Datenströmenübertragung aus mehrerer Quellen eines Systems
EP1130517B1 (de) 2000-03-02 2004-05-26 STMicroelectronics S.r.l. Redundanzarchitektur bei einem verschachtelten Speicher
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JP4894095B2 (ja) * 2001-06-15 2012-03-07 富士通セミコンダクター株式会社 半導体記憶装置
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US6940770B2 (en) * 2003-01-21 2005-09-06 Hewlett-Packard Development Company, L.P. Method for precharging word and bit lines for selecting memory cells within a memory array
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
WO2005052944A1 (ja) * 2003-11-28 2005-06-09 Fujitsu Limited セルフタイミング回路を有する半導体メモリ
JP4598420B2 (ja) * 2004-03-18 2010-12-15 富士通セミコンダクター株式会社 半導体記憶装置、及びタイミング制御方法
EP1630815B1 (de) * 2004-08-24 2011-10-05 Infineon Technologies AG Speicherschaltung mit spannungsversorgungsnachgebiegkeit und einer an spannunasversorgung angepassten leistung
KR100541370B1 (ko) * 2004-09-06 2006-01-10 주식회사 하이닉스반도체 반도체메모리소자
JP4836162B2 (ja) * 2004-11-26 2011-12-14 株式会社リコー 半導体集積回路
JP2006164399A (ja) * 2004-12-07 2006-06-22 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7221607B1 (en) * 2005-02-09 2007-05-22 Lattice Semiconductor Corporation Multi-port memory systems and methods for bit line coupling
US7693002B2 (en) * 2006-10-10 2010-04-06 Qualcomm Incorporated Dynamic word line drivers and decoders for memory arrays
US7755964B2 (en) * 2006-10-25 2010-07-13 Qualcomm Incorporated Memory device with configurable delay tracking
US7646658B2 (en) * 2007-05-31 2010-01-12 Qualcomm Incorporated Memory device with delay tracking for improved timing margin
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US20090109772A1 (en) * 2007-10-24 2009-04-30 Esin Terzioglu Ram with independent local clock
US7859920B2 (en) * 2008-03-14 2010-12-28 Qualcomm Incorporated Advanced bit line tracking in high performance memory compilers
US7864625B2 (en) * 2008-10-02 2011-01-04 International Business Machines Corporation Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator
US8082401B2 (en) * 2009-03-25 2011-12-20 Qualcomm Incorporated Self-timing for a multi-ported memory system
JP5452348B2 (ja) * 2009-07-27 2014-03-26 ルネサスエレクトロニクス株式会社 半導体記憶装置
US8279659B2 (en) * 2009-11-12 2012-10-02 Qualcomm Incorporated System and method of operating a memory device
CN102682827B (zh) * 2011-03-14 2015-03-04 复旦大学 Dram的读出放大器的控制电路及包括其的dram
JP5677205B2 (ja) * 2011-06-13 2015-02-25 ルネサスエレクトロニクス株式会社 半導体記憶装置
CN103123806B (zh) * 2011-11-20 2016-08-03 复旦大学 Dram的列选择信号的控制电路及包括其的存取存储器
US8848414B2 (en) 2012-10-22 2014-09-30 International Business Machines Corporation Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
US9281032B2 (en) * 2014-04-10 2016-03-08 Infineon Technologies Ag Memory timing circuit
KR102491136B1 (ko) * 2015-12-18 2023-01-25 에스케이하이닉스 주식회사 수신 장치, 이를 이용하는 반도체 장치 및 시스템
US9852024B2 (en) * 2016-04-19 2017-12-26 Winbond Electronics Corporation Apparatus and method for read time control in ECC-enabled flash memory
FR3061798B1 (fr) * 2017-01-10 2019-08-02 Dolphin Integration Circuit de commande d'une ligne d'une matrice memoire
US10283191B1 (en) * 2018-03-09 2019-05-07 Stmicroelectronics International N.V. Method and circuit for adaptive read-write operation in self-timed memory
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Also Published As

Publication number Publication date
WO1997024726A1 (en) 1997-07-10
EP0871956A1 (de) 1998-10-21
EP0871956B1 (de) 2000-05-03
JP2000516008A (ja) 2000-11-28
DE69608125D1 (de) 2000-06-08
US5596539A (en) 1997-01-21

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