EP2054803A4 - Memory circuit system and method - Google Patents

Memory circuit system and method

Info

Publication number
EP2054803A4
EP2054803A4 EP07870726A EP07870726A EP2054803A4 EP 2054803 A4 EP2054803 A4 EP 2054803A4 EP 07870726 A EP07870726 A EP 07870726A EP 07870726 A EP07870726 A EP 07870726A EP 2054803 A4 EP2054803 A4 EP 2054803A4
Authority
EP
European Patent Office
Prior art keywords
memory circuit
circuit system
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP07870726A
Other languages
German (de)
French (fr)
Other versions
EP2054803A2 (en
Inventor
Suresh Natarajan Rajan
Keith R Schakel
Michael John Sebastian Smith
David T Wang
Frederick Daniel Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
MetaRAM Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,439 external-priority patent/US7580312B2/en
Priority claimed from US11/524,812 external-priority patent/US7386656B2/en
Priority claimed from US11/524,716 external-priority patent/US7392338B2/en
Priority claimed from US11/524,811 external-priority patent/US7590796B2/en
Priority claimed from US11/524,730 external-priority patent/US7472220B2/en
Priority claimed from US11/538,041 external-priority patent/US20080082763A1/en
Priority claimed from US11/762,010 external-priority patent/US8041881B2/en
Priority claimed from US11/762,013 external-priority patent/US8090897B2/en
Priority to EP12150807.1A priority Critical patent/EP2442310A3/en
Application filed by MetaRAM Inc filed Critical MetaRAM Inc
Priority to EP18166674.4A priority patent/EP3364298B1/en
Priority to EP12150798A priority patent/EP2442309A3/en
Publication of EP2054803A2 publication Critical patent/EP2054803A2/en
Publication of EP2054803A4 publication Critical patent/EP2054803A4/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
EP07870726A 2006-07-31 2007-07-18 Memory circuit system and method Ceased EP2054803A4 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP12150807.1A EP2442310A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit
EP12150798A EP2442309A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit system
EP18166674.4A EP3364298B1 (en) 2006-07-31 2007-07-18 Memory circuit system and method

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US11/461,439 US7580312B2 (en) 2006-07-31 2006-07-31 Power saving system and method for use with a plurality of memory circuits
US11/524,716 US7392338B2 (en) 2006-07-31 2006-09-20 Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US11/524,730 US7472220B2 (en) 2006-07-31 2006-09-20 Interface circuit system and method for performing power management operations utilizing power management signals
US11/524,812 US7386656B2 (en) 2006-07-31 2006-09-20 Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US11/524,811 US7590796B2 (en) 2006-07-31 2006-09-20 System and method for power management in memory systems
US11/538,041 US20080082763A1 (en) 2006-10-02 2006-10-02 Apparatus and method for power management of memory circuits by a system or component thereof
US11/584,179 US7581127B2 (en) 2006-07-31 2006-10-20 Interface circuit system and method for performing power saving operations during a command-related latency
US11/762,010 US8041881B2 (en) 2006-07-31 2007-06-12 Memory device with emulated characteristics
US11/762,013 US8090897B2 (en) 2006-07-31 2007-06-12 System and method for simulating an aspect of a memory circuit
PCT/US2007/016385 WO2008063251A2 (en) 2006-07-31 2007-07-18 Memory circuit system and method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP18166674.4A Division EP3364298B1 (en) 2006-07-31 2007-07-18 Memory circuit system and method

Publications (2)

Publication Number Publication Date
EP2054803A2 EP2054803A2 (en) 2009-05-06
EP2054803A4 true EP2054803A4 (en) 2009-10-21

Family

ID=56290996

Family Applications (4)

Application Number Title Priority Date Filing Date
EP12150798A Withdrawn EP2442309A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit system
EP18166674.4A Active EP3364298B1 (en) 2006-07-31 2007-07-18 Memory circuit system and method
EP07870726A Ceased EP2054803A4 (en) 2006-07-31 2007-07-18 Memory circuit system and method
EP12150807.1A Ceased EP2442310A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit

Family Applications Before (2)

Application Number Title Priority Date Filing Date
EP12150798A Withdrawn EP2442309A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit system
EP18166674.4A Active EP3364298B1 (en) 2006-07-31 2007-07-18 Memory circuit system and method

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP12150807.1A Ceased EP2442310A3 (en) 2006-07-31 2007-07-18 Power management for memory circuit

Country Status (3)

Country Link
EP (4) EP2442309A3 (en)
DK (1) DK3364298T3 (en)
WO (1) WO2008063251A2 (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8639874B2 (en) * 2008-12-22 2014-01-28 International Business Machines Corporation Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device
US9105323B2 (en) * 2009-01-23 2015-08-11 Micron Technology, Inc. Memory device power managers and methods
US8811110B2 (en) * 2012-06-28 2014-08-19 Intel Corporation Configuration for power reduction in DRAM
US10586795B1 (en) * 2018-04-30 2020-03-10 Micron Technology, Inc. Semiconductor devices, and related memory devices and electronic systems
US11282815B2 (en) 2020-01-14 2022-03-22 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices and electronic systems
US11335602B2 (en) 2020-06-18 2022-05-17 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices and electronic systems
US11699652B2 (en) 2020-06-18 2023-07-11 Micron Technology, Inc. Microelectronic devices and electronic systems
US11380669B2 (en) 2020-06-18 2022-07-05 Micron Technology, Inc. Methods of forming microelectronic devices
US11563018B2 (en) 2020-06-18 2023-01-24 Micron Technology, Inc. Microelectronic devices, and related methods, memory devices, and electronic systems
US11705367B2 (en) 2020-06-18 2023-07-18 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices, memory devices, electronic systems, and additional methods
US11557569B2 (en) 2020-06-18 2023-01-17 Micron Technology, Inc. Microelectronic devices including source structures overlying stack structures, and related electronic systems
US11587919B2 (en) 2020-07-17 2023-02-21 Micron Technology, Inc. Microelectronic devices, related electronic systems, and methods of forming microelectronic devices
US11417676B2 (en) 2020-08-24 2022-08-16 Micron Technology, Inc. Methods of forming microelectronic devices and memory devices, and related microelectronic devices, memory devices, and electronic systems
US11825658B2 (en) 2020-08-24 2023-11-21 Micron Technology, Inc. Methods of forming microelectronic devices and memory devices
EP4248444A1 (en) * 2020-11-23 2023-09-27 Qualcomm Incorporated Method and system for refreshing memory of a portable computing device
US11751408B2 (en) 2021-02-02 2023-09-05 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
US11930634B2 (en) 2021-06-30 2024-03-12 Micron Technology, Inc. Methods of forming microelectronic devices
US11842990B2 (en) 2021-06-30 2023-12-12 Micron Technology, Inc. Microelectronic devices and electronic systems
US11776925B2 (en) 2021-06-30 2023-10-03 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices and electronic systems
US11810838B2 (en) 2021-06-30 2023-11-07 Micron Technology, Inc. Microelectronic devices, and related electronic systems and methods of forming microelectronic devices
US11785764B2 (en) 2021-06-30 2023-10-10 Micron Technology, Inc. Methods of forming microelectronic devices
US11837594B2 (en) 2021-06-30 2023-12-05 Micron Technology, Inc. Microelectronic devices and electronic systems
US11751383B2 (en) 2021-08-31 2023-09-05 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices and electronic systems
US11791273B2 (en) 2021-10-13 2023-10-17 Micron Technology, Inc. Microelectronic devices including contact structures, and related memory devices, electronic systems, and methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644547A2 (en) * 1993-09-13 1995-03-22 International Business Machines Corporation Integrated multichip memory module, structure and fabrication
US5590071A (en) * 1995-11-16 1996-12-31 International Business Machines Corporation Method and apparatus for emulating a high capacity DRAM
WO2001090900A1 (en) * 2000-05-23 2001-11-29 Smart Modular Technologies, (Ma) Inc. The method of emulating different protocol of flash memory
WO2001097160A1 (en) * 2000-06-14 2001-12-20 Bull Hn Information Systems, Inc. Method and data processing system for emulating virtual memory working spaces
US20020129204A1 (en) * 2001-03-06 2002-09-12 Lance Leighnor Hypercache RAM based disk emulation and method
US20020165706A1 (en) * 2001-05-03 2002-11-07 Raynham Michael B. Memory controller emulator

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181640B1 (en) * 1997-06-24 2001-01-30 Hyundai Electronics Industries Co., Ltd. Control circuit for semiconductor memory device
US5835435A (en) * 1997-12-02 1998-11-10 Intel Corporation Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US6523089B2 (en) * 2000-07-19 2003-02-18 Rambus Inc. Memory controller with power management logic
US6356500B1 (en) * 2000-08-23 2002-03-12 Micron Technology, Inc. Reduced power DRAM device and method
US6781911B2 (en) * 2002-04-09 2004-08-24 Intel Corporation Early power-down digital memory device and method
US7549066B2 (en) * 2002-11-15 2009-06-16 Intel Corporation Automatic power savings stand-by control for non-volatile memory
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7752470B2 (en) * 2003-12-03 2010-07-06 International Business Machines Corporation Method and system for power management including device controller-based device use evaluation and power-state control
US7085152B2 (en) * 2003-12-29 2006-08-01 Intel Corporation Memory system segmented power supply and control
US7366931B2 (en) * 2004-12-30 2008-04-29 Intel Corporation Memory modules that receive clock information and are placed in a low power state
US20060181949A1 (en) * 2004-12-31 2006-08-17 Kini M V Operating system-independent memory power management

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644547A2 (en) * 1993-09-13 1995-03-22 International Business Machines Corporation Integrated multichip memory module, structure and fabrication
US5590071A (en) * 1995-11-16 1996-12-31 International Business Machines Corporation Method and apparatus for emulating a high capacity DRAM
WO2001090900A1 (en) * 2000-05-23 2001-11-29 Smart Modular Technologies, (Ma) Inc. The method of emulating different protocol of flash memory
WO2001097160A1 (en) * 2000-06-14 2001-12-20 Bull Hn Information Systems, Inc. Method and data processing system for emulating virtual memory working spaces
US20020129204A1 (en) * 2001-03-06 2002-09-12 Lance Leighnor Hypercache RAM based disk emulation and method
US20020165706A1 (en) * 2001-05-03 2002-11-07 Raynham Michael B. Memory controller emulator

Also Published As

Publication number Publication date
EP2054803A2 (en) 2009-05-06
WO2008063251A3 (en) 2008-10-16
WO2008063251A2 (en) 2008-05-29
EP3364298B1 (en) 2019-12-11
EP2442310A3 (en) 2013-04-24
EP2442309A3 (en) 2013-01-23
EP3364298A2 (en) 2018-08-22
DK3364298T3 (en) 2020-03-02
EP3364298A3 (en) 2018-11-28
EP2442309A2 (en) 2012-04-18
EP2442310A2 (en) 2012-04-18

Similar Documents

Publication Publication Date Title
EP2054803A4 (en) Memory circuit system and method
IL186614A0 (en) Memory repair system and method
GB2427721B (en) System and method for communicating with memory devices
TWI348677B (en) System for increasing circuit reliability and method thereof
TWI340386B (en) Semiconductor memory and memory system
HK1121287A1 (en) Memory module system and method
GB201109817D0 (en) System and method
GB2429805B (en) Memory correction system and method
EP2023461A4 (en) Charging circuit, charging system, and charging method
EP2126915A4 (en) Memory system and method with serial and parallel modes
EP2088097A4 (en) Storage system and storage method
EP2075703A4 (en) Memory control circuit, method, and integrated circuit
EP2095285A4 (en) Manufacturing system and method
EP1934840A4 (en) Electronic discovery system and method
IL174186A0 (en) Reliability simulation method and system
HK1119298A1 (en) Protection circuit and method therefor
EP2012407A4 (en) Charging circuit and its charging method
IL192759A0 (en) New method and system
EP2047367A4 (en) Memory system and memory chip
IL200641A0 (en) System and method for circuit design scaling
EP1988730A4 (en) Radio access system and radio access method
EP1971072A4 (en) Electronic bidding system and electronic bidding method
GB2440186B (en) Protection circuit and method
TWI366666B (en) Thermocouple circuit and method and system for forming same
EP1912222A4 (en) Memory control method and memory system

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20090227

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

A4 Supplementary search report drawn up and despatched

Effective date: 20090921

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20100111

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: GOOGLE INC.

REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20120514

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230519