US20010000949A1 - Integrated circuit memory devices having programmable output driver circuits therein - Google Patents
Integrated circuit memory devices having programmable output driver circuits therein Download PDFInfo
- Publication number
- US20010000949A1 US20010000949A1 US09/753,927 US75392701A US2001000949A1 US 20010000949 A1 US20010000949 A1 US 20010000949A1 US 75392701 A US75392701 A US 75392701A US 2001000949 A1 US2001000949 A1 US 2001000949A1
- Authority
- US
- United States
- Prior art keywords
- pull
- driver circuit
- electrically coupled
- down driver
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
Definitions
- the present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having output driver circuits therein.
- Integrated circuit devices may contain specialized output driver circuits therein for driving external devices when the loads associated with the external devices are appreciable.
- an integrated circuit device may also be provided having a plurality of memory modules 111 , 113 , 115 and 117 therein which are electrically coupled to a data bus (DATA), a command bus (CMD) and a chip select (CS) signal line.
- Each memory module may itself be comprised of a plurality of memory devices 101 , 103 , 105 and 107 .
- an increase in the number of memory modules on an integrated circuit system board may lead to unbalanced loading on the memory modules. Such unbalanced loading may be caused by the unequal lengths in the signal lines connected to the modules and may result in clock skew which limits high frequency performance.
- FIG. 2 illustrates a conventional output driver circuit which comprises a PMOS pull-up transistor P 1 and an NMOS pull-down transistor N 1 , connected as illustrated.
- a PMOS pull-up transistor P 1 and an NMOS pull-down transistor N 1 connected as illustrated.
- application of logic 0 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P 1 and NMOS pull-down transistor N 1 will cause the output DOUT to be pulled to VCC.
- application of logic 1 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P 1 and NMOS pull-down transistor N 1 will cause the output DOUT to be pulled to VSS.
- FIG. 3 illustrates another conventional output driver circuit which comprises an NMOS pull-up transistor N 2 and an NMOS pull-down transistor N 3 , connected as illustrated.
- application of logic 1 and logic 0 signals as DOKP and DOKN, respectively will cause the output DOUT to be pulled to VCC.
- application of logic 0 and logic 1 signals as DOKP and DOKN, respectively will cause the output DOUT to be pulled to VSS.
- simultaneous application of logic 0 signals as DOKP and DOKN will cause the output DOUT to float in a high impedance state.
- Driver circuits which contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively.
- Driver circuits include first and second control signal lines (e.g., MRS 1 , MRS 2 ), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS 1 ) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS 2 ) and a second control input.
- MRS 1 control signal line
- MRS 2 second control input
- First and second complementary control signals lines are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively.
- These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.
- the first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors.
- the first and second NMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first control input, respectively
- the first and second PMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively.
- the plurality of pull-up/pull-down driver circuits may each comprise four MOS transistors of the same type electrically connected in series between first and second supply signal lines (e.g., VCC and VSS).
- a pull-up/pull-down driver circuit which is always active to provide a baseline level of drive capability.
- a third pull-up/pull-down driver circuit may be provided which comprises only a single pair of MOS transistors and has first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively.
- a controller is preferably provided which generates a first pair of complementary control signals on the first control signal line and the first complementary control signal line and generates a second pair of complementary control signals on the second control signal line and the second complementary control signal line, in response to command signals and an address.
- a memory array may also be provided which is electrically coupled to a pair of differential data lines and a data buffer may be provided which has first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit.
- FIG. 1 is a block diagram of a system board containing a memory module array therein, according to the prior art.
- FIG. 2 is an electrical schematic of an output driver circuit according to the prior art.
- FIG. 3 is an electrical schematic of another output driver circuit according to the prior art.
- FIG. 4 is a block diagram of a preferred memory device according to an embodiment of the present invention.
- FIG. 5 is an electrical schematic of the programmable output driver of FIG. 4, according to a first embodiment of the present invention.
- FIG. 6 is an electrical schematic of the programmable output driver of FIG. 4, according to a second embodiment of the present invention.
- FIG. 7 is a block diagram of the controller of FIG. 4.
- FIG. 8 is an electrical schematic of an embodiment of the control signal generator of FIG. 7.
- FIG. 9 is a timing diagram which illustrates operation of the controller of FIG. 7.
- a preferred memory device includes a memory cell array block 401 , a data output buffer 403 , a programmable output driver 405 (which is coupled to an output pad DOUT) and an output driver controller 407 .
- the data output buffer 403 receives differential output data from the memory cell array block 401 via complementary data buses DB and ⁇ overscore (DB) ⁇ , and generates first and second output signals DOKP and DOKN.
- the programmable output driver 405 has a driving capability which can be varied in response to a plurality of control signals MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ and in response to the first and second output signals DOKP and DOKN.
- the output driver controller 407 is also provided to generate the plurality of control signals MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ , in response to command signals (CMD) and address signals A 1 -A 4 .
- These command signals include a row address strobe signal ⁇ overscore (RAS) ⁇ , a column address strobe signal ⁇ overscore (CAS) ⁇ and a write enable signal ⁇ overscore (WE) ⁇ .
- the driving capability of the preferred output driver 405 can be programmed when the command signals ⁇ overscore (RAS) ⁇ , ⁇ overscore (GAS) ⁇ and ⁇ overscore (WE) ⁇ are properly activated, the addresses A 1 -A 4 are applied and the plurality of control signals MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ are generated. These control signals are generated at respective complementary levels based on the values of the addresses A 1 -A 4 , as described more fully hereinbelow with respect to FIGS. 7-8.
- the size of the output driver for each memory device can be selectively programmed to account for different loading conditions associated with each device and module.
- the skew between signals generated by memory devices within modules at different positions within a system board can be efficiently reduced.
- the programmable output driver circuit 405 includes four output driving units 501 , 503 , 505 and 507 for driving an output pad DOUT in response to first and second output signals DOKP and DOKN.
- Each of the output driving units 501 , 503 , 505 and 507 is independently controlled by corresponding control signals MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ .
- MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ The number of programmable output driving units can be adjusted depending upon application.
- Each of the output driving units 501 , 503 , 505 and 507 includes: (i) PMOS switch transistors 501 a, 503 a, 505 a and 507 a (each of which has a source to which a power supply voltage VCC is applied and a gate to which a corresponding inverted control signal, one of ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ , is applied); (ii) PMOS pull-up transistors 501 b , 503 b , 505 b and 507 b (each of which has a source connected to a respective drain of a PMOS switch transistor, a gate to which the first output signal DOKP is applied and a drain connected to the pad DOUT); (iii) NMOS pull-down transistors 501 c , 503 c , 505 c and 507 c (each of which has a drain connected to the pad DOUT and a gate to which the second output signal DOK
- the effective size of the output driver 405 can be controlled by selectively turning on or off the PMOS switch transistors 501 a , 503 a , 505 a and 507 a (which are controlled by the inverted control signals ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ ) and turning on or off the corresponding NMOS switch transistors 501 d , 503 d , 505 d and 507 d controlled by the control signals MRS 1 -MRS 4 .
- the PMOS switch transistors 501 a , 503 a , 505 a and 507 a and the NMOS switch transistors 501 d , 503 d , 505 d and 507 d of the output driving units 501 , 503 , 505 and 507 are all turned on.
- This means the driving units 501 , 503 , 505 and 507 all drive the output pad DOUT in parallel in response to the first and second output signals DOKP and DOKN.
- control signals MRS 1 -MRS 4 are set to (0,0,0,1), the PMOS switch transistors 501 a , 503 a and 505 a and the NMOS switch transistors 501 d , 503 d and 505 d of the output driving units 501 , 503 and 505 are turned off, and the PMOS switch transistor 507 a and the NMOS switch transistor 507 d of the output driving unit 507 are turned on. Accordingly, only a single driving unit 507 drives the output pad DOUT in response to the first and second output signals DOKP and DOKN. Finally, when the control signals MRS 1 -MRS 4 are set to (0,0,0,0), no output drive capability is provided.
- an additional driving unit can be added which is not responsive to the control signals.
- the programmable output driver circuit 405 of FIG. 6 includes an additional driving unit 609 which is responsive to the first and second output signals DOKP and DOKN and provides output drive capability even if the control signals MRS 1 -MRS 4 are set to (0,0,0,0).
- the programmable output driver circuit 405 includes five output driving units 601 , 603 , 605 , 607 and 609 for driving an output pad DOUT in response to first and second output signals DOKP and DOKN.
- Each of the output driving units 601 , 603 , 605 and 607 is independently controlled by corresponding control signals MRS 1 / ⁇ overscore (MRS 1 ) ⁇ -MRS 4 / ⁇ overscore (MRS 4 ) ⁇ .
- Each of the output driving units 601 , 603 , 605 and 607 includes: (i) PMOS switch transistors 601 a , 603 a , 605 a and 607 a (each of which has a source to which a power supply voltage VCC is applied and a gate to which a corresponding inverted control signal, one of ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ , is applied); (ii) PMOS pull-up transistors 601 b , 603 b , 605 b and 607 b (each of which has a source connected to a respective drain of a PMOS switch transistor, a gate to which the first output signal DOKP is applied and a drain connected to the pad DOUT); (iii) NMOS pull-down transistors 601 c , 603 c , 605 c and 607 c (each of which has a drain connected to the pad DOUT and a gate to which the second output signal
- the effective size of the output driver 405 can be controlled by selective turning on or off the PMOS switch transistors 601 a, 603 a , 605 a and 607 a (which are controlled by the inverted control signals ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ ) and turning on or off the corresponding NMOS switch transistors 601 d, 603 d, 605 d and 607 d controlled by the control signals MRS 1 -MRS 4 .
- the PMOS switch transistors 601 a, 603 a , 605 a and 607 a and the NMOS switch transistors 601 d , 603 d , 605 d and 607 d of the output driving units 601 , 603 , 605 and 607 are all turned on.
- the driving units 601 , 603 , 605 , 607 and 609 all drive the output pad DOUT in parallel in response to the first and second output signals DOKP and DOKN.
- the PMOS switch transistors 601 a, 603 a and 605 a and the NMOS switch transistors 601 d , 603 d and 605 d of the output driving units 601 , 603 and 605 are turned off, and the PMOS switch transistor 607 a and the NMOS switch transistor 607 d of the output driving unit 607 are turned on. Accordingly, only driving units 607 and 609 drive the output pad DOUT in response to the first and second output signals DOKP and DOKN.
- Alternative embodiments of the above described driver circuit 405 may also be provided.
- NMOS transistors may be substituted for the PMOS transistors 601 b , 603 b , 605 b , 607 b and 609 a of FIG. 6.
- the inverted control signals ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ need not be generated.
- the output driver controller 407 of FIG. 4 preferably includes a mode register set controller 701 , a control signal generator 703 and an address buffer 705 .
- the mode register set controller 701 receives a clock signal CLK and generates a mode control signal ⁇ MRS in response to command signals. These command signals include a row address strobe signal ⁇ overscore (RAS) ⁇ , a column address strobe signal ⁇ overscore (CAS) ⁇ and a write enable signal ⁇ overscore (WE) ⁇ .
- the mode control signal ⁇ MRS is activated when the command signals are appropriately activated at the time the clock signal CLK transitions from 0 ⁇ 1.
- the control signal generator 703 generates the control signals MRS 1 -MRS 4 and the inverted control signals ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ in response to the mode control signal ⁇ MRS and buffered address signals ADD 1 -ADD 4 .
- the address buffer 705 buffers the external addresses A 1 -A 4 which are applied.
- the control signal generator 703 of FIG. 7 may include NAND gates 803 a - 803 d and inverters 803 c - 803 l, and reproduces each bit of the addresses ADD 1 -ADD 4 as the control signals MRS 1 -MRS 4 when the mode control signal ⁇ MRS is active.
- the mode control signal is inactive (i.e., at a logic 0 potential)
- the control signals MRS 1 -MRS 4 are set to logic 0 potentials and the inverted control signals ⁇ overscore (MRS 1 ) ⁇ - ⁇ overscore (MRS 4 ) ⁇ are set to logic 1 potentials which turn off the output driver circuit 405 .
Abstract
Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS1)}, {overscore (MRS2)}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.
Description
- 1. The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having output driver circuits therein.
- 2. Integrated circuit devices may contain specialized output driver circuits therein for driving external devices when the loads associated with the external devices are appreciable. Referring now to FIG. 1, an integrated circuit device may also be provided having a plurality of
memory modules memory devices - 3.FIG. 2 illustrates a conventional output driver circuit which comprises a PMOS pull-up transistor P1 and an NMOS pull-down transistor N1, connected as illustrated. As will be understood by those skilled in the art, application of logic 0 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P1 and NMOS pull-down transistor N1 will cause the output DOUT to be pulled to VCC. Similarly, application of
logic 1 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor P1 and NMOS pull-down transistor N1 will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of alogic 1 signal as DOKP to the gate of the PMOS pull-up transistor P1 and a logic 0 signal as DOKN to the gate of the NMOS pull-down transistor N1 will cause the output DOUT to float in a high impedance state. - 4.FIG. 3 illustrates another conventional output driver circuit which comprises an NMOS pull-up transistor N2 and an NMOS pull-down transistor N3, connected as illustrated. As will be understood by those skilled in the art, application of
logic 1 and logic 0 signals as DOKP and DOKN, respectively, will cause the output DOUT to be pulled to VCC. Similarly, application of logic 0 andlogic 1 signals as DOKP and DOKN, respectively, will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of logic 0 signals as DOKP and DOKN will cause the output DOUT to float in a high impedance state. - 5. Unfortunately, the driving capability of the circuits of FIG. 2 and 3, which is a function of the sizes of the pull-up and pull-down transistors, is fixed and typically cannot be varied in response to dynamic or static variations in loading. Thus, notwithstanding these conventional driver circuits, there continues to be a need for improved driver circuits which account for variations in loading.
- 6. It is therefore an object of the present invention to provide improved driver circuits and integrated circuit devices containing improved driver circuits therein.
- 7. It is another object of the present invention to provide driver circuits which can account for variations in loading.
- 8. These and other objects, features and advantages of the present invention are provided by output drivers which contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits according to an embodiment of the present invention include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS1)}, {overscore (MRS2)}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.
- 9. According to a preferred aspect of the present invention, the first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors. In particular, the first and second NMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first control input, respectively, and the first and second PMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively. Alternatively, the plurality of pull-up/pull-down driver circuits may each comprise four MOS transistors of the same type electrically connected in series between first and second supply signal lines (e.g., VCC and VSS).
- 10. According to another aspect of the present invention, a pull-up/pull-down driver circuit is provided which is always active to provide a baseline level of drive capability. In particular, a third pull-up/pull-down driver circuit may be provided which comprises only a single pair of MOS transistors and has first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively.
- 11. In addition, a controller is preferably provided which generates a first pair of complementary control signals on the first control signal line and the first complementary control signal line and generates a second pair of complementary control signals on the second control signal line and the second complementary control signal line, in response to command signals and an address. If the preferred driver circuit is used in an integrated circuit memory device, a memory array may also be provided which is electrically coupled to a pair of differential data lines and a data buffer may be provided which has first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit.
- 12.FIG. 1 is a block diagram of a system board containing a memory module array therein, according to the prior art.
- 13.FIG. 2 is an electrical schematic of an output driver circuit according to the prior art.
- 14.FIG. 3 is an electrical schematic of another output driver circuit according to the prior art.
- 15.FIG. 4 is a block diagram of a preferred memory device according to an embodiment of the present invention.
- 16.FIG. 5 is an electrical schematic of the programmable output driver of FIG. 4, according to a first embodiment of the present invention.
- 17.FIG. 6 is an electrical schematic of the programmable output driver of FIG. 4, according to a second embodiment of the present invention.
- 18.FIG. 7 is a block diagram of the controller of FIG. 4.
- 19.FIG. 8 is an electrical schematic of an embodiment of the control signal generator of FIG. 7.
- 20.FIG. 9 is a timing diagram which illustrates operation of the controller of FIG. 7.
- 21. The present invention will now be described in greater detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
- 22. Referring now to FIG. 4, a preferred memory device includes a memory
cell array block 401, adata output buffer 403, a programmable output driver 405 (which is coupled to an output pad DOUT) and anoutput driver controller 407. Thedata output buffer 403 receives differential output data from the memorycell array block 401 via complementary data buses DB and {overscore (DB)}, and generates first and second output signals DOKP and DOKN. Theprogrammable output driver 405 has a driving capability which can be varied in response to a plurality of control signals MRS1/{overscore (MRS1)}-MRS4/{overscore (MRS4)} and in response to the first and second output signals DOKP and DOKN. Theoutput driver controller 407 is also provided to generate the plurality of control signals MRS1/{overscore (MRS1)}-MRS4/{overscore (MRS4)}, in response to command signals (CMD) and address signals A1-A4. These command signals include a row address strobe signal {overscore (RAS)}, a column address strobe signal {overscore (CAS)} and a write enable signal {overscore (WE)}. - 23. In particular, the driving capability of the
preferred output driver 405 can be programmed when the command signals {overscore (RAS)}, {overscore (GAS)} and {overscore (WE)} are properly activated, the addresses A1-A4 are applied and the plurality of control signals MRS1/{overscore (MRS1)}-MRS4/{overscore (MRS4)} are generated. These control signals are generated at respective complementary levels based on the values of the addresses A1-A4, as described more fully hereinbelow with respect to FIGS. 7-8. - 24. Accordingly, when a system board includes a plurality of modules and each module includes a plurality of semiconductor memory devices, as illustrated by FIG. 1, the size of the output driver for each memory device can be selectively programmed to account for different loading conditions associated with each device and module. Thus, the skew between signals generated by memory devices within modules at different positions within a system board can be efficiently reduced.
- 25. The structure and operation of preferred programmable
output driver circuits 405 will now be described with reference to FIGS. 5-6. Referring specifically to FIG. 5, the programmableoutput driver circuit 405 according to a first embodiment includes fouroutput driving units output driving units output driving units PMOS switch transistors transistors transistors NMOS switch transistors - 26. Based on this configuration of driving units, the effective size of the
output driver 405 can be controlled by selectively turning on or off thePMOS switch transistors NMOS switch transistors PMOS switch transistors NMOS switch transistors output driving units units PMOS switch transistors NMOS switch transistors output driving units PMOS switch transistor 507 a and theNMOS switch transistor 507 d of theoutput driving unit 507 are turned on. Accordingly, only asingle driving unit 507 drives the output pad DOUT in response to the first and second output signals DOKP and DOKN. Finally, when the control signals MRS1-MRS4 are set to (0,0,0,0), no output drive capability is provided. - 27. To address this limitation of the driver of FIG. 5 when the control signals MRS1-MRS4 are set to (0,0,0,0), an additional driving unit can be added which is not responsive to the control signals. In particular, the programmable
output driver circuit 405 of FIG. 6 includes anadditional driving unit 609 which is responsive to the first and second output signals DOKP and DOKN and provides output drive capability even if the control signals MRS1-MRS4 are set to (0,0,0,0). - 28. Referring specifically to FIG. 6, the programmable
output driver circuit 405 according to a second embodiment includes fiveoutput driving units output driving units output driving units PMOS switch transistors transistors transistors NMOS switch transistors output driver 405 can be controlled by selective turning on or off thePMOS switch transistors NMOS switch transistors PMOS switch transistors NMOS switch transistors output driving units units PMOS switch transistors NMOS switch transistors output driving units PMOS switch transistor 607 a and theNMOS switch transistor 607 d of theoutput driving unit 607 are turned on. Accordingly, only drivingunits driver circuit 405 may also be provided. For example, NMOS transistors may be substituted for thePMOS transistors PMOS transistors - 29. Referring now to FIGS. 7 and 9, the
output driver controller 407 of FIG. 4 preferably includes a mode register setcontroller 701, acontrol signal generator 703 and anaddress buffer 705. The mode register setcontroller 701 receives a clock signal CLK and generates a mode control signal φMRS in response to command signals. These command signals include a row address strobe signal {overscore (RAS)}, a column address strobe signal {overscore (CAS)} and a write enable signal {overscore (WE)}. The mode control signal φMRS is activated when the command signals are appropriately activated at the time the clock signal CLK transitions from 0→1. Thecontrol signal generator 703 generates the control signals MRS1-MRS4 and the inverted control signals {overscore (MRS1)}-{overscore (MRS4)} in response to the mode control signal φMRS and buffered address signals ADD1-ADD4. As will be understood by those skilled in the art, theaddress buffer 705 buffers the external addresses A1-A4 which are applied. - 30. Referring to FIGS. 8 and 9, the
control signal generator 703 of FIG. 7 may include NAND gates 803 a-803 d andinverters 803 c-803 l, and reproduces each bit of the addresses ADD1-ADD4 as the control signals MRS1-MRS4 when the mode control signal φMRS is active. Whenever the mode control signal is inactive (i.e., at a logic 0 potential), the control signals MRS1-MRS4 are set to logic 0 potentials and the inverted control signals {overscore (MRS1)}-{overscore (MRS4)} are set tologic 1 potentials which turn off theoutput driver circuit 405. - 31. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (15)
1. A programmable output driver circuit, comprising:
first and second control signal lines;
a first pull-up/pull-down driver circuit, said first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to said first control signal line, a second control input and an output; and
a second pull-up/pull-down driver circuit, said second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to said second control signal line, a second control input and an output electrically coupled to the output of said first pull-up/pull-down driver circuit.
2. The driver circuit of , further comprising first and second complementary control signals lines; wherein the second control input of said first pull-up/pull-down driver circuit is electrically coupled to said first complementary control signal line; and wherein the second control input of said second pull-up/pull-down driver circuit is electrically coupled to said second complementary control signal line.
claim 1
3. The driver circuit of , wherein said first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors.
claim 2
4. The driver circuit of , wherein the first and second NMOS transistors of said first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first control input, respectively; and wherein the first and second PMOS transistors of said first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively.
claim 3
5. The driver circuit of , wherein said first pull-up/pull-down driver circuit comprises four MOS transistors of the same type electrically connected in series between first and second supply signal lines.
claim 1
6. The driver circuit of , further comprising a third pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively.
claim 4
7. The driver circuit of , wherein outputs of said first, second and third pull-up/pull-down driver circuits are electrically coupled together; and wherein said third pull-up/pull-down driver circuit comprises only a single pair of MOS transistors.
claim 6
8. The driver circuit of , further comprising means, responsive to a plurality of command signals and an address, for generating a first pair of complementary control signals on the first control signal line and first complementary control signal line and generating a second pair of complementary control signals on the second control signal line and second complementary control signal line; wherein outputs of said first, second and third pull-up/pull-down driver circuits are electrically coupled together; and wherein said third pull-up/pull-down driver circuit is not responsive to said generating means.
claim 7
9. The driver circuit of , wherein the command signals include a row address strobe signal, a column address strobe signal and a write enable signal.
claim 8
10. The driver circuit of , further comprising a memory array electrically coupled to a pair of differential data lines; and a data buffer having first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit.
claim 8
11. An integrated circuit memory device, comprising:
a memory cell array electrically coupled to a pair of differential data lines;
an output buffer having first and second inputs electrically coupled to the pair of differential data lines;
a plurality of pairs of differential control signal lines; and
a programmable output driver having first and second data inputs electrically coupled to at least one output of said output buffer and a plurality of pairs of differential control inputs electrically coupled to said plurality of pairs of differential control signal lines.
12. The memory device of , wherein said programmable output driver comprises first, second and third pull-up/pull-down driver circuits having outputs electrically coupled together.
claim 11
13. The memory device of , wherein each of the first, second and third pull-up/pull-down driver circuits has a pair of inputs electrically coupled to the first and second data inputs.
claim 12
14. The memory device of , wherein each of the first, second and third pull-up/pull-down driver circuits comprises a pair of PMOS transistors and a pair of NMOS transistors.
claim 13
15. The memory device of , wherein one of the NMOS transistors in the first pull-up/pull-down driver circuit has a gate electrode electrically coupled to one of a first pair of differential control signal lines; and wherein one of the PMOS transistors in the first pull-up/pull-down driver circuit has a gate electrode electrically coupled to another of the first pair of differential control signal lines.
claim 14
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/753,927 US6362656B2 (en) | 1997-06-27 | 2001-01-03 | Integrated circuit memory devices having programmable output driver circuits therein |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR97-28114 | 1997-06-27 | ||
KR19970028114 | 1997-06-27 | ||
KR97-77760 | 1997-12-30 | ||
KR1019970077760A KR100278651B1 (en) | 1997-06-27 | 1997-12-30 | Programmable output driver and semiconductor memory device including the same |
US09/105,394 US6208168B1 (en) | 1997-06-27 | 1998-06-26 | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
US09/753,927 US6362656B2 (en) | 1997-06-27 | 2001-01-03 | Integrated circuit memory devices having programmable output driver circuits therein |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,394 Continuation US6208168B1 (en) | 1997-06-27 | 1998-06-26 | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010000949A1 true US20010000949A1 (en) | 2001-05-10 |
US6362656B2 US6362656B2 (en) | 2002-03-26 |
Family
ID=26632879
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,394 Expired - Lifetime US6208168B1 (en) | 1997-06-27 | 1998-06-26 | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
US09/753,927 Expired - Lifetime US6362656B2 (en) | 1997-06-27 | 2001-01-03 | Integrated circuit memory devices having programmable output driver circuits therein |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,394 Expired - Lifetime US6208168B1 (en) | 1997-06-27 | 1998-06-26 | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
Country Status (3)
Country | Link |
---|---|
US (2) | US6208168B1 (en) |
JP (1) | JPH1125678A (en) |
TW (1) | TW393649B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6894529B1 (en) | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
US6967501B1 (en) | 2003-12-18 | 2005-11-22 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having enhanced predriver control |
US20070103186A1 (en) * | 2005-10-27 | 2007-05-10 | Clements Steven M | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection |
US20070170958A1 (en) * | 2004-02-11 | 2007-07-26 | Koninklijke Philips Electronics N.V. | High voltage driver circuit with fast slow voltage operation |
US7411419B1 (en) * | 2005-08-09 | 2008-08-12 | Lattice Semiconductor Corporation | Input/output systems and methods |
US20080297199A1 (en) * | 2007-06-04 | 2008-12-04 | Micron Technology, Inc. | Adjustable drive strength apparatus, systems, and methods |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6518792B2 (en) * | 2001-06-11 | 2003-02-11 | Sun Microsystems, Inc. | Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling |
JP2003087109A (en) * | 2001-09-13 | 2003-03-20 | Mitsubishi Electric Corp | Output buffer of semiconductor device |
US6580290B1 (en) | 2002-01-22 | 2003-06-17 | Agilent Technologies, Inc. | Open collector/drain and SSTL compliant output driver circuit and method for operating the circuit |
US7123046B2 (en) | 2002-02-13 | 2006-10-17 | Micron Technology, Inc | Apparatus for adaptively adjusting a data receiver |
JP2003337640A (en) | 2002-05-21 | 2003-11-28 | Mitsubishi Electric Corp | Bus control apparatus |
KR100505645B1 (en) * | 2002-10-17 | 2005-08-03 | 삼성전자주식회사 | Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information |
US7142461B2 (en) * | 2002-11-20 | 2006-11-28 | Micron Technology, Inc. | Active termination control though on module register |
JP3877673B2 (en) | 2002-11-28 | 2007-02-07 | 株式会社東芝 | Output buffer circuit and semiconductor memory using the same |
ITRM20030029A1 (en) * | 2003-01-27 | 2004-07-28 | Micron Technology Inc | "STRENGTH" ADJUSTMENT FOR ELECTRONIC CIRCUIT OUTPUT BUFFERS. |
KR100546214B1 (en) * | 2003-11-13 | 2006-01-24 | 주식회사 하이닉스반도체 | Data and Data Strobe Driver Strength Control Circuits for Semiconductor Devices |
KR100564586B1 (en) * | 2003-11-17 | 2006-03-29 | 삼성전자주식회사 | Data output driver for controlling slew rate of output signal according to bit organization |
TWI267857B (en) * | 2003-12-19 | 2006-12-01 | Hynix Semiconductor Inc | Apparatus for adjusting slew rate in semiconductor memory device and method therefor |
KR100605590B1 (en) * | 2004-05-10 | 2006-07-31 | 주식회사 하이닉스반도체 | Semiconductor memory device with ability to mediate impedance of data output-driver |
US7173450B2 (en) * | 2004-06-01 | 2007-02-06 | Hewlett-Packard Development Company, L.P. | Bus controller |
JP2005346908A (en) * | 2004-06-03 | 2005-12-15 | Samsung Electronics Co Ltd | Device and system associated with method for modifying operating characteristic of memory device using control bit received through data pin |
JP4825429B2 (en) * | 2005-02-17 | 2011-11-30 | 富士通セミコンダクター株式会社 | Semiconductor device |
US7233165B2 (en) * | 2005-03-31 | 2007-06-19 | Seiko Epson Corporation | High speed driver for serial communications |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7386656B2 (en) * | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
WO2007002324A2 (en) * | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8041881B2 (en) * | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US7571406B2 (en) * | 2005-08-04 | 2009-08-04 | Freescale Semiconductor, Inc. | Clock tree adjustable buffer |
GB2444663B (en) | 2005-09-02 | 2011-12-07 | Metaram Inc | Methods and apparatus of stacking drams |
JP4930875B2 (en) * | 2005-09-29 | 2012-05-16 | 株式会社ハイニックスセミコンダクター | On-die termination control device |
JP2007095262A (en) * | 2005-09-29 | 2007-04-12 | Hynix Semiconductor Inc | Semiconductor memory and its drive method |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
JP4901286B2 (en) * | 2006-04-24 | 2012-03-21 | 株式会社東芝 | Semiconductor device and memory circuit system |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US7902875B2 (en) * | 2006-11-03 | 2011-03-08 | Micron Technology, Inc. | Output slew rate control |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
KR101003153B1 (en) * | 2009-05-15 | 2010-12-21 | 주식회사 하이닉스반도체 | Voltage Stabilization Circuit and a Semiconductor Memory Apparatus using the same |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
JP2011124683A (en) * | 2009-12-09 | 2011-06-23 | Toshiba Corp | Output buffer circuit, input buffer circuit, and input/output buffer circuit |
KR101053543B1 (en) * | 2010-04-30 | 2011-08-03 | 주식회사 하이닉스반도체 | Clock duty correction circuit |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
US8587340B2 (en) * | 2012-03-27 | 2013-11-19 | Micron Technology, Inc. | Apparatuses including scalable drivers and methods |
USRE49506E1 (en) * | 2012-12-03 | 2023-04-25 | Samsung Electronics Co., Ltd. | High/low speed mode selection for output driver circuits of a memory interface |
US9130557B2 (en) * | 2012-12-03 | 2015-09-08 | Samsung Electronics Co., Ltd. | Operating method of input/output interface |
KR102012901B1 (en) * | 2012-12-03 | 2019-08-21 | 삼성전자주식회사 | Operating method of input/output(i/o) interface |
JP6297575B2 (en) * | 2013-08-19 | 2018-03-20 | 国立研究開発法人科学技術振興機構 | Reconfigurable delay circuit, delay monitor circuit using the delay circuit, variation correction circuit, variation measurement method, and variation correction method |
US10419252B2 (en) * | 2015-06-22 | 2019-09-17 | Qualcomm Incorporated | Low power physical layer driver topologies |
JP2017216611A (en) | 2016-06-01 | 2017-12-07 | マイクロン テクノロジー, インク. | Semiconductor device |
KR102349415B1 (en) * | 2017-08-07 | 2022-01-11 | 삼성전자주식회사 | Pulse amplitude modulation transmitter and pulse amplitude modulation receiver |
KR20210144074A (en) | 2020-05-21 | 2021-11-30 | 에스케이하이닉스 주식회사 | Transmitter circuit |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0253914A1 (en) | 1986-07-23 | 1988-01-27 | Deutsche ITT Industries GmbH | Insulated-gate field-effect transistor push-pull driver stage with compensation for fluctuations of working parameters and variations in manufacturing process |
KR910004735B1 (en) | 1988-07-18 | 1991-07-10 | 삼성전자 주식회사 | Butter circuit for data output |
US5134311A (en) * | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
US5153450A (en) | 1991-07-16 | 1992-10-06 | Samsung Semiconductor, Inc. | Programmable output drive circuit |
US5397942A (en) * | 1991-08-23 | 1995-03-14 | Nec Corporation | Driver circuit for a plurality of outputs |
JPH0591522A (en) | 1991-09-30 | 1993-04-09 | Toshiba Corp | Digital oscillator and chrominance subcarrier reproducing circuit using same |
US5220216A (en) * | 1992-01-02 | 1993-06-15 | Woo Ann K | Programmable driving power of a CMOS gate |
US5227679A (en) * | 1992-01-02 | 1993-07-13 | Advanced Micro Devices, Inc. | Cmos digital-controlled delay gate |
US5361003A (en) | 1993-01-14 | 1994-11-01 | Micron Semiconductor, Inc. | Adjustable buffer driver |
US5477166A (en) | 1993-04-22 | 1995-12-19 | Benchmarq Microelectronics | Programmable output device with integrated circuit |
JPH07335834A (en) | 1994-06-07 | 1995-12-22 | Nippon Motorola Ltd | Output driver of semiconductor integrated circuit device |
KR100368120B1 (en) | 1995-08-24 | 2003-03-31 | 삼성전자 주식회사 | data output driver in semiconductor memory device |
US5719491A (en) | 1995-12-19 | 1998-02-17 | Cherry Semiconductor Corporation | Output driver for high-speed device |
US5677555A (en) | 1995-12-22 | 1997-10-14 | Cypress Semiconductor Corp. | Output driver transistor with multiple gate bodies |
US5666078A (en) | 1996-02-07 | 1997-09-09 | International Business Machines Corporation | Programmable impedance output driver |
US5742832A (en) * | 1996-02-09 | 1998-04-21 | Advanced Micro Devices | Computer system with programmable driver output's strengths responsive to control signal matching preassigned address range |
US5732027A (en) | 1996-12-30 | 1998-03-24 | Cypress Semiconductor Corporation | Memory having selectable output strength |
US5900744A (en) * | 1996-12-30 | 1999-05-04 | Intel Corporation | Method and apparatus for providing a high speed tristate buffer |
-
1998
- 1998-06-09 JP JP16095798A patent/JPH1125678A/en active Pending
- 1998-06-10 TW TW087109205A patent/TW393649B/en not_active IP Right Cessation
- 1998-06-26 US US09/105,394 patent/US6208168B1/en not_active Expired - Lifetime
-
2001
- 2001-01-03 US US09/753,927 patent/US6362656B2/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6894529B1 (en) | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
US7123055B1 (en) | 2003-07-09 | 2006-10-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having coarse and fine tuning control |
US6967501B1 (en) | 2003-12-18 | 2005-11-22 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having enhanced predriver control |
US7053661B1 (en) | 2003-12-18 | 2006-05-30 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having enhanced predriver control |
US20070170958A1 (en) * | 2004-02-11 | 2007-07-26 | Koninklijke Philips Electronics N.V. | High voltage driver circuit with fast slow voltage operation |
US7746125B2 (en) * | 2004-02-11 | 2010-06-29 | Nxp B.V. | High voltage driver circuit with fast slow voltage operation |
US7411419B1 (en) * | 2005-08-09 | 2008-08-12 | Lattice Semiconductor Corporation | Input/output systems and methods |
US20070103186A1 (en) * | 2005-10-27 | 2007-05-10 | Clements Steven M | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection |
US7307447B2 (en) | 2005-10-27 | 2007-12-11 | International Business Machines Corporation | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection |
US20080297199A1 (en) * | 2007-06-04 | 2008-12-04 | Micron Technology, Inc. | Adjustable drive strength apparatus, systems, and methods |
US7558130B2 (en) * | 2007-06-04 | 2009-07-07 | Micron Technology, Inc. | Adjustable drive strength apparatus, systems, and methods |
Also Published As
Publication number | Publication date |
---|---|
US6208168B1 (en) | 2001-03-27 |
US6362656B2 (en) | 2002-03-26 |
JPH1125678A (en) | 1999-01-29 |
TW393649B (en) | 2000-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6362656B2 (en) | Integrated circuit memory devices having programmable output driver circuits therein | |
US6058063A (en) | Integrated circuit memory devices having reduced power consumption requirements during standby mode operation | |
US6282128B1 (en) | Integrated circuit memory devices having multiple data rate mode capability and methods of operating same | |
GB2325322A (en) | A high speed and low power signal line driver and semiconductor memory device using the same | |
US6445226B2 (en) | Output circuit converting an internal power supply potential into an external supply potential in a semiconductor apparatus | |
US4905201A (en) | Semiconductor memory device capable of selective operation of memory cell blocks | |
CN1140904C (en) | Synchronous semiconductor memory device with clock generating circuit | |
US8750014B2 (en) | Tri-state driver circuits having automatic high-impedance enabling | |
US5812492A (en) | Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal | |
US6870776B2 (en) | Data output circuit in combined SDR/DDR semiconductor memory device | |
US5682110A (en) | Low capacitance bus driver | |
US6378008B1 (en) | Output data path scheme in a memory device | |
KR19990014168A (en) | A semiconductor memory device having a burn-in test function | |
US5373470A (en) | Method and circuit for configuring I/O devices | |
US5040151A (en) | Memory circuit with improved power interconnections | |
US5598371A (en) | Data input/output sensing circuit of semiconductor memory device | |
JPH05325557A (en) | Semiconductor memory | |
US7139847B2 (en) | Semiconductor memory device having externally controllable data input and output mode | |
US20040120178A1 (en) | Test mode circuit of semiconductor memory device | |
US6597201B1 (en) | Dynamic predecoder circuitry for memory circuits | |
KR100745053B1 (en) | Circuit for Driving Output | |
JP2631925B2 (en) | MOS type RAM | |
KR100331548B1 (en) | Semiconductor memory device capable of preventing mis-operation due to load of column address line | |
US7286424B2 (en) | Semiconductor integrated circuit device | |
JPH08102192A (en) | Semiconductor memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |