US20030061436A1 - Transportation of main memory and intermediate memory contents - Google Patents
Transportation of main memory and intermediate memory contents Download PDFInfo
- Publication number
- US20030061436A1 US20030061436A1 US09/963,185 US96318501A US2003061436A1 US 20030061436 A1 US20030061436 A1 US 20030061436A1 US 96318501 A US96318501 A US 96318501A US 2003061436 A1 US2003061436 A1 US 2003061436A1
- Authority
- US
- United States
- Prior art keywords
- memory
- reserved area
- designator
- host system
- nonvolatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Definitions
- This disclosure relates to intermediate memory systems, more particularly to those using nonvolatile memory.
- Intermediate memory has several useful applications. For example, a personal computer uses a cache memory to store frequently accessed data in a faster memory than that used for the main memory. Similarly, placing frequently used data in a smaller memory saves time in seeking and reading the data from a larger memory.
- intermediate memory Other types are used as well.
- portable electronic devices that communicate with a computer or workstation may use the hard disk of the computer as its main memory. They use the local memory in the device as an intermediate storage.
- each workstation connected to the central server or repository may have a local storage to avoid having to transport the same data across the network unnecessarily.
- the local store is a volatile memory that does not retain its data upon loss of power.
- nonvolatile memory allowing retention of the data in the intermediate storage.
- no know systems make any effort to create or store images of the intermediate storage. However, this ability would provide several advantages for manufacturers of electronic devices, among others.
- FIG. 1 shows one embodiment of an electronic device having a nonvolatile intermediate memory module, in accordance with the invention.
- FIG. 2 shows an alternative embodiment of a nonvolatile intermediate memory module, in accordance with the invention.
- FIG. 3 shows one embodiment of a method to create an image of an intermediate memory, in accordance with the invention.
- FIG. 4 shows one embodiment of a method to populate an intermediate memory, in accordance with the invention.
- Intermediate memory is used in computers, distributed computing environments, a wide range of consumer electronic devices, among many others.
- Intermediate storage or memory terms that will be used interchangeably here, is used in computers, distributed computing environments, a wide range of consumer electronic devices, among many others.
- an initial example of a computer using a cache memory as the intermediate memory will be used. This is not intended to limit application of the invention or the scope of the claims in any way.
- a host system 10 has a central processing unit 16 , a main memory 14 , and an intermediate memory module 12 .
- Intermediate memory module 12 may have a dedicated memory controller 20 .
- the central processing unit or other processor in the system may act as the memory controller.
- the memory module also includes a nonvolatile (NV) memory array 18 .
- the memory module may be a separate device from the CPU, as shown here, or it may reside coincident with the CPU. Similarly, the nonvolatile memory array may reside coincident with the memory controller, or as reside separately from the memory controller.
- the connector 26 may be a back plane connector.
- the connector 26 may comprises a trace line on a printed circuit board.
- FIG. 2 An alternative embodiment is shown in FIG. 2, wherein the memory module 12 is contained in an external chassis to the host system 10 .
- the connector 26 allows connection between the host system 10 and the memory module 12 .
- the memory controller may be a dedicated controller in the chassis, or the central processing unit or other system processor may assume the function of a memory controller when the memory module 12 is connected.
- the nonvolatile memory array 18 that is part of memory module 12 may be any type of persistent memory, one that retains its contents even after loss of power.
- a particularly well-suited memory technology for the context of this invention is polymer ferroelectric memory arrays.
- this type of memory comprises a layer of polymer material having ferroelectric properties sandwiched between layers of metal.
- the layers of metal are patterned to define word lines and bit lines as are commonly used in addressing memory cells.
- the region of polymer between the word line and bit line cross over points become the memory cells.
- Manipulation of the voltages on the word lines and bit lines can causes changes in the polarization state of the ferroelectric polymer, with one state being defined as a data ‘1’ and the opposite polarization state being defined as a data ‘0.’
- the polymer ferroelectric memories generally do not require separate circuits of transistors for each cell. Therefore, they are simpler to manufacture, as well as denser in population. This provides a large capacity, nonvolatile memory array that is not very expensive. Other types of nonvolatile memory are also within the scope of the invention, including volatile memory with a battery backup, as the battery will prevent the memory from losing its contents when the main power is turned off. Such a large, nonvolatile memory array provides opportunities in management of memory in various types of system that were not previously available.
- the effectiveness of cache memory in the computer example lies in its ability to allow the CPU to avoid having to access the main memory.
- the main memory is larger and requires more seeking prior to locating the data for which the CPU is looking.
- Many main memory technologies are also slower than those memories used for cache memory. This increases the amount of time needed to satisfy each request, slowing the overall processing speed of the system and reducing the efficiency.
- the memory controller of FIG. 1 may create an image of the nonvolatile intermediate memory or cause the nonvolatile intermediate memory to be populated. For example, once a manufacturer has obtained a populated cache memory in a demonstration or test machine, the system may make a copy of the cache onto the main storage. This copy may be used for many purposes.
- an activation signal will be received.
- the activation signal indicates that a copy of the nonvolatile intermediate memory contents should be made.
- the activation signal will be some sort of shut down signal, or a signal indicating that no further changes to the memory are to be made. This avoids any changes being made to the intermediate memory contents during the copying of those contents.
- a reserved area of the main memory is designated at 32 .
- An example of a reserved area is shown at 22 of FIG. 1.
- the contents of the reserved area will not be moved to intermediate storage. In the personal computer example, the reserved area will not be ‘cached.’ Again, this prevents changes being made to both the intermediate memory and the main memory.
- the reserved area may be designated at manufacture of the machine, during system initialization, periodically throughout system operation or each time the imaging process is initiated. For those instances where the reserved area is already designated, determining the reserved area will comprise accessing that area in preparation for transfer of data.
- the contents of the intermediate memory are copied to the reserved area.
- the designator discussed above is set at 36 .
- the state of the designator is changed to indicate that the host system should access the intermediate storage contents from the main memory initially, instead of accessing the intermediate storage directly. This process will be discussed in more detail with reference to FIG. 4.
- the designator may comprise many different types of indicators. In the example of FIG. 1, the designator is at least one bit stored in the reserved area of the main storage at 24 .
- the designator may be stored just about anywhere. However, in the computer manufacturing example above, if the main memory is removed from the current host system and installed in another host system to populate the other host system's cache, the designator would have to be resident on the other host. Otherwise, the new host would not detect the designator and would not access the copy of the intermediate memory residing on the main memory at system initialization. Removal of the main memory from the host is an option shown at 38 .
- FIG. 4 An embodiment of this is shown in FIG. 4.
- this replication or restoration process will be referred to as an installation.
- the copy of the intermediate memory is being installed in either the same intermediate memory, or another intermediate memory. Typically, this process will occur at initialization of the host system.
- the initialization of the host system occurs at 50 .
- the host system detects whether or not the designator, discussed above, indicates that an installation should occur at 52 . If the designator is not selected, the system operates ‘normally’ at 54 . If it does indicate an installation should occur, the host system accesses a reserved area in the host system main memory at 56 . The contents of the reserved area are then copied to the intermediate memory at 58 . As mentioned above, if desired, some of the contents of the reserved area may pertain to other areas of the main memory. If so, those contents are copied back to the other areas at 60 . Finally, the install designator is reset or cleared at 62 . This is usually accomplished by setting the predetermined number of bits to a different state, where the different state indicates that the installation from main memory to intermediate memory does not need to occur.
- these processes will be implemented by software in the host system.
- a driver resident on the new host system may be the entity that determines the state of the designator or flag that indicates whether an install should occur.
- a driver resident on the host system may also initiate the imaging process that results in the contents of the intermediate storage being copied to the main storage upon activation.
- the methods of the invention are implemented in software, that software will typically comprise machine-readable code that implement the methods of the invention when that code is executed.
- the code may be contained in some type of article, such as a diskette or compact disc. Similarly, it may be contained in a downloadable file.
Abstract
A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.
Description
- 1. Field
- This disclosure relates to intermediate memory systems, more particularly to those using nonvolatile memory.
- 2. Background
- Intermediate memory has several useful applications. For example, a personal computer uses a cache memory to store frequently accessed data in a faster memory than that used for the main memory. Similarly, placing frequently used data in a smaller memory saves time in seeking and reading the data from a larger memory.
- Other types of intermediate memory are used as well. For example, portable electronic devices that communicate with a computer or workstation may use the hard disk of the computer as its main memory. They use the local memory in the device as an intermediate storage. Similarly, in a distributed computing environment, each workstation connected to the central server or repository may have a local storage to avoid having to transport the same data across the network unnecessarily.
- In many applications, the local store is a volatile memory that does not retain its data upon loss of power. However, it is possible to use nonvolatile memory, allowing retention of the data in the intermediate storage. Currently, no know systems make any effort to create or store images of the intermediate storage. However, this ability would provide several advantages for manufacturers of electronic devices, among others.
- The invention may be best understood by reading the disclosure with reference to the drawings, wherein:
- FIG. 1 shows one embodiment of an electronic device having a nonvolatile intermediate memory module, in accordance with the invention.
- FIG. 2 shows an alternative embodiment of a nonvolatile intermediate memory module, in accordance with the invention.
- FIG. 3 shows one embodiment of a method to create an image of an intermediate memory, in accordance with the invention.
- FIG. 4 shows one embodiment of a method to populate an intermediate memory, in accordance with the invention.
- Several examples of use of intermediate memory exist. Intermediate storage or memory, terms that will be used interchangeably here, is used in computers, distributed computing environments, a wide range of consumer electronic devices, among many others. For ease of discussion and to promote understanding of the invention, however, an initial example of a computer using a cache memory as the intermediate memory will be used. This is not intended to limit application of the invention or the scope of the claims in any way.
- Turning now to FIG. 1, it can be seen that a
host system 10 has acentral processing unit 16, amain memory 14, and anintermediate memory module 12.Intermediate memory module 12 may have adedicated memory controller 20. Alternatively, the central processing unit or other processor in the system may act as the memory controller. The memory module also includes a nonvolatile (NV)memory array 18. The memory module may be a separate device from the CPU, as shown here, or it may reside coincident with the CPU. Similarly, the nonvolatile memory array may reside coincident with the memory controller, or as reside separately from the memory controller. - For a memory array or controller that resides separately, the
connector 26 may be a back plane connector. For those residing coincident with the CPU, theconnector 26 may comprises a trace line on a printed circuit board. An alternative embodiment is shown in FIG. 2, wherein thememory module 12 is contained in an external chassis to thehost system 10. Theconnector 26 allows connection between thehost system 10 and thememory module 12. Again, the memory controller may be a dedicated controller in the chassis, or the central processing unit or other system processor may assume the function of a memory controller when thememory module 12 is connected. - The
nonvolatile memory array 18 that is part ofmemory module 12 may be any type of persistent memory, one that retains its contents even after loss of power. A particularly well-suited memory technology for the context of this invention is polymer ferroelectric memory arrays. Generally, this type of memory comprises a layer of polymer material having ferroelectric properties sandwiched between layers of metal. The layers of metal are patterned to define word lines and bit lines as are commonly used in addressing memory cells. The region of polymer between the word line and bit line cross over points become the memory cells. Manipulation of the voltages on the word lines and bit lines can causes changes in the polarization state of the ferroelectric polymer, with one state being defined as a data ‘1’ and the opposite polarization state being defined as a data ‘0.’ - The polymer ferroelectric memories generally do not require separate circuits of transistors for each cell. Therefore, they are simpler to manufacture, as well as denser in population. This provides a large capacity, nonvolatile memory array that is not very expensive. Other types of nonvolatile memory are also within the scope of the invention, including volatile memory with a battery backup, as the battery will prevent the memory from losing its contents when the main power is turned off. Such a large, nonvolatile memory array provides opportunities in management of memory in various types of system that were not previously available.
- This can be seen using the example of a computer using cache memory as an intermediate storage. When most computers are manufactured, the manufacture images a ‘gold’ image of the main memory, typically a disk drive. However, no current techniques or apparatuses exist that allow a ‘gold’ image of a cache memory to be made. Generally, a cache memory only reaches true effectiveness after the system has been used for an extensive period of time.
- The effectiveness of cache memory in the computer example lies in its ability to allow the CPU to avoid having to access the main memory. The main memory is larger and requires more seeking prior to locating the data for which the CPU is looking. Many main memory technologies are also slower than those memories used for cache memory. This increases the amount of time needed to satisfy each request, slowing the overall processing speed of the system and reducing the efficiency. Many different techniques exist in which the cache memory is populated with frequently used data, and analyses are run to bring data with a high probability of access to the cache memory.
- In one application of the invention, the memory controller of FIG. 1 may create an image of the nonvolatile intermediate memory or cause the nonvolatile intermediate memory to be populated. For example, once a manufacturer has obtained a populated cache memory in a demonstration or test machine, the system may make a copy of the cache onto the main storage. This copy may be used for many purposes.
- Among those may be methods to copy the cache image onto unpopulated cache memories of other systems being manufactured. This provides the new systems with a populated cache memory, increasing the effectiveness of the new system right off the factory floor. Other applications may be in restoration of a system to a known cache state, such as for those systems used in testing and debugging of programs. With the ‘gold’ cache image contained within the ‘gold’ main memory image, the ability to replicate the cache contents on the manufacturing floor becomes relatively simple. For example, a driver could be included as part of the operating system that checks the main memory to determine if a copy of the cache resides within. As will be discussed later with reference to FIGS. 3 and 4, a designator may be used that will serve to notify the memory controller as to the location from which the cache contents should first be accessed.
- Referring now to FIG. 3, one embodiment of a method to create an image of an intermediate memory will be discussed. At30, an activation signal will be received. The activation signal indicates that a copy of the nonvolatile intermediate memory contents should be made. Generally, the activation signal will be some sort of shut down signal, or a signal indicating that no further changes to the memory are to be made. This avoids any changes being made to the intermediate memory contents during the copying of those contents.
- A reserved area of the main memory is designated at32. An example of a reserved area is shown at 22 of FIG. 1. The contents of the reserved area will not be moved to intermediate storage. In the personal computer example, the reserved area will not be ‘cached.’ Again, this prevents changes being made to both the intermediate memory and the main memory. The reserved area may be designated at manufacture of the machine, during system initialization, periodically throughout system operation or each time the imaging process is initiated. For those instances where the reserved area is already designated, determining the reserved area will comprise accessing that area in preparation for transfer of data.
- Returning to FIG. 3 at34, the contents of the intermediate memory are copied to the reserved area. In an alternative embodiment, it may be desirable to copy other parts of the main memory to the reserved area as shown at 40. This may occur in any situation in which it is desirable to recreate a portion of the main memory to a known state. This is an optional step.
- The designator discussed above is set at36. The state of the designator is changed to indicate that the host system should access the intermediate storage contents from the main memory initially, instead of accessing the intermediate storage directly. This process will be discussed in more detail with reference to FIG. 4. The designator may comprise many different types of indicators. In the example of FIG. 1, the designator is at least one bit stored in the reserved area of the main storage at 24.
- The designator may be stored just about anywhere. However, in the computer manufacturing example above, if the main memory is removed from the current host system and installed in another host system to populate the other host system's cache, the designator would have to be resident on the other host. Otherwise, the new host would not detect the designator and would not access the copy of the intermediate memory residing on the main memory at system initialization. Removal of the main memory from the host is an option shown at38.
- Once a copy of a populated intermediate storage exists, it is possible to replicate it or use it to restore systems. An embodiment of this is shown in FIG. 4. For purposes of discussion here, this replication or restoration process will be referred to as an installation. The copy of the intermediate memory is being installed in either the same intermediate memory, or another intermediate memory. Typically, this process will occur at initialization of the host system.
- In FIG. 4, the initialization of the host system occurs at50. The host system detects whether or not the designator, discussed above, indicates that an installation should occur at 52. If the designator is not selected, the system operates ‘normally’ at 54. If it does indicate an installation should occur, the host system accesses a reserved area in the host system main memory at 56. The contents of the reserved area are then copied to the intermediate memory at 58. As mentioned above, if desired, some of the contents of the reserved area may pertain to other areas of the main memory. If so, those contents are copied back to the other areas at 60. Finally, the install designator is reset or cleared at 62. This is usually accomplished by setting the predetermined number of bits to a different state, where the different state indicates that the installation from main memory to intermediate memory does not need to occur.
- Typically, these processes will be implemented by software in the host system. For example, a driver resident on the new host system may be the entity that determines the state of the designator or flag that indicates whether an install should occur. Similarly, a driver resident on the host system may also initiate the imaging process that results in the contents of the intermediate storage being copied to the main storage upon activation.
- If the methods of the invention are implemented in software, that software will typically comprise machine-readable code that implement the methods of the invention when that code is executed. The code may be contained in some type of article, such as a diskette or compact disc. Similarly, it may be contained in a downloadable file.
- In this manner, systems using intermediate memory will have the capacity to have a ‘pre-warmed’ intermediate memory upon system initialization. This avoids the delays that typically occur while the intermediate storage is populated enough to increase system efficiency.
- Thus, although there has been described to this point a particular embodiment for a method and apparatus for transporting of main and intermediate memory contents, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.
Claims (24)
1. A nonvolatile memory module, comprising:
a) a nonvolatile memory array;
b) a connector operable to connect the nonvolatile memory array to a host system; and
c) a memory controller operable to:
i) create an image of a nonvolatile intermediate memory in response to an imaging request; and
ii) populate a nonvolatile intermediate memory in response to an installation request.
2. The nonvolatile memory module of claim 1 , wherein the nonvolatile memory array further comprises a polymer ferroelectric memory array.
3. The nonvolatile memory module of claim 1 , wherein the memory controller further comprises a dedicated memory controller.
4. The nonvolatile memory module of claim 1 , wherein the memory controller further comprises a central processing unit on the host system acting as a memory controller.
5. The nonvolatile memory module of claim 1 , wherein the memory controller is further operable to change the state of a designator based upon the completion of one of either the imaging request or the installation request.
6. The nonvolatile memory module of claim 1 , wherein the nonvolatile memory array resides coincident with the memory controller.
7. The nonvolatile memory module of claim 1 , wherein the nonvolatile memory array resides separately from the memory controller.
8. A method of creating an image of an intermediate memory, the method comprising:
a) receiving an activation signal from a host system;
b) determining a reserved area on a main memory device in the host system;
c) copying contents of an intermediate memory to the reserved area; and
d) changing the state of a designator to a state that indicates a copy of the intermediate memory exists in the reserved area.
9. The method of claim 8 , wherein the method further comprises making copies of at least one other area of the main memory to the reserved area.
10. The method of claim 8 , wherein the method further comprises removing the main memory from the host system.
11. The method of claim 10 , wherein the method further comprises transporting the main memory to a new host system.
12. The method of claim 8 , wherein determining a reserved area further comprises accessing a predetermined area.
13. The method of claim 8 , wherein determining a reserved area further comprises performing an analysis of possible areas and selecting one of the possible areas as the reserved area.
14. The method of claim 8 , wherein changing the state of a designator further comprises setting a predetermined number of bits to a predetermined state.
15. The method of claim 14 , wherein the predetermined number of bits reside in the reserved area.
16. An article containing machine-readable code that, when executed, causes a machine to:
a) receive an activation signal from a host system;
b) determine a reserved area on a main memory device in the host system;
c) copy contents of an intermediate memory to the reserved area; and
d) change the state of a designator to a state that indicates a copy of the intermediate memory exists in the reserved area.
17. The method of claim 8 , wherein the article contains further code that, when executed, causes the machine to make copies of at least one other area of the main memory to the reserved area.
18. The article of claim 16 wherein the article is selected from the group comprised of: a diskette, a downloadable file, and a compact disc.
19. A method of installing contents of an intermediate memory, the method comprising:
a) determining if a designator has been set to a predetermined state;
b) if the designator has been set to the predetermined state:
i) accessing a reserved area of a main memory on a host system;
ii) copying contents of the reserved area to an intermediate memory; and
iii) setting the designator to a different predetermined state.
20. The method of claim 19 , wherein the method further comprises copying contents of the reserved area to at least one other area of the main memory.
21. The method of claim 19 , wherein setting the designator farther comprises setting the value of at least one bit to a predetermined state.
22. The method of claim 21 , wherein the bit resides in the reserved area.
23. An article containing machine-readable code that, when executed, causes a machine to:
a) determine if a designator has been set to a predetermined state;
b) if the designator has been set to the predetermined state:
i) accessing a reserved area of a main memory in a host system;
ii) copy contents of the reserved area to an intermediate memory; and
iii) set the designator to a different predetermined state.
24. The method of claim 23 , wherein the article contains further code that, when executed, causes the machine to copy contents of a reserved area to at least one other area of the main memory.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/963,185 US20030061436A1 (en) | 2001-09-25 | 2001-09-25 | Transportation of main memory and intermediate memory contents |
US10/861,718 US7085878B2 (en) | 2001-09-25 | 2004-06-04 | Transportation of main memory and intermediate memory contents |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/963,185 US20030061436A1 (en) | 2001-09-25 | 2001-09-25 | Transportation of main memory and intermediate memory contents |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/861,718 Continuation US7085878B2 (en) | 2001-09-25 | 2004-06-04 | Transportation of main memory and intermediate memory contents |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030061436A1 true US20030061436A1 (en) | 2003-03-27 |
Family
ID=25506869
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/963,185 Abandoned US20030061436A1 (en) | 2001-09-25 | 2001-09-25 | Transportation of main memory and intermediate memory contents |
US10/861,718 Expired - Fee Related US7085878B2 (en) | 2001-09-25 | 2004-06-04 | Transportation of main memory and intermediate memory contents |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/861,718 Expired - Fee Related US7085878B2 (en) | 2001-09-25 | 2004-06-04 | Transportation of main memory and intermediate memory contents |
Country Status (1)
Country | Link |
---|---|
US (2) | US20030061436A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030005223A1 (en) * | 2001-06-27 | 2003-01-02 | Coulson Richard L. | System boot time reduction method |
US20030046493A1 (en) * | 2001-08-31 | 2003-03-06 | Coulson Richard L. | Hardware updated metadata for non-volatile mass storage cache |
US20030074524A1 (en) * | 2001-10-16 | 2003-04-17 | Intel Corporation | Mass storage caching processes for power reduction |
US20050204090A1 (en) * | 2004-03-10 | 2005-09-15 | Eilert Sean S. | Hardware stack for blocked nonvolatile memories |
WO2005093588A2 (en) * | 2004-02-27 | 2005-10-06 | Intel Corporation | Interface for a block addressable mass storage system |
US7103724B2 (en) | 2002-04-01 | 2006-09-05 | Intel Corporation | Method and apparatus to generate cache data |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386552A (en) * | 1991-10-21 | 1995-01-31 | Intel Corporation | Preservation of a computer system processing state in a mass storage device |
US6101576A (en) * | 1992-07-31 | 2000-08-08 | Fujitsu Limited | Method for saving generated character image in a cache system including a backup cache |
US6470424B1 (en) * | 1997-02-13 | 2002-10-22 | Novell, Inc. | Pin management of accelerator for interpretive environments |
US6493806B1 (en) * | 2000-03-14 | 2002-12-10 | Intel Corporation | Method and apparatus for generating a transportable physical level data block trace |
US20030005223A1 (en) * | 2001-06-27 | 2003-01-02 | Coulson Richard L. | System boot time reduction method |
US20030046493A1 (en) * | 2001-08-31 | 2003-03-06 | Coulson Richard L. | Hardware updated metadata for non-volatile mass storage cache |
US6539456B2 (en) * | 1999-10-13 | 2003-03-25 | Intel Corporation | Hardware acceleration of boot-up utilizing a non-volatile disk cache |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5175842A (en) * | 1988-05-31 | 1992-12-29 | Kabushiki Kaisha Toshiba | Data storage control system capable of reading data immediately after powered on |
US5193162A (en) * | 1989-11-06 | 1993-03-09 | Unisys Corporation | Cache memory with data compaction for use in the audit trail of a data processing system having record locking capabilities |
DE69231667D1 (en) * | 1991-04-22 | 2001-03-08 | Canon Kk | Printer control program transmission method and printer suitable for receiving a control program |
JP2882192B2 (en) * | 1992-07-28 | 1999-04-12 | ブラザー工業株式会社 | Printing device |
US5778167A (en) * | 1994-06-14 | 1998-07-07 | Emc Corporation | System and method for reassigning a storage location for reconstructed data on a persistent medium storage system |
US5586291A (en) * | 1994-12-23 | 1996-12-17 | Emc Corporation | Disk controller with volatile and non-volatile cache memories |
JP4272714B2 (en) * | 1996-07-19 | 2009-06-03 | キヤノン株式会社 | Image recording apparatus and image recording method |
US6012983A (en) | 1996-12-30 | 2000-01-11 | Walker Asset Management Limited Partnership | Automated play gaming device |
NO972803D0 (en) | 1997-06-17 | 1997-06-17 | Opticom As | Electrically addressable logic device, method of electrically addressing the same and use of device and method |
US6854000B2 (en) * | 1997-12-27 | 2005-02-08 | Canon Kabushiki Kaisha | Image forming apparatus and control method for the same |
US6295577B1 (en) * | 1998-02-24 | 2001-09-25 | Seagate Technology Llc | Disc storage system having a non-volatile cache to store write data in the event of a power failure |
DE69930697T2 (en) * | 1998-07-29 | 2006-10-05 | Seiko Epson Corp. | Initialization of a computer printer |
US6369840B1 (en) * | 1999-03-10 | 2002-04-09 | America Online, Inc. | Multi-layered online calendaring and purchasing |
US6618751B1 (en) * | 1999-08-20 | 2003-09-09 | International Business Machines Corporation | Systems and methods for publishing data with expiration times |
US6918113B2 (en) * | 2000-11-06 | 2005-07-12 | Endeavors Technology, Inc. | Client installation and execution system for streamed applications |
US6564286B2 (en) * | 2001-03-07 | 2003-05-13 | Sony Corporation | Non-volatile memory system for instant-on |
-
2001
- 2001-09-25 US US09/963,185 patent/US20030061436A1/en not_active Abandoned
-
2004
- 2004-06-04 US US10/861,718 patent/US7085878B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386552A (en) * | 1991-10-21 | 1995-01-31 | Intel Corporation | Preservation of a computer system processing state in a mass storage device |
US6101576A (en) * | 1992-07-31 | 2000-08-08 | Fujitsu Limited | Method for saving generated character image in a cache system including a backup cache |
US6470424B1 (en) * | 1997-02-13 | 2002-10-22 | Novell, Inc. | Pin management of accelerator for interpretive environments |
US6539456B2 (en) * | 1999-10-13 | 2003-03-25 | Intel Corporation | Hardware acceleration of boot-up utilizing a non-volatile disk cache |
US6493806B1 (en) * | 2000-03-14 | 2002-12-10 | Intel Corporation | Method and apparatus for generating a transportable physical level data block trace |
US20030005223A1 (en) * | 2001-06-27 | 2003-01-02 | Coulson Richard L. | System boot time reduction method |
US20030046493A1 (en) * | 2001-08-31 | 2003-03-06 | Coulson Richard L. | Hardware updated metadata for non-volatile mass storage cache |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030005223A1 (en) * | 2001-06-27 | 2003-01-02 | Coulson Richard L. | System boot time reduction method |
US6920533B2 (en) | 2001-06-27 | 2005-07-19 | Intel Corporation | System boot time reduction method |
US20030046493A1 (en) * | 2001-08-31 | 2003-03-06 | Coulson Richard L. | Hardware updated metadata for non-volatile mass storage cache |
US7275135B2 (en) | 2001-08-31 | 2007-09-25 | Intel Corporation | Hardware updated metadata for non-volatile mass storage cache |
US20030074524A1 (en) * | 2001-10-16 | 2003-04-17 | Intel Corporation | Mass storage caching processes for power reduction |
US7103724B2 (en) | 2002-04-01 | 2006-09-05 | Intel Corporation | Method and apparatus to generate cache data |
WO2005093588A2 (en) * | 2004-02-27 | 2005-10-06 | Intel Corporation | Interface for a block addressable mass storage system |
WO2005093588A3 (en) * | 2004-02-27 | 2006-12-14 | Intel Corp | Interface for a block addressable mass storage system |
JP2007522590A (en) * | 2004-02-27 | 2007-08-09 | インテル・コーポレーション | Interface for mass storage systems with block addresses |
KR100968998B1 (en) * | 2004-02-27 | 2010-07-09 | 인텔 코포레이션 | Interface for a block addressable mass storage system |
US20050204090A1 (en) * | 2004-03-10 | 2005-09-15 | Eilert Sean S. | Hardware stack for blocked nonvolatile memories |
Also Published As
Publication number | Publication date |
---|---|
US7085878B2 (en) | 2006-08-01 |
US20040225826A1 (en) | 2004-11-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7533215B2 (en) | Distributed and packed metadata structure for disk cache | |
US10740010B2 (en) | Memory module and memory system including memory module | |
JP5216743B2 (en) | Interface for mass storage systems with block addresses | |
US9405680B2 (en) | Communication-link-attached persistent memory system | |
US8370574B2 (en) | System and method for storing configuration data of a storage automation device | |
EP2026356B1 (en) | Method for creating a memory defect map and optimizing performance using the memory defect map | |
US11269846B2 (en) | Efficient database journaling using non-volatile system memory | |
CN101283330A (en) | Fast booting an operating system from an off state | |
US10754737B2 (en) | Boot assist metadata tables for persistent memory device updates during a hardware fault | |
US10725933B2 (en) | Method and apparatus for redirecting memory access commands sent to unusable memory partitions | |
US10331614B2 (en) | Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modules | |
US20220138096A1 (en) | Memory system | |
US7085878B2 (en) | Transportation of main memory and intermediate memory contents | |
US10732859B2 (en) | Systems and methods for granular non-volatile memory health visibility to a host | |
KR102589609B1 (en) | Snapshot management in partitioned storage | |
KR20230161375A (en) | Systems and methods for expandable memory error handling | |
US20110161647A1 (en) | Bootable volatile memory device, memory module and processing system comprising bootable volatile memory device, and method of booting processing system using bootable volatile memory device | |
US20080133836A1 (en) | Apparatus, system, and method for a defined multilevel cache | |
US8225030B2 (en) | Systems and methods for using a page table in an information handling system comprising a semiconductor storage device | |
KR20230134288A (en) | Memory system and operating method thereof | |
US7921324B2 (en) | Providing file system availability during local path failure of a non-server node | |
US10795771B2 (en) | Information handling system with reduced data loss in block mode | |
US20190332533A1 (en) | Maintaining multiple cache areas | |
KR20050058497A (en) | Replacement memory device | |
US11016896B2 (en) | Reducing overhead of managing cache areas |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTEL CORPORATION ( A DELAWARE CORPORATION), CALIF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROYER, ROBERT J., JR.;GARNEY, JOHN I.;REEL/FRAME:012205/0235;SIGNING DATES FROM 20010924 TO 20010925 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |