US20030191876A1 - Data storewidth accelerator - Google Patents

Data storewidth accelerator Download PDF

Info

Publication number
US20030191876A1
US20030191876A1 US10/306,581 US30658102A US2003191876A1 US 20030191876 A1 US20030191876 A1 US 20030191876A1 US 30658102 A US30658102 A US 30658102A US 2003191876 A1 US2003191876 A1 US 2003191876A1
Authority
US
United States
Prior art keywords
data
controller
cache
disk
compression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/306,581
Inventor
James Fallon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Realtime Data LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=46281629&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20030191876(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from US09/775,905 external-priority patent/US6748457B2/en
Application filed by Individual filed Critical Individual
Priority to US10/306,581 priority Critical patent/US20030191876A1/en
Assigned to REALTIME DATA, LLC reassignment REALTIME DATA, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FALLON, JAMES J.
Publication of US20030191876A1 publication Critical patent/US20030191876A1/en
Priority to US11/400,712 priority patent/US7376772B2/en
Priority to US12/688,413 priority patent/US20100332700A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/445Program loading or initiating
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638Organizing or formatting or addressing of data
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device
    • G06F3/0676Magnetic disk device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4406Loading of operating system
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Definitions

  • the present invention relates generally to systems and methods for data storage and retrieval and, more particularly, to data storage controllers employing lossless and/or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth.
  • Modern computers utilize a hierarchy of memory devices. To achieve maximum performance levels, modern processors utilize onboard memory and on board cache to obtain high bandwidth access to both program and data. Limitations in process technologies currently prohibit placing a sufficient quantity of onboard memory for most applications. Thus, in order to offer sufficient memory for the operating system(s), application programs, and user data, computers often use various forms of popular off-processor high speed memory including static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous burst static ram (SBSRAM). Due to the prohibitive cost of the high-speed random access memory, coupled with their power volatility, a third lower level of the hierarchy exists for non-volatile mass storage devices.
  • SRAM static random access memory
  • SDRAM synchronous dynamic random access memory
  • SBSRAM synchronous burst static ram
  • Mass storage devices offer increased capacity and fairly economical data storage.
  • Mass storage devices (such as a “hard disk”) typically store the operating system of a computer system, as well as applications and data and rapid access to such data is critical to system performance.
  • the data storage and retrieval bandwidth of mass storage devices is typically much less as compared with the bandwidth of other elements of a computing system. Indeed, over the last decade, although computer processor performance has improved by at least a factor of 50, magnetic disk storage performance has only improved by a factor of 5. Consequently, memory storage devices severely limit the performance of consumer, entertainment, office, workstation, servers, and mainframe computers for all disk and memory intensive operations.
  • RAID systems often afford the user the benefit of increased data bandwidth for data storage and retrieval.
  • data bandwidth may be increased at a maximum rate that is linear and directly proportional to the number of disks employed.
  • RAID systems also afford the user the benefit of increased data bandwidth for data storage and retrieval.
  • RAID systems employ data redundancy distributed across multiple disks to enhance data storage and retrieval reliability. In the simplest case, data may be explicitly repeated on multiple places on a single disk drive, on multiple places on two or more independent disk drives. More complex techniques are also employed that support various trade-offs between data bandwidth and data reliability.
  • Standard types of RAID systems currently available include RAID Levels 0, 1, and 5.
  • the configuration selected depends on the goals to be achieved. Specifically data reliability, data validation, data storage/retrieval bandwidth, and cost all play a role in defining the appropriate RAID data storage solution.
  • RAID level 0 entails pure data striping across multiple disk drives. This increases data bandwidth at best linearly with the number of disk drives utilized. Data reliability and validation capability are decreased. A failure of a single drive results in a complete loss of all data. Thus another problem with RAID systems is that low cost improved bandwidth requires a significant decrease in reliability.
  • RAID Level 1 utilizes disk mirroring where data is duplicated on an independent disk subsystem. Validation of data amongst the two independent drives is possible if the data is simultaneously accessed on both disks and subsequently compared. This tends to decrease data bandwidth from even that of a single comparable disk drive.
  • the failed drive is removed and a replacement drive is inserted. The data on the failed drive is then copied in the background while the entire system continues to operate in a performance degraded but fully operational mode. Once the data rebuild is complete, normal operation resumes.
  • another problem with RAID systems is the high cost of increased reliability and associated decrease in performance.
  • RAID Level 5 employs disk data striping and parity error detection to increase both data bandwidth and reliability simultaneously. A minimum of three disk drives is required for this technique. In the event of a single disk drive failure, that drive may be rebuilt from parity and other data encoded on disk remaining disk drives. In systems that offer hot swap capability, the failed drive is removed and a replacement drive is inserted. The data on the failed drive is then rebuilt in the background while the entire system continues to operate in a performance degraded but fully operational mode. Once the data rebuild is complete, normal operation resumes.
  • the present invention is generally directed to data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth.
  • a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput.
  • the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration.
  • a controller for controlling storage and retrieval of data to and from a data storage device comprises a data compression/decompression engine for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device, a first cache, operatively connected to the storage device and the data compression/decompression engine, for temporary storage of (i) compressed data that is read from the data storage device and (ii) compressed data from the data compression/decompression engine that is to be written to the data storage device, a second cache, operatively connected to the data compression/decompression engine and to a host interface bus, for temporary storage of (i) data that is received from a host system over the host interface bus for compression and storage and (ii) data that is to be sent to the host system over the host interface bus, and a cache manager for controlling the first and second data caches under commands received from the data compression/decompression engine.
  • first cache, second cache and the data compression/decompression engine are operatively connected by a first local bus and the data compression/decompression engine is connected to the cache manager over a dedicated bus.
  • a magnetic disk controller for controlling storage and retrieval of data to and from a magnetic disk comprises an embedded data compression/decompression engine for compressing data stored to the magnetic disk and for decompressing data retrieved from the magnetic disk, an embedded bi-directional cache for temporary storage of (i) compressed data that is read from the magnetic disk and (ii) compressed data from the data compression/decompression engine that is to be written to the magnetic disk, an embedded cache manager for controlling the bi-directional cache, and an embedded virtual file management system for mapping compressed data blocks stored on the disk to corresponding uncompressed data blocks.
  • the present invention is realized due to recent improvements in processing speed, inclusive of dedicated analog and digital hardware circuits, central processing units, (and any hybrid combinations thereof), that, coupled with advanced data compression and decompression algorithms are enabling of ultra high bandwidth data compression and decompression methods that enable improved data storage and retrieval bandwidth
  • FIG. 1 is a block diagram of a data storage controller according to one embodiment of the present invention.
  • FIG. 2 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIG. 3 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIG. 4 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIG. 5 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIGS. 6 a and 6 b comprise a flow diagram of a method for initializing a data storage controller according to one aspect of the present invention.
  • FIGS. 7 a and 7 b comprise a flow diagram of a method for providing accelerated loading of an operating system and/or application programs upon system boot, according to one aspect of the present invention.
  • FIGS. 8 a and 8 b comprise a flow diagram of a method for providing accelerated loading of application programs according to one aspect of the present invention.
  • FIG. 9 is a diagram of an exemplary data compression system that may be employed in a data storage controller according to the present invention.
  • FIG. 10 is a diagram of an exemplary data decompression system that may be employed in a data storage controller according to the present invention.
  • FIG. 11 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIG. 12 is a block diagram of a data storage controller according to another embodiment of the present invention.
  • FIG. 13 is a block diagram of a data storage device comprising an embedded data storage accelerator, according to an embodiment of the present invention.
  • the present invention may be implemented in various forms of hardware, software, firmware, or a combination thereof.
  • the present invention is implemented on a computer platform including hardware such as one or more central processing units (CPU) or digital signal processors (DSP), a random access memory (RAM), and input/output (I/O) interface(s).
  • the computer platform may also include an operating system, microinstruction code, and dedicated processing hardware utilizing combinatorial logic or finite state machines.
  • the various processes and functions described herein may be either part of the hardware, microinstruction code or application programs that are executed via the operating system, or any combination thereof.
  • the present invention is directed to data storage controllers that provide increased data storage/retrieval rates that are not otherwise achievable using conventional disk controller systems and protocols to store/retrieve data to/from mass storage devices.
  • the concept of “accelerated” data storage and retrieval was introduced in copending U.S. patent application Ser. No. 09/266,394, filed March 11, 1999, entitled “System and Methods For Accelerated Data Storage and Retrieval” and copending U.S. patent application Ser. No. 09/481,243, filed Jan. 11, 2000, entitled “System and Methods For Accelerated Data Storage and Retrieval,” both of which are commonly assigned and incorporated herein by reference.
  • “accelerated” data storage comprises receiving a digital data stream at a data transmission rate which is greater that the data storage rate of a target storage device, compressing the input stream at a compression rate that increases the effective data storage rate of the target storage device and storing the compressed data in the target storage device.
  • a mass storage device such as a hard disk
  • a storage controller for the mass storage device is capable of compressing an input data stream with an average compression rate of 3:1, then data can be stored in the mass storage device at a rate of 60 megabytes per second, thereby effectively increasing the storage bandwidth (“storewidth”) of the mass storage device by a factor of three.
  • accelerated data retrieval comprises retrieving a compressed digital data stream from a target storage device at the rate equal to, e.g., the data access rate of the target storage device and then decompressing the compressed data at a rate that increases the effective data access rate of the target storage device.
  • accelerated data storage/retrieval mitigates the traditional bottleneck associated with, e.g., local and network disk accesses.
  • the data storage controller 10 comprises a data compression engine 12 for compressing/decompressing data (preferably in real-time or psuedo real-time) stored/retrieved from a hard disk 11 (or any other type of mass storage device) to provide accelerated data storage/retrieval.
  • the DCE 12 preferably employs the data compression/decompression techniques disclosed in U.S. Pat. No. 6,195,024, issued on Feb. 27, 2001, entitled “Content Independent Data Compression Method and System,” which is commonly assigned and which is fully incorporated herein by reference. It is to be appreciated that the compression and decompression systems and methods disclosed in U.S. Pat. No. 6,195,024 are suitable for compressing and decompressing data at rates, which provide accelerated data storage and retrieval. A detailed discussion of a preferred “content independent” data compression process will be provided below.
  • the data storage controller 10 further comprises a cache 13 , a disk interface (or disk controller) 14 and a bus interface 15 .
  • the storage controller 10 is operatively connected to the hard disk 12 via the disk controller 14 and operatively connected to an expansion bus (or main bus) 16 of a computer system via the bus interface 15 .
  • the disk interface 14 may employ a known disk interface standard such as UltraDMA, SCSI, Serial Storage Architecture, FibreChannel or any other interface that provides suitable disk access data rates.
  • the storage controller 10 preferably utilizes the American National Standard for Information Systems (ANSI) AT Attachment Interface (ATA/ATAPI-4) to connect the data storage controller 10 to the hard disk 12 .
  • ANSI American National Standard for Information Systems
  • ATA/ATAPI-4 As is known in the art, this standard defines the connectors and cables for the physical interconnects between the data storage controller and the storage devices, along with the electrical and logical characteristics of the interconnecting signals.
  • the bus interface 15 may employ a known standard such as the PCI (Peripheral Component Interconnect) bus interface for interfacing with a computer system.
  • PCI Peripheral Component Interconnect
  • the use of industry standard interfaces and protocols is preferable, as it allows the storage controller 10 to be backwards compatible and seamlessly integrated with current systems.
  • the present invention may be utilize any suitable computer interface or combination thereof.
  • FIG. 1 illustrates a hard disk 12
  • the storage controller 10 may be employed with any form of memory device including all forms of sequential, pseudo-random, and random access storage devices.
  • Storage devices as known within the current art include all forms of random access memory, magnetic and optical tape, magnetic and optical disks, along with various other forms of solid-state mass storage devices.
  • the current invention applies to all forms and manners of memory devices including, but not limited to, storage devices utilizing magnetic, optical, and chemical techniques, or any combination thereof.
  • the cache 13 may comprise volatile or non-volatile memory, or any combination thereof.
  • the cache 13 is implemented in SDRAM (static dynamic random access memory).
  • the system of FIG. 1 generally operates as follows.
  • data When data is read from disk by the host computer, data flows from the disk 11 through the data storage controller 10 to the host computer.
  • Data is stored in one of several proprietary compression formats on the disk 11 (e.g., “content independent” data compression).
  • Data blocks are pre-specified in length, comprised of single or multiple sectors, and are typically handled in fractional or whole equivalents of tracks, e.g. 1 ⁇ 2 track, whole track, multiple tracks, etc.
  • a DMA transfer is setup from the disk interface 14 to the onboard cache memory 13 .
  • the disk interface 14 comprises integral DMA control to allow transfer of data from the disk 11 directly to the onboard cache 13 without intervention by the DCE 12 .
  • the DCE 12 acts as a system level controller and sets-up specific registers within both the disk interface 14 and bus interface 15 to facilitate DMA transfers to and from the cache memory 13 .
  • the DMA transfer is setup via specifying the appropriate command (read disk), the source address (disk logical block number), amount of data to be transferred (number of disk logical blocks), and destination address within the onboard cache memory 13 .
  • a disk data interrupt signal (“DISKINT#”) is cleared (if previously set and not cleared) and the command is initiated by writing to the appropriate address space.
  • DISKINT# disk data interrupt signal
  • the DISKINT# interrupt is asserted notifying the DCE 12 that requested data is now available in the cache memory 13 .
  • Data is then read by the DMA controller within the DCE 12 and placed into local memory for subsequent decompression. The decompressed data is then DMA transferred from the local memory of the DCE 12 back to the cache memory 13 .
  • data is DMA transferred via the bus interface controller 15 from the cache memory 13 to the bus 16 .
  • the data storage controller acts as a bus master.
  • a bus DMA transfer is then setup via specifying the appropriate command (write to host computer), the source address within the cache memory 13 , the quantity of data words to be transferred (transfers are preferably in 4 byte increments), and the destination address on the host computer.
  • the appropriate interrupt signals (respectively referred to as PCIRDINT# and PCIWRINT#) are asserted to the DCE 12 . Either of these interrupts are cleared by a corresponding interrupt service routines through a read or write to the appropriate address of the DCE 12 .
  • data when data is written to the disk 11 from the host computer, data flows from the host computer through the data storage controller 10 and onto disk 11 .
  • Data is normally received from the host computer in uncompressed (raw) format and is compressed by the DCE 12 and stored on the disk 11 .
  • Data blocks from the host are pre-specified in length and are typically handled in blocks that are a fixed multiplier higher than fractional or whole equivalents of tracks, e.g. 1 ⁇ 2 track, whole track, multiple tracks, etc. This multiplier is preferably derived from the expected average compression ratio that is selected when the disk is formatted with the virtual file management system.
  • a bus DMA transfer is setup from the host bus 16 to the onboard cache memory 13 .
  • the bus interface controller 15 comprises integral DMA control that allows large block transfers from the host computer directly to the onboard cache 13 without intervention by the DCE 12 .
  • the bus interface controller 15 acts as a host computer Bus Master when executing such transfer.
  • the onboard DMA controller residing on the DCE 12
  • the compressed data is then DMA transferred from the local memory of the DCE 12 back to the cache memory 13 .
  • data is DMA transferred via the disk controller 14 from the cache 13 to the disk 11 .
  • the data storage controller 10 initializes the onboard interfaces 14 , 5 prior to release of the external host bus 16 from reset.
  • the processor of the host computer requests initial data from the disk 11 to facilitate the computer's boot-up sequence.
  • the host computer requests disk data over the Bus 16 via a command packet issued from the host computer.
  • Command packets are preferably eight words long (in a preferred embodiment, each word comprises 32 bits). Commands are written from the host computer to the data storage controller 10 with the host computer as the Bus Master and the data storage controller 10 as the slave.
  • the data storage controller 10 includes at least one Base Address Register (BAR) for decoding the address of a command queue of the data storage controller 10 .
  • the command queue resides within the cache 13 or within onboard memory of the DCE 12 .
  • an interrupt (referred to herein as PCICMDINT#) is generated to the DCE processor.
  • the eight-word command is read by the DCE 12 and placed into the command queue. Because the commands occupy a very small amount of memory, the location of the command queue is at the discretion of software and the associated system level performance considerations. Commands may be moved from the bus interface 16 to the command queue by wither explicit reads and writes by the DCE processor or, as explained below, by utilizing programmed DMA from an Enhanced DMA Controller (EDMA) residing on the DCE 12 . This second technique may better facilitate system throughput by allowing the EDMA to automatically load commands while the highly pipelined data compression and decompression processing in the DCE is executed fully undisturbed.
  • EDMA Enhanced DMA Controller
  • the DCE 12 , disk interface 14 and bus interface 15 commonly share the cache 13 .
  • the storage controller 10 preferably provides maximum system bandwidth by allowing simultaneous data transfers between the disk 12 and cache 13 , the DCE 12 and the cache 13 , and the expansion bus 16 and the cache 13 .
  • This is realized by employing an integral DMA (direct memory access) protocol that allows the DCE 12 , disk interface 14 and bus interface 15 to transfer data without interrupting or interfering with other ongoing processes.
  • an integral bandwidth allocation controller (or arbitrator) is preferably employed to allow the DCE 12 , disk controller 14 , and bus interface 15 to access the onboard cache with a bandwidth proportional to the overall bandwidth of the respective interface or processing element.
  • the bandwidth arbitration occurs transparently and does not introduce latency in memory accesses.
  • Bandwidth division is preferably performed with a high degree of granularity to minimize the size of requisite onboard buffers to synchronize data from the disk interface 14 and bus interface 15 .
  • n: 1 in disk storage capacity(for example, assuming a compression ration of 3:1, a 20 gigabyte hard drive effectively becomes a 60 gigabyte hard drive) (2) a significant decrease in the computer boot-up time (turn-on and operating system load) and the time for loading application software and (3) User data storage and retrieval is increased by a factor of n:1.
  • FIG. 2 a block diagram illustrates a data storage controller 20 according to another embodiment of the present invention. More specifically, FIG. 2 illustrates a PCB (printed circuit board) implementation of the data storage controller 10 of FIG. 1.
  • the storage controller 20 comprises a DSP (digital signal processor) 21 (or any other micro-processor device) that implements the DCE 12 of FIG. 1.
  • the storage controller 21 further comprises at least one programmable logic device 22 (or volatile logic device).
  • the programmable logic device 22 preferably implements the logic (program code) for instantiating and driving both the disk interface 14 and the bus interface 15 and for providing full DMA capability for the disk and bus interfaces 14 , 15 .
  • the DSP 21 initializes and programs the programmable logic device 22 before of the completion of initialization of the host computer.
  • the data storage controller 20 further comprises a plurality of memory devices including a RAM (random access memory) device 23 and a ROM (read only memory) device 24 (or FLASH memory or other types of non-volatile memory).
  • the RAM device 23 is utilized as on-board cache and is preferably implemented as SDRAM (preferably, 32 megabytes minimum).
  • the ROM device 24 is utilized for non-volatile storage of logic code associated with the DSP 21 and configuration data used by the DSP 21 to program the programmable logic device 22 .
  • the ROM device 24 preferably comprises a one time (erasable) programmable memory (OTP-EPROM) device.
  • the DSP 21 is operatively connected to the memory devices 23 , 24 and the programmable logic device 22 via a local bus 25 .
  • the DSP 21 is also operatively connected to the programmable logic device 22 via an independent control bus 26 .
  • the programmable logic device 22 provides data flow control between the DSP 21 and the host computer system attached to the bus 16 , as well as data flow control between the DSP 21 and the storage device.
  • a plurality of external I/O ports 27 are included for data transmission and/or loading of one programmable logic devices.
  • the disk interface 14 driven by the programmable logic device 22 supports a plurality of hard drives.
  • the storage controller 20 further comprises computer reset and power up circuitry 28 (or “boot configuration circuit”) for controlling initialization (either cold or warm boots) of the host computer system and storage controller 20 .
  • computer reset and power up circuitry 28 or “boot configuration circuit” for controlling initialization (either cold or warm boots) of the host computer system and storage controller 20 .
  • boot configuration circuit 28 is employed for controlling the initializing and programming the programmable logic device 22 during configuration of the host computer system (i.e., while the CPU of the host is held in reset).
  • the boot configuration circuit 28 ensures that the programmable logic device 22 (and possibly other volatile or partially volatile logic devices) is initialized and programmed before the bus 16 (such as a PCI bus) is fully reset.
  • the boot configuration circuit 28 when power is first applied to the boot configuration circuit 28 , the boot configuration circuit 28 generates a control signal to reset the local system (e.g., storage controller 20 ) devices such as a DSP, memory, and I/O interfaces.
  • the controlling device such as the DSP 21
  • the DSP 21 of the disk storage controller 20 would sense that the data storage controller 20 is on a PCI computer bus (expansion bus) and has attached to it a hard disk on an IDE interface.
  • the DSP 21 would then load the appropriate PCI and IDE interfaces into the programmable logic device 22 prior to completion of the host system reset.
  • boot device controller is reset and ready to accept commands over the computer/expansion bus 16 . Details of the boot process using a boot device comprising a programmable logic device will be provided below.
  • the data storage controller 20 may be utilized as a controller for transmitting data (compressed or uncompressed) to and from remote locations over the DSP I/O ports 27 or system bus 16 , for example.
  • the I/O ports 27 of the DSP 21 may be used for transmitting data (compressed or uncompressed) that is either retrieved from the disk 11 or received from the host system via the bus 16 , to remote locations for processing and/or storage.
  • the I/O ports may be operatively connected to other data storage controllers or to a network communication channels.
  • the data storage controller 20 may receive data (compressed or uncompressed) over the I/O ports 27 of the DSP 21 from remote systems that are connected to the I/O ports 27 of the DSP, for local processing by the data storage controller 20 .
  • a remote system may remotely access the data storage controller (via the I/O ports of the DSP or system bus 16 ) to utilize the data compression, in which case the data storage controller would transmit the compressed data back to the system that requested compression.
  • the DSP 21 may comprise any suitable commercially available DSP or processor.
  • the data storage controller 20 utilizes a DSP from Texas Instruments' 320 series, C62x family, of DSPs (such as TMS320C6211GFN-150), although any other DSP or processor comprising a similar architecture and providing similar functionalities may be employed.
  • the preferred DSP is capable of up to 1.2 billion instructions per second. Additional features of the preferred DSP include a highly parallel eight processor single cycle instruction execution, onboard 4K byte LIP Program Cache, 4K LID Data Cache, and 64K byte Unified L2 Program/Data Cache.
  • the preferred DSP further comprises a 32 bit External Memory Interface (EMIF) that provides for a glueless interface to the RAM 23 and the non-volatile memory 24 (ROM).
  • the DSP further comprises two multi-channel buffered serial ports (McBSPs) and two 32 bit general purpose timers.
  • McBSPs multi-channel buffered serial ports
  • the storage controller disables the I/O capability of these devices and utilizes the I/O ports of the DSP as general purpose I/O for both programming the programmable logic device 22 using a strobed eight bit interface and signaling via a Light Emitting Diode (LED).
  • LED Light Emitting Diode
  • Ancillary DSP features include a 16 bit Host Port Interface and full JTAG emulation capability for development support.
  • the programmable logic device 22 may comprise any form of volatile or non-volatile memory.
  • the programmable logic device 22 comprises a dynamically reprogrammable FPGA (field programmable gate array) such as the commercially available Xilinx Spartan Series XCS40XL-PQ240-5 FPGA.
  • the FPGA instantiates and drives the disk and bus interfaces 14 , 15 .
  • the non-volatile memory device 24 preferably comprises a 128 Kbyte M27W101-80K one time (erasable) programmable read only memory, although other suitable non-volatile storage devices may be employed.
  • the non-volatile memory device 24 is decoded at a designated memory space in the DSP 21 .
  • the non-volatile memory device 24 stores the logic for the DSP 21 and configuration data for the programmable logic device 22 . More specifically, in a preferred embodiment, the lower 80 Kbytes of the non-volatile memory device 24 are utilized for storing DSP program code, wherein the first 1 k bytes are utilized for the DSP's boot loader. Upon reset of the DSP 21 (via boot configuration circuit 28 ), the first 1 K of memory of the non-volatile memory device 24 is copied into an internal RAM of the DSP 21 by e.g., the DSP's Enhanced DMA Controller (EDMA).
  • EDMA Enhanced DMA Controller
  • the boot process begins when the CPU of the host system is released from external reset, the transfer of the boot code into the DSP and the DSP's initialization of the programmable logic device actually occurs while the CPU of the host system is held in reset. After completion of the 1K block transfer, the DSP executes the boot loader code and continues thereafter with executing the remainder of the code in non-volatile memory device to program the programmable logic device 22 .
  • the upper 48K bytes of the non-volatile memory device 24 are utilized for storing configuration data associated with the programmable logic device 22 .
  • the data storage controller 20 is employed as the primary boot storage device for the host computer, the logic for instantiating and driving the disk and bus interfaces 14 , 15 should be stored on the data storage controller 20 (although such code may be stored in remotely accessible memory locations) and loaded prior to release of the host system bus 16 from “reset”. For instance, revision 2.2 of the PCI Local Bus specification calls for a typical delay of 100 msec from power-stable before release of PCI Reset. In practice this delay is currently 200 msec although this varies amongst computer manufacturers. A detailed discussion of the power-on sequencing and boot operation of the data storage controller 20 will be provided below.
  • FIG. 3 illustrates another embodiment of a data storage controller 30 wherein the data storage controller 35 is embedded within the motherboard of the host computer system.
  • This architecture provides the same functionality as the system of FIG. 2, and also adds the cost advantage of being embedded on the host motherboard.
  • the system comprises additional RAM and ROM memory devices 23 a , 24 a , operatively connected to the DSP 21 via a local bus 25 a.
  • FIG. 4 illustrates another embodiment of a data storage controller.
  • the data storage controller 40 comprises a PCB implementation that is capable of supporting RAID levels 0, 1 and 5. This architecture is similar to those of FIGS. 1 and 2, except that a plurality of programmable logic devices 22 , 22 a are utilized.
  • the programmable logic device 22 is dedicated to controlling the bus interface 15 .
  • the programmable logic device 22 a is dedicated to controlling a plurality of disk interfaces 14 , preferably three interfaces. Each disk interface 14 can connect up to two drives.
  • the DSP in conjunction with the programmable logic device 22 a can operate at RAID level 0, 1 or 5. At RAID level 0, which is disk striping, two interfaces are required. This is also true for RAID level 1, which is disk mirroring. At RAID level 5, all three interfaces are required.
  • FIG. 5 illustrates another embodiment of a data storage controller according to the present invention.
  • the data storage controller 45 provides the same functionality as that of FIG. 4, and has the cost advantage of being embedded within the computer system motherboard.
  • the data storage controller 20 preferably employs an onboard Texas Instruments TMS320C6211 Digital Signal Processor (DSP) to program the onboard Xilinx Spartan Series XCS40XL FPGA upon power-up or system level PCI reset.
  • DSP Digital Signal Processor
  • the onboard boot configuration circuit 28 ensures that from system power-up and/or the assertion of a bus reset (e.g., PCI reset), the DSP 21 is allotted a predetermined amount of time (preferably a minimum of 10 msec) to boot the DSP 21 and load the programmable logic device 22 .
  • an “Express Mode” programming mode for configuring the SpartanXL family XCS40XL device is preferably employed.
  • the XCS40XL is factory set to byte-wide Express-Mode programming by setting both the M1/M0 bits of the XCS40XL to 0x0.
  • the DSP 21 is programmed to utilize its serial ports reconfigured as general purpose I/O. However, after the logic device 22 is programmed, the DSP 21 may then reconfigure its serial ports for use with other devices.
  • using the same DSP ports for multiple purposes affords greater flexibility while minimizing hardware resources and thus reducing product cost.
  • the volatile nature of the logic device 22 effectively affords the ability to have an unlimited number of hardware interfaces. Any number of programs for execution by the programmable logic device 22 can be kept in an accessible memory location (EPROM, hard disk, or other storage device). Each program can contain new disk interfaces, interface modes or subsets thereof. When necessary, the DSP 21 can clear the interface currently residing in the logic device 22 and reprogram it with a new interface. This feature allows the data storage controller 20 to have compatibility with a large number of interfaces while minimizing hardware resources and thus reducing product cost.
  • a preferred protocol for programming the programmable logic device can be summarized in the following steps: (1) Clearing the configuration memory; (2) Initialization; (3) Configuration; and (4) Start-Up.
  • the host computer is first powered-up or a power failure and subsequent recovery occurs (cold boot), or a front panel computer reset is initiated (warm boot), the host computer asserts RST# (reset) on the PCI Bus.
  • the data storage controller 20 preferably comprises a boot configuration circuit 28 that senses initial host computer power turn-on and/or assertion of a PCI Bus Reset (“PCI RST#”).
  • PCI RST# is asserted as soon as the computer's power exceeds a nominal threshold of about 1 volt (although this varies) and remains asserted for 200 msec thereafter.
  • Power failure detection of the 5 volt or 3.3 volt bus typically resets the entire computer as if it is an initial power-up event (i.e., cold boot).
  • Front panel resets (warm boots) are more troublesome and are derived from a debounced push-button switch input.
  • Typical front panel reset times are a minimum of 20 msec, although again the only governing specification limit is 1 msec reset pulse width.
  • the boot configuration circuit 20 preferably comprises a state machine output signal that is readable by the DSP 21 to ascertain the type of boot process requested. For example, with a front-panel reset (warm boot), the power remains stable on the PCI Bus, thus the programmable logic device 22 should not require reloading.
  • FIG. 6 a flow diagram illustrates a method for initializing the programmable logic device 22 according to one aspect of the invention.
  • the DSP 21 is reset by asserting a DSP reset signal (step 50 ).
  • the DSP reset signal is generated by the boot circuit configuration circuit 28 (as described in the above-incorporated U.S. patent application Ser. No. 09/775,897). While the DSP reset signal is asserted (e.g., active low), the DSP is held in reset and is initialized to a prescribed state.
  • the logic code for the DSP (referred to as the “boot loader”) is copied from the non-volatile logic device 24 into memory residing in the DSP 21 (step 51 ). This allows the DSP to execute the initialization of the programmable logic device 22 .
  • the lower 1K bytes of EPROM memory is copied to the first 1 k bytes of DSP's low memory (0x0000 0000 through 0x0000 03FF).
  • the memory mapping of the DSP 21 maps the CE1 memory space located at 0x9000 0000 through 0x9001 FFFF with the OTP EPROM.
  • this ROM boot process is executed by the EDMA controller of the DSP. It is to be understood, however, that the EDMA controller may be instantiated in the programmable logic device (Xilinx), or shared between the DSP and programmable logic device.
  • Xilinx programmable logic device
  • the DSP 21 begins execution out of the lower 1K bytes of memory (step 52 ).
  • the DSP 21 initializes with at least the functionality to read EPROM Memory (CE1) space.
  • the DSP preferably configures its serial ports as general purpose I/O (step 53 ).
  • the DSP 21 will initialize the programmable logic device 22 using one or more suitable control signals. (step 54 ). After initialization, the DSP 21 begins reading the configuration data of the programmable logic device 22 from the non-volatile memory 24 (step 55 ). This process begins with clearing a Data Byte Counter and then reading the first data byte beginning at a prespecified memory location in the non-volatile memory 24 (step 56 ). Then, the first output byte is loaded into the DSP's I/O locations with LSB at D0 and MSB at D7 (step 57 ).
  • a prespecified time delay (e.g., 5 usec) is provided to ensure that the logic device 22 has been initialized (step 58 ).
  • this time delay should be of a duration at least equal to the internal setup time of the programmable logic device 22 from completion of initialization.
  • step 60 a determination is made as to whether the Data Byte Counter is less than a prespecified value. If the Data Byte Counter is less than the prespecified value (affirmative determination in step 60 ), the next successive data byte for the programmable logic device 22 is read from the non-volatile memory 24 (step 61 ) and the Data Byte Counter is incremented (step 62 ).
  • the read data byte is loaded into the I/O of the DSP (step 63 ).
  • a time delay of, e.g., 20 nsec is allowed to expire before the data byte is latched to the programmable logic device to ensure that a minimum data set-up time to the programmable logic device 21 is observed (step 64 ) and the process is repeated (return to step 60 ).
  • steps 60 - 64 may be performed while the current data byte is being latched to the programmable logic device. This provides “pipeline” programming of the logic device 22 and minimizes programming duration.
  • step 65 the last data byte is read from the non-volatile memory and latched to the programmable logic device 22 , and the DSP 21 will then poll a control signal generated by the programmable logic device 22 to ensure that the programming of the logic device 22 is successful (step 65 ). If programming is complete (affirmative determination in step 66 ), the process continues with the remainder of the data storage controller initialization (step 67 ). Otherwise, a timeout occurs (step 68 ) and upon expiration of the timeout, an error signal is provided and the programming process is repeated (step 69 ).
  • the data storage controller 20 utilizes a plurality of commands to implement the data storage, retrieval, and disk maintenance functions described herein. Each command preferably comprises eight thirty-two bit data words stored and transmitted in little endian format.
  • the commands include: Read Disk Data; Write Disk Data; and Copy Disk Data, for example.
  • a preferred format for the “Read Disk Data” command is: 31 16 15 8 7 0 Command Packet Number Command Type Command 00h 0000h to FFFFh 00h Parameters (00h) Starting Block Address (Least Significant Word) 04h Starting Block Address (Most Significant Word) 08h Number of Blocks (Least Significant Word) 0Ch Number of Blocks (Most Significant Word) 10h Destination Address (Least Significant Word) 14h Destination Address (Most Significant Word) 18h Checksum Reserved 1Ch
  • the host computer commands the data storage controller 20 over the PCI Bus 16 , for example.
  • the host computer issues a PCI Bus Reset with a minimum pulse width of 100 msec (in accordance with PCI Bus Specification Revision 2.2).
  • PCI Bus Reset with a minimum pulse width of 100 msec (in accordance with PCI Bus Specification Revision 2.2).
  • the data storage controller 20 is fully initialized and waiting for completion of the PCI configuration cycle.
  • the data storage controller will wait in an idle state for the first disk command.
  • the host operating system may issue a command to the data storage controller 20 to store, retrieve, or copy specific logical data blocks.
  • Each command is transmitted over the PCI Bus 16 at the Address assigned to the Base Address Register (BAR) of the data storage controller 20 .
  • BAR Base Address Register
  • the commands issued by the host system to the data storage controller and the data transmitted to and from the data storage controller are preferably communicated via a 32 bit, 33 MHz, PCI Data Bus.
  • the PCI Interface is preferably housed within the onboard Xilinx Spartan XCS40XL-5 40,000 field programmable gate array which instantiates a PCI 32, 32 Bit, 33 MHz PCI Bus Interface (as per PCI Bus Revision 2.2).
  • the PCI Bus interface operates in Slave Mode when receiving commands and as a Bus Master when reading or writing data.
  • the source and destination for all data is specified within each command packet.
  • the Enhanced Direct Memory Access (EDMA) Controller of the DSP (or the Xilinx) utilizes two Control Registers, a 16 Word Data Write to PCI Bus FIFO, a 16 Word Data Read From PCI Bus FIFO, and a PCI Data Interrupt (PCIDATINT).
  • the 32 Bit PCI Address Register holds either the starting Source Address for data storage controller Disk Writes where data is read from the PCI Bus, or the starting Destination Address for data storage controller Disk Reads where data is written to the PCI Bus.
  • the second control register is a PCI Count Register that specifies the direction of the data transfer along with the number of 32 bit Data words to be written to or from the PCI bus.
  • Data is written to the PCI Bus from the DSP via a 16 Word PCI Data Write FIFO located within a prespecified address range. Data writes from the DSP to anywhere within the address range place that data word in the next available location within the FIFO. Data is read from the PCI Bus to the DSP via a 16 Word PCI Data Read FIFO located within a prespecified address range and data read by the DSP from anywhere within this address range provides the next data word from the FIFO.
  • the data storage controller After completion of the Xilinx initialization by the DSP and subsequent negation of the PCI Bus Reset signal (RST#) by the host computer's PCI Bridge, the data storage controller is ready to accept commands from the host computer via the PCI Bus.
  • the data storage controller is a PCI Target (Slave) Device. Commands are preferably fixed in length at exactly 8 (thirty-two bit) words long. Commands are written from the host computer to the data storage controller via the PCI Bus utilizing the data storage controller's Base Address Register 0 (BAR0).
  • BAR0 Base Address Register 0
  • the PCI Bus Reset initially sets the Command FIFO's Counter to zero and also signals the Xilinx's PCI Bus State Controller that the Command FIFO is empty and enable to accept a command.
  • the PCI Command FIFO State Controller then asserts the Command Available Interrupt to the DSP.
  • the DSP services the Command Available Interrupt by reading the command data from a prespecified address range. It should be noted that the command FIFO is read sequentially from any data access that reads data within such address range. It is the responsibility of the DSP to understand that the data is read sequentially from any order of accesses within the data range and should thus be stored accordingly.
  • the DSP Upon completion of the Command Available Interrupt Service Routine the DSP executes a memory read or write to desired location within the PCI Control Register Space mapped into the DSP's CE3 (Xilinx) memory space. This resets the Command FIFO Counter back to zero. Next, the DSP executes a memory read or write to location in the DSP Memory Space that clears the Command Available Interrupt. Nested interrupts are not possible since the PCI Bus State Machine is not yet able to accept any Command Data at BAR0. Once the Command Available Interrupt routine has cleared the interrupt and exited, the DSP may then enable the PCI State Machine to accept a new command by reading or writing to PCI Command Enable location within the PCI Command FIFO Control Register Space.
  • a preferred architecture has been selected to enable the data storage controller to operate on one command at a time or to accept multiple prioritized commands in future implementations.
  • the decoupling of the Command Available Interrupt Service Routine from the PCI State Machine that accepts Commands at BAR0 enables the DSP's “operating system kernel” to accept additional commands at any time by software command.
  • a command is accepted, the Command Available Interrupt Cleared, and the Command executed by the data storage controller in PCI Master Mode prior to the enabling of the PCI State machine to accept new commands.
  • the “operating system kernel” may elect to immediately accept new commands or defer the acceptance of new commands based upon any software implemented decision criteria.
  • the O/S code might only allow a pre-specified number of commands to be queued.
  • commands might only be accepted during processor idle time or when the DSP is not executing time critical (i.e. highly pipelined) compress/decompress routines.
  • various processes are enabled based upon a pre-emptive prioritized based scheduling system.
  • the data storage controller retrieves commands from the input command FIFO in 8 thirty-two bit word packets. Prior to command interpretation and execution, a command's checksum value is computed to verify the integrity of the data command and associated parameters. If the checksum fails, the host computer is notified of the command packet that failed utilizing the Command Protocol Error Handler. Once the checksum is verified the command type and associated parameters are utilized as an offset into the command “pointer” table or nay other suitable command/data structure that transfers control to the appropriate command execution routine.
  • Commands are executed by the data storage controller with the data storage controller acting as a PCI Master. This is in direct contrast to command acceptance where the data storage controller acts as a PCI Slave.
  • the data storage controller When acting as a PCI Bus Master, the data storage controller reads or writes data to the PCI Bus utilizing a separate PCI Bus Data FIFO (distinct & apart from the Command FIFO).
  • the PCI Data FIFO is 64 (thirty-two bit) words deep and may be utilized for either data reads or data writes from the DSP to the PCI Bus, but not both simultaneously.
  • the DSP For data to be written from the data storage controller to the Host Computer, the DSP must first write the output data to the PCI Bus Data FIFO.
  • the Data FIFO is commanded to PCI Bus Data Write Mode by writing to a desired location within the Xilinx (CE3) PCI Control Register Space.
  • PCI Bus Reset the default state for the PCI Data FIFO is write mode and the PCI Data FIFO Available Interrupt is cleared.
  • the PCI Data FIFO Available Interrupt should also be software cleared by writing to a prespecified location.
  • the first task for the data storage controller is for system boot-up or application code to be downloaded from disk.
  • PCI Data Read Mode is commanded by writing to location BFF0 0104.
  • the PCI Bus Reset initializes the Data FIFO Pointer to the first data of the 64 data words within the FIFO. However this pointer should always be explicitly initialized by a memory write to location BFF0 0108. This ensures that the first data word written to the FIFO by the DSP performing the data write anywhere in address range B000 0000 to B000 01FF is placed at the beginning of the FIFO. Each subsequent write to any location within this address range then places one thirty-two bit data word into the next available location within the PCI Data FIFO.
  • the FIFO accepts up to 64 thirty-two bit data words although it should be clearly understood that not all data transfers to and from the PCI Bus will consist of a full FIFO.
  • Counting the number of thirty-two bit data words written to the PCI Data FIFO is the responsibility of the DSP Code. It is envisioned that the DSP will, in general, use 64 word DMA data transfers, thus alleviating any additional processor overhead.
  • the PCI Bus Controller also needs the address of the PCI Target along with the number of data words to be transmitted.
  • the PCI Bus Address is thirty-two bits wide, although future PCI bus implementations may utilize multiword addressing and/or significantly larger (64 bit & up) address widths.
  • the single thirty-two bit address word is written by the DSP to memory location aaaa+0 ⁇ 10 in the PCI Control Register Space.
  • PCI Bus Data Write transaction is initiated by writing the PCI Data FIFO word count to a prespecified memory address.
  • the word count value is always decimal 64 or less (0 ⁇ 3F).
  • the count register is written the value is automatically transferred to the PCI Controller for executing the PCI Bus Master writes.
  • PCI Data FIFO Available Interrupt When the PCI Bus has completed the transfer of all data words within the PCI Data FIFO the PCI Data FIFO Available Interrupt is set. The DSP PCI Data FIFO Available Interrupt handler will then check to see if additional data is waiting or expected to be written to the PCI Data Bus. If additional data is required the interrupt is cleared and the data transfer process repeats. If no additional data is required to be transferred then the interrupt is cleared and the routine must exit to a system state controller. For example, if the command is complete then master mode must be disabled and then slave mode (command mode) enabled—assuming a single command by command execution data storage controller.
  • the DSP For data to be read by the data storage controller from the Host Computer, the DSP must command the PCI Bus with the address and quantity of data to be received.
  • the PCI Data FIFO is commanded to PCI Bus Data Read Mode by writing to a desired location within the Xilinx (CE3) PCI Control Register Space.
  • PCI Bus Reset the default state for the PCI Data FIFO is Write Mode and the PCI Data FIFO Full Interrupt is cleared.
  • the PCI Data FIFO Full Interrupt should also be cleared via software by writing to such location.
  • the PCI Bus Reset also initializes the PCI Data FIFO Pointer to the first data word of the available 64 data words within the FIFO. However this pointer should always be explicitly initialized by a memory write to prespecified location.
  • the Xilinx PCI Bus Controller requires the address of the PCI Target along with the number of data words to be received.
  • the PCI Bus Address is thirty-two bits wide, although future PCI bus implementations may utilize multiword addressing and/or significantly larger (64 bit & up) address widths. The single thirty-two bit address word is written by the DSP to prespecified memory location in the PCI Control Register Space.
  • PCI Bus Data Read transaction is initiated by writing the PCI Data FIFO word count to prespecified memory address.
  • the word count value is always decimal 64 or less (0 ⁇ 3F).
  • the count register is written the value is automatically transferred to the PCI Controller for executing the PCI Bus Master Read.
  • PCI Data FIFO Full Interrupt When the PCI Bus has received all the requested data words PCI Data FIFO Full Interrupt is set. The DSP PCI Data FIFO Full Interrupt handler will then check to see if additional data is waiting or expected to be read from the PCI Data Bus. If additional data is required the interrupt is cleared and the data receipt process repeats. If no additional data is required to be transferred, then the interrupt is cleared and the routine exits to a system state controller. For example, if the command is complete then master mode must be disabled and then slave mode (command mode) enabled—assuming a single command by command execution data storage controller.
  • the onboard cache of the data storage controller is shared by the DSP, Disk Interface, and PCI Bus.
  • the best case, maximum bandwidth for the SDRAM memory is 70 megawords per second, or equivalently, 280 megabytes per second.
  • the 32 bit PCI Bus interface has a best case bandwidth of 132 megabytes per second, or equivalently 33 megawords per second. In current practice, this bandwidth is only achieved in short bursts.
  • the granularity of PCI data bursts to/from the data storage controller is governed by the PCI Bus interface data buffer depth of sixteen words (64 bytes).
  • the time division multiplexing nature of the current PCI Data Transfer Buffering methodology cuts the 10 sustained PCI bandwidth down to 66 megabytes/second.
  • Each EMIF clock cycle is 14.2857 nsec, thus the maximum latency translates to 224 clock cycles. It should be noted that transfers across the disk interface are 16 bits wide, thus the FPGA is required to translate 32 bit memory transfers to 16 bit disk transfers, and vice-versa.
  • the DSP services request for its external bus from two requesters, the Enhanced Direct Memory Access (EDMA) Controller and an external shared memory device controller.
  • the DSP can typically utilize the full 280 megabytes of bus bandwidth on an 8k through 64K byte (2 k word through 16 k word) burst basis. It should be noted that the DSRA does not utilize the SDRAM memory for interim processing storage, and as such only utilizes bandwidth in direct proportion to disk read and write commands.
  • PCI Bus Interface A + B
  • DSP Accesses A + B/K
  • each ratio may all be scaled by a constant in order to most effectively utilize the bandwidths of the internal busses and external interfaces.
  • each ratio can be scale by an adjustment factor based upon the time required to complete individual cycles. For example if PCI Bus interface takes 20% longer than all other cycles, the PCI time slice should be adjusted longer accordingly.
  • the boot device controller will wait for a command over the computer bus (such as PCI). Since the boot device controller will typically be reset prior to bus reset and before the computer bus starts sending commands, this wait period is unproductive time. The initial bus commands inevitably instruct the boot device controller to retrieve data from the boot device (such as a disk) for the operating system. Since most boot devices are relatively slow compared to the speed of most computer busses, a long delay is seen by the computer user. This is evident in the time it takes for a typical computer to boot.
  • a data storage controller may employ a technique of data preloading to decrease the computer system boot time.
  • the data storage controller Upon host system power-up or reset, the data storage controller will perform a self-diagnostic and program the programmable logic device (as discussed above) prior to completion of the host system reset (e.g., PCI bus reset) so that the logic device can accept PCI Bus commands after system reset.
  • the data storage controller can proceed to pre-load the portions of the computer operating system from the boot device (e.g., hard disk) into the on-board cache memory. The data storage controller preloads the needed sectors of data in the order in which they will be needed.
  • the boot device controller Since the same portions of the operating system must be loaded upon each boot process, it is advantageous for the boot device controller to preload such portions and not wait until it is commanded to load the operating system.
  • the data storage controller employs a dedicated 10 channel of the DSP (with or without data compression) to pre-load computer operating systems and applications.
  • the data storage controller could also preload other data that the user would likely want to use at startup.
  • An example of this would be a frequently used application such as a word processor and any number of document files.
  • Another technique (illustrated by the flow diagram of FIGS. 7 a and 7 b ) that may be employed comprises an automatic process that requires no input from the user.
  • the data storage controller maintain a list comprising the data associated with the first series of data requests received by the data storage controller by the host system after a power-on/reset.
  • the data storage controller will receive requests for the boot data (step 70 ).
  • the data storage controller will retrieve the requested boot data from the boot device (e.g., hard disk) in the local cache memory (step 71 ).
  • the data storage controller will record the requested data block number in a list (step 72 ).
  • the data storage controller will record the data block number of each data block requested by the host computer during the boot process (repeat steps 70 - 72 ).
  • the data storage controller will store the data list on the boot device (or other storage device) (step 74 ).
  • the data storage controller would retrieve and read the stored list (step 76 ) and proceed to preload the boot data specified on the list (i.e., the data associated with the expected data requests) into the onboard cache memory (step 77 ).
  • the preloading process may be completed prior to commencement of the boot process, or continued after the boot process begins (in which case booting and preloading are performed simultaneously).
  • step 78 the storage controller is initialized and the system bus reset is deasserted
  • the data storage controller will receive requests for boot data (step 79 ). If the host computer issues a request for boot data that is pre-loaded in the local memory of the data storage controller (affirmative result in step 80 ), the request is immediately serviced using the preloaded boot data (step 81 ). If the host computer issues a request for boot data that is not preloaded in the local memory of the data storage controller (negative determination in step 80 ), the controller will retrieve the requested data from the boot device, store the data in the local memory, and then deliver the requested boot data to the computer bus (step 82 ).
  • the data storage controller would update the boot data list by recording any changes in the actual data requests as compared to the expected data requests already stored in the list (step 83 ). Then, upon the next boot sequence, the boot device controller would pre-load that data into the local cache memory along with the other boot data previously on the list.
  • step 84 if no request is made by the host computer for a data block that was pre-loaded into the local memory of the data storage controller (affirmative result in step 84 ), then the boot data list will be updated by removing the non-requested data block from the list (step 85 ). Thereafter, upon the next boot sequence, the data storage controller will not pre-load that data into local memory.
  • the data storage controller may employ a technique of data preloading to decrease the time to load application programs (referred to as “quick launch”).
  • quick launch a technique of data preloading to decrease the time to load application programs
  • the file system reads the first few blocks of the file off the disk, and then the portion of the loaded software will request via the file system what additional data it needs from the disk.
  • a user may open a spreadsheet program, and the program may be configured to always load a company spreadsheet each time the program is started.
  • the company spreadsheet may require data from other spreadsheet files.
  • the data storage controller may be configured to “remember” what data is typically loaded following the launch of the spreadsheet program, for example. The data storage controller may then proceed to preload the company spreadsheet and all the necessary data in the order is which such data is needed. Once this is accomplished, the data storage controller can service read commands using the preloaded data. Before transmission to the bus, if the preloaded data was stored in compressed format, the data will be decompressed. The process of preloading (compressed) program data significantly reduces the time for launching an application.
  • a custom utility program is employed that would allow the user to specify what applications should be made ready for quick launch.
  • FIGS. 8 a and 8 b comprise a flow diagram of a quick launch method according to one aspect of the present invention.
  • the data storage controller maintains a list comprising the data associated with launching an application.
  • the data storage controller will receive requests for the application data (step 90 ).
  • the data storage controller will retrieve the requested application data from memory (e.g., hard disk) and store it in the local cache memory (step 91 ).
  • the data storage controller will record the data block number of each data block requested by the host computer during the launch process (step 92 ).
  • the data storage controller will store the data list in a designated memory location (step 94 ).
  • the data storage controller upon each subsequent launch of the application (affirmative result in step 95 ), the data storage controller would retrieve and read the stored list (step 96 ) and then proceed to preload the application data specified on the list (i.e., the data associated with the expected data requests) into the onboard cache memory (step 97 ). During the application launch process, the data storage controller will receive requests for application data (step 98 ). If the host computer issues a request for application data that is pre-loaded in the local memory of the data storage controller (affirmative result in step 99 ), the request is immediately serviced using the preloaded data (step 100 ).
  • the controller will retrieve the requested data from the hard disk memory, store the data in the local memory, and then deliver the requested application data to the computer bus (step 101 ).
  • the data storage controller would update the application data list by recording any changes in the actual data requests as compared to the expected data requests already stored in the list (step 102 ).
  • step 103 if no request is made by the host computer for a data block that was pre-loaded into the local memory of the data storage controller (affirmative result in step 103 ), then the application data list will be updated by removing the non-requested data block from the list (step 104 ). Thereafter, upon the next launch sequence for the given application, the data storage controller will not pre-load that data into local memory.
  • quick boot and quick launch methods described above are preferably implemented by a storage controller according to the present invention and may or may not utilize data compression/decompression by the DSP.
  • the quick boot and quick launch methods may be implemented by a separate device, processor, or system, or implemented in software.
  • any conventional compression/decompression system and method (which comply with the above mentioned constraints) may be employed in the data storage controller for providing accelerated data storage and retrieval in accordance with the present invention.
  • the present invention employs the data compression/decompression techniques disclosed in the above-incorporated U.S. Pat. No. 6,195,024.
  • FIG. 9 a detailed block diagram illustrates an exemplary data compression system 110 that may be employed herein. Details of this data compression system are provided in U.S. Pat. No. 6,195,024.
  • the data compression system 110 accepts data blocks from an input data stream and stores the input data block in an input buffer or cache 115 . It is to be understood that the system processes the input data stream in data blocks that may range in size from individual bits through complete files or collections of multiple files. Additionally, the input data block size may be fixed or variable.
  • a counter 120 counts or otherwise enumerates the size of input data block in any convenient units including bits, bytes, words, and double words.
  • the input buffer 115 and counter 120 are not required elements of the present invention.
  • the input data buffer 115 may be provided for buffering the input data stream in order to output an uncompressed data stream in the event that, as discussed in further detail below, every encoder fails to achieve a level of compression that exceeds an a priori specified minimum compression ratio threshold.
  • Data compression is performed by an encoder module 125 which may comprise a set of encoders E 1 , E 2 , E 3 . . . En.
  • the encoder module 125 successively receives as input each of the buffered input data blocks (or unbuffered input data blocks from the counter module 120 ). Data compression is performed by the encoder module 125 wherein each of the encoders E 1 . . . En processes a given input data block and outputs a corresponding set of encoded data blocks. It is to be appreciated that the system affords a user the option to enable/disable any one or more of the encoders E 1 . . . En prior to operation. As is understood by those skilled in the art, such feature allows the user to tailor the operation of the data compression system for specific applications. It is to be further appreciated that the encoding process may be performed either in parallel or sequentially.
  • encoders E 1 through En of encoder module 125 may operate in parallel (i.e., simultaneously processing a given input data block by utilizing task multiplexing on a single central processor, via dedicated hardware, by executing on a plurality of processor or dedicated hardware systems, or any combination thereof).
  • encoders E 1 through En may operate sequentially on a given unbuffered or buffered input data block. This process is intended to eliminate the complexity and additional processing overhead associated with multiplexing concurrent encoding techniques on a single central processor and/or dedicated hardware, set of central processors and/or dedicated hardware, or any achievable combination.
  • encoders of the identical type may be applied in parallel to enhance encoding speed.
  • encoder E 1 may comprise two parallel Huffman encoders for parallel processing of an input data block.
  • a buffer/counter module 130 is operatively connected to the encoder module 125 for buffering and counting the size of each of the encoded data blocks output from encoder module 125 .
  • the buffer/counter 130 comprises a plurality of buffer/counters BC 1 , BC 2 , BC 3 . . . .BCn, each operatively associated with a corresponding one of the encoders E 1 . . . En.
  • a compression ratio module 135 operatively connected to the output buffer/counter 130 , determines the compression ratio obtained for each of the enabled encoders E 1 . . . En by taking the ratio of the size of the input data block to the size of the output data block stored in the corresponding buffer/counters BC 1 . . .
  • the compression ratio module 135 compares each compression ratio with an a priori-specified compression ratio threshold limit to determine if at least one of the encoded data blocks output from the enabled encoders E 1 . . . En achieves a compression that exceeds an a priori-specified threshold.
  • the threshold limit may be specified as any value inclusive of data expansion, no data compression or expansion, or any arbitrarily desired compression limit.
  • a description module 138 operatively coupled to the compression ratio module 135 , appends a corresponding compression type descriptor to each encoded data block which is selected for output so as to indicate the type of compression format of the encoded data block.
  • a data compression type descriptor is defined as any recognizable data token or descriptor that indicates which data encoding technique has been applied to the data. It is to be understood that, since encoders of the identical type may be applied in parallel to enhance encoding speed (as discussed above), the data compression type descriptor identifies the corresponding encoding technique applied to the encoded data block, not necessarily the specific encoder. The encoded data block having the greatest compression ratio along with its corresponding data compression type descriptor is then output for subsequent data processing, storage, or transmittal. If there are no encoded data blocks having a compression ratio that exceeds the compression ratio threshold limit, then the original unencoded input data block is selected for output and a null data compression type descriptor is appended thereto.
  • a null data compression type descriptor is defined as any recognizable data token or descriptor that indicates no data encoding has been applied to the input data block. Accordingly, the unencoded input data block with its corresponding null data compression type descriptor is then output for subsequent data processing, storage, or transmittal.
  • the embodiment of the data compression engine of FIG. 9 is exemplary of a preferred compression system which may be implemented in the present invention, and that other compression systems and methods known to those skilled in the art may be employed for providing accelerated data storage in accordance with the teachings herein.
  • a timer is included to measure the time elapsed during the encoding process against an a priori-specified time limit. When the time limit expires, only the data output from those encoders (in the encoder module 125 ) that have completed the present encoding cycle are compared to determine the encoded data with the highest compression ratio.
  • the time limit ensures that the real-time or pseudo real-time nature of the data encoding is preserved.
  • the results from each encoder in the encoder module 125 may be buffered to allow additional encoders to be sequentially applied to the output of the previous encoder, yielding a more optimal lossless data compression ratio.
  • FIG. 10 a detailed block diagram illustrates an exemplary decompression system that may be employed herein or accelerated data retrieval as disclosed in the above-incorporated U.S. Pat. No. 6,195,024.
  • the data compression engine 180 retrieves or otherwise accepts compressed data blocks from one or more data storage devices and inputs the data via a data storage interface. It is to be understood that the system processes the input data stream in data blocks that may range in size from individual bits through complete files or collections of multiple files.
  • the input data block size may be fixed or variable.
  • the data decompression engine 180 comprises an input buffer 155 that receives as input an uncompressed or compressed data stream comprising one or more data blocks.
  • the data blocks may range in size from individual bits through complete files or collections of multiple files. Additionally, the data block size may be fixed or variable.
  • the input data buffer 55 is preferably included (not required) to provide storage of input data for various hardware implementations.
  • a descriptor extraction module 160 receives the buffered (or unbuffered) input data block and then parses, lexically, syntactically, or otherwise analyzes the input data block using methods known by those skilled in the art to extract the data compression type descriptor associated with the data block.
  • the data compression type descriptor may possess values corresponding to null (no encoding applied), a single applied encoding technique, or multiple encoding techniques applied in a specific or random order (in accordance with the data compression system embodiments and methods discussed above).
  • a decoder module 165 includes one or more decoders D 1 . . . Dn for decoding the input data block using a decoder, set of decoders, or a sequential set of decoders corresponding to the extracted compression type descriptor.
  • the decoders D 1 . . . Dn may include those lossless encoding techniques currently well known within the art, including: run length, Huffman, Lempel-Ziv Dictionary Compression, arithmetic coding, data compaction, and data null suppression. Decoding techniques are selected based upon their ability to effectively decode the various different types of encoded input data generated by the data compression systems described above or originating from any other desired source.
  • the decoder module 165 may include multiple decoders of the same type applied in parallel so as to reduce the data decoding time.
  • An output data buffer or cache 170 may be included for buffering the decoded data block output from the decoder module 165 .
  • the output buffer 70 then provides data to the output data stream.
  • the data compression system 180 may also include an input data counter and output data counter operatively coupled to the input and output, respectively, of the decoder module 165 . In this manner, the compressed and corresponding decompressed data block may be counted to ensure that sufficient decompression is obtained for the input data block.
  • the embodiment of the data decompression system 180 of FIG. 10 is exemplary of a preferred decompression system and method which may be implemented in the present invention, and that other data decompression systems and methods known to those skilled in the art may be employed for providing accelerated data retrieval in accordance with the teachings herein.
  • FIGS. 11 and 12 illustrate disk architectures according to additional embodiments of the present invention.
  • FIG. 11 and FIGS. 12 illustrate composite implementations of disk controller frameworks. Novel aspects of these architectures include, for example, the incorporation of a separate disk controller function and the addition of a data compression/decompression engine.
  • the disk controller architectures in FIGS. 11 and 12 essentially provide an interface directly from the disk to the host main bus. Any number of busses could be implemented such as PCI, PCMCIA, Pentium, VMEBUS, etc.
  • the disk controller framework illustrated in FIG. 11 comprises a disk controls and status module 1110 , a cache management and interface control module 1120 , a data cache 1130 , a compression/decompression engine 1140 , host interface busses 1150 , a local high-speed bus 1160 and a data and command cache 1170 .
  • the data and command cache 1170 is operatively connected to the host interface busses 1150 (via a host interface buffered data bus 80 ) and to the data compression/decompression engine 1140 via the local bus 1160 , to thereby allow data to be transferred to/from the host while the compression engine 1140 works on another buffered data block.
  • the architecture of FIG. 11 maximizes pipelining and produces a maximum throughput.
  • FIG. 12 is a block diagram of a disk controller according to another embodiment of the present invention, comprising a disk controls and status module 1110 , a cache management and interface control module 1120 , a data cache 1130 , a compression/decompression engine 1140 , host interface busses 1150 , and a local high-speed bus 1160 .
  • the architecture of FIG. 12 comprises a single buffer between the host and the compression engine 1140 and comprises a more cost effective architecture than that of FIG. 11, but with reduced throughput in certain applications.
  • the data cache 1130 is connected to the data compression/decompression engine 1140 and the actual disk, which enable overlap of disk operations with data storage operations.
  • the local high-speed bus 1160 in both architectures preferably operates primarily in block mode for optimal efficiency.
  • the cache management & interface control module 1120 which communicates with the compression engine 1140 over a dedicated secondary high-speed bus 1190 , controls the data flow through the disk system under commands from the compression/decompression engine 1140 .
  • This architecture allows data to flow from the disk and the host interface at the same time while the engine 1140 is operating on a separate block of data.
  • the data compression/decompression engine 1140 employs the compression/decompression methods described in the above-incorporated U.S. Pat. No. 6,195,024, issued Feb. 27, 2001 to J. Fallon, U.S. Pat. No. 6,309,424, issued on Oct. 30, 2001 to J. Fallon, and/or the techniques described in U.S. patent application Ser. No. 10/016,355, filed on Oct. 29, 2001, which are all commonly assigned and incorporated herein by reference.
  • DSP digital signal processor
  • DSP digital signal processor
  • the data compression and decompression functions to accomplish data storewidth acceleration and or storage multiplication may be accomplished in either hardware, software, or any combination thereof.
  • minimizing the cost of the data storage and maximizing retrieval storewidth acceleration and or storage multiplication function is preferably achieved by sharing hardware and or software resources.
  • FIG. 13 is a block diagram of a magnetic disk controller according to another embodiment of the present invention. It should be noted that although the exemplary embodiment of FIG. 13 describes a magnetic disk, the present invention is applicable to any mass storage device.
  • a magnetic disk implementation according to an embodiment of the present invention comprises a host computer interface 1300 coupled to a compression/decompression engine 1301 , a bi-directional cache 1302 , a command and status control module 1303 , a cache management/virtual file system 1304 and/or full host file system.
  • the system further comprises high performance Giant Magneto Resistive Heads 1305 , analog signal processing/data recognition module 1306 , a decoding and tracking module 1307 , a closed loop positioning module 1308 , multistage linear actuators 1309 for positioning, ramp load/unloading of heads, closed loop brushless DC motors 1310 with liquid bearings and associated drivers 1311 , and a power conversion and management system 1312 .
  • Additional functions comprise dynamic head calibrations, static head calibrations, dynamic calibration functions, static calibration functions, and corrections for time, temperature, aging, stress, and radiation, along with error detection and correction functions.
  • a DSP is utilized for storewidth acceleration and or storage multiplication, as well as other disk functions or control thereof as mentioned above.
  • the virtual file management system 1304 and/or cache system 1302 are implemented in the same DSP.
  • management of a bi-directional cache, separate read/write caches, and or compressed/uncompressed caches, or any combination thereof, is also managed by the DSP.
  • the disk command and control functions are further implemented in the DSP.
  • one or more of the following functions may be advantageously implemented in the DSP: data recognition or correlation, decoding and tracking, closed loop servo positioning, multistage linear actuator control for positioning, ramp load/unload management and control, closed loop brushless DC motor control, liquid bearing monitoring (temperature, fluid level), and power conversion and management system.
  • Additional functions comprise on the fly dynamic head calibrations with read/write testing, or with pre-stored patterns on the disk, static head calibrations (performed at construction or periodically), dynamic and static calibration functions performed periodically or by command, along with corrections for time, temperature, aging, stress, radiation, along with canonical error detection and correction functions.
  • the virtual file management system 1304 may be executed in an alternate processor, for example in the host computer, to offload the DSP or other disk processing for other data acceleration, bandwidth multiplication, and aforementioned disk functions.
  • the virtual file management system 1304 is utilized to map uncompressed/unaccelerated blocks to the disk when they are compressed. With the present invention, a compressed data block occupies the same or less space than the original data. As such, the file management system 1304 must be aware of the new data size in order to store data efficiently on the disk.
  • the virtual file management 1304 system allows the appropriate data to be stored or retrieved even when the actual data is different in size than the original uncompressed data. Embedding the virtual file management system 1304 within the mass storage device has the advantage of reducing costs by sharing the processing and virtual file management mapping tasks.
  • Virtual file management and data block mapping may be accomplished via look up tables or mathematical hashing functions.
  • the mapping or hashing function virtualizes the physical disk or mass storage space. Assuming a 3:1 compression ratio, a one terabyte physical disk appears as a three terabyte virtual disk.
  • the virtual file system 1304 allows uncompressed data in the three terabyte virtual space to be stored efficiently in the one terabyte physical space. Mapping data in small blocks has the advantage of being able to store, retrieve, or append with smaller more efficient units of data at the expense of larger look-up tables or more complex hashing functions.
  • cache management is employed to manage data caching in both the physical space to the virtual space.
  • Data retrieved from the mass storage device is stored compressed in a cache awaiting a cache hit.
  • physically adjacent data or data known to be frequently referenced within the context of the retrieved data is also read from disk.
  • Caches are typically uncompressed and thus require more memory and additional bandwidth for transfer.
  • the cache is capable of storing a significantly larger quantity of data, making the likelihood of cache hits better and thus increasing system performance. Data is then decompressed when called for or in the background when the disk or controller is idle.
  • the compressed data is stored in the cache awaiting synchronization with the mass storage disk or memory device.
  • the cache is capable of storing a much larger quantity of data (a function of compression ratio) and thus increases overall system performance.
  • any element of the above-mentioned disk functions may be implemented wholly or partially with the disk DSP(s), host processor(s), alternate processor(s), or any combination thereof.
  • the virtual file management system and the host operating system file management system are merged, with the results of the compression/decompression process utilized to minimize redundant disk management tasks.
  • This function may be resident within the disk, within the host(s), or any combination thereof.
  • the virtual file management system can consume significant processing resources, as such it may not always be optimal to embed the virtual file system within the mass storage device.
  • the processing can be resident in the host, thus allowing the disk processor to work on disk management and data acceleration tasks, split between the two, or wholly resident within the storage device.
  • the data acceleration is performed solely with the host.
  • the data acceleration may be advantageous to have the data acceleration solely within one or more host CPUs.
  • the CPU(s) can share workload with other functions, such as network interfacing and application processing.
  • the virtual file system can also be allocated to one or more of the same CPUs or it can be performed within the mass storage or disk device.
  • the DSP utilized for the data storewidth acceleration or storage multiplication is also utilized to perform the monitoring and actuation functions for a bearing fluid replenishment system as described below.
  • the monitoring and actuation functions for the bearing fluid replenishment system may be performed in a separate processor, DSP, one or a plurality of general purpose processors, finite state machines, micro code, logic, firmware, or software—in addition the control function may be implemented in the host computer.
  • a bearing fluid replenishment system is utilized with a bearing fluid reservoir to extend the life of the bearing system.
  • An actuator is utilized to fill the fluid to a constant level.
  • the fluid level or pressure within the system is maintained at a constant level.
  • the pressure is preferably maintained a constant level to provide minimum frictional losses while still isolating the rotating parts from contact.
  • the pressure and or fluid level is adjusted to optimum as a function of spin rate.
  • the fluid level or pressure is adjusted to optimum as a function of temperature.
  • the fluid level and/or pressure is adjusted according to closed loop feedback from the motor current or power consumption to an optimal level.
  • any combination of the above parameters are utilized in optimal combination to achieve lowest wear, longest life, highest reliability, minimum breakaway friction, minimum frictional losses, lowest power consumption, etc.
  • Moving fluid from the reservoir to the bearing chamber and/or back is accomplished by any means including piezo actuators, expandable/compressible diaphragms, mechanical actuators, electromagnetic actuators, gas pressure by heat, or any other means.

Abstract

Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a Continuation-in-Part of U.S. patent application Ser. No. 09/775,905, filed Feb. 2, 2001, which claims priority to U.S. Provisional Application Serial No. 60/180,114, filed on Feb. 3, 2000, which are fully incorporated herein by reference. In addition, this application claims priority to U.S. Provisional Application Serial No. 60/333,919, filed on Nov. 28, 2001, which is fully incorporated herein by reference.[0001]
  • TECHNICAL FIELD
  • The present invention relates generally to systems and methods for data storage and retrieval and, more particularly, to data storage controllers employing lossless and/or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. [0002]
  • BACKGROUND
  • Modern computers utilize a hierarchy of memory devices. To achieve maximum performance levels, modern processors utilize onboard memory and on board cache to obtain high bandwidth access to both program and data. Limitations in process technologies currently prohibit placing a sufficient quantity of onboard memory for most applications. Thus, in order to offer sufficient memory for the operating system(s), application programs, and user data, computers often use various forms of popular off-processor high speed memory including static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous burst static ram (SBSRAM). Due to the prohibitive cost of the high-speed random access memory, coupled with their power volatility, a third lower level of the hierarchy exists for non-volatile mass storage devices. [0003]
  • Furthermore, mass storage devices offer increased capacity and fairly economical data storage. Mass storage devices (such as a “hard disk”) typically store the operating system of a computer system, as well as applications and data and rapid access to such data is critical to system performance. The data storage and retrieval bandwidth of mass storage devices, however, is typically much less as compared with the bandwidth of other elements of a computing system. Indeed, over the last decade, although computer processor performance has improved by at least a factor of 50, magnetic disk storage performance has only improved by a factor of 5. Consequently, memory storage devices severely limit the performance of consumer, entertainment, office, workstation, servers, and mainframe computers for all disk and memory intensive operations. [0004]
  • The explosion in the data storage market will require both an increase in disk densities as well as a reduction in overall size. This latter aspect, ongoing computer miniaturization will not only affect disk architectures but will create pressure to merge current individual functions into more optimized composite implementations. [0005]
  • The ubiquitous Internet combined with new multimedia applications has put tremendous emphasis on storage volumetric density, storage mass density, storewidth, and power consumption. Specifically, storage density is limited by the number of bits that are encoded in a mass storage device per unit volume. Similarly mass density is defined as storage bits per unit mass. Storewidth is the data rate at which the data may be accessed. There are various ways of categorizing storewidth in terms, several of the more prevalent metrics include sustained continuous storewidth, burst storewidth, and random access storewidth, all typically measured in megabytes/sec. Power consumption is canonically defined in terms of power consumption per bit and may be specified under a number of operating modes including active (while data is being accessed and transmitted) and standby mode. Hence one fairly obvious limitation within the current art is the need for even more volume, mass, and power efficient data storage. [0006]
  • Magnetic disk mass storage devices currently employed in a variety of home, business, and scientific computing applications suffer from significant seek-time access delays along with profound read/write data rate limitations. Currently the fastest available disk drives support only a sustained output data rate in the tens of megabytes per second data rate (MB/sec). This is in stark contrast to the modern Personal Computer's Peripheral Component Interconnect (PCI) Bus's [0007] low end 32 bit/33 Mhz input/output capability of 264 MB/sec and the PC's internal local bus capability of 800 MB/sec.
  • Another problem within the current art is that emergent high performance disk interface standards such as the Small Computer Systems Interface (SCSI-3), Fibre Channel, AT Attachment UltraDMA/66/100, Serial Storage Architecture, and Universal Serial Bus offer only higher data transfer rates through intermediate data buffering in random access memory. These interconnect strategies do not address the fundamental problem that all modern magnetic disk storage devices for the personal computer marketplace are still limited by the same typical physical media restrictions. In practice, faster disk access data rates are only achieved by the high cost solution of simultaneously accessing multiple disk drives with a technique known within the art as data striping and redundant array of independent disks (RAID). [0008]
  • RAID systems often afford the user the benefit of increased data bandwidth for data storage and retrieval. By simultaneously accessing two or more disk drives, data bandwidth may be increased at a maximum rate that is linear and directly proportional to the number of disks employed. Thus another problem with modern data storage systems utilizing RAID systems is that a linear increase in data bandwidth requires a proportional number of added disk storage devices. [0009]
  • Another problem with most modern mass storage devices is their inherent unreliability. Many modern mass storage devices utilize rotating assemblies and other types of electromechanical components that possess failure rates one or more orders of magnitude higher than equivalent solid-state devices. RAID systems employ data redundancy distributed across multiple disks to enhance data storage and retrieval reliability. In the simplest case, data may be explicitly repeated on multiple places on a single disk drive, on multiple places on two or more independent disk drives. More complex techniques are also employed that support various trade-offs between data bandwidth and data reliability. [0010]
  • Standard types of RAID systems currently available include [0011] RAID Levels 0, 1, and 5. The configuration selected depends on the goals to be achieved. Specifically data reliability, data validation, data storage/retrieval bandwidth, and cost all play a role in defining the appropriate RAID data storage solution. RAID level 0 entails pure data striping across multiple disk drives. This increases data bandwidth at best linearly with the number of disk drives utilized. Data reliability and validation capability are decreased. A failure of a single drive results in a complete loss of all data. Thus another problem with RAID systems is that low cost improved bandwidth requires a significant decrease in reliability.
  • [0012] RAID Level 1 utilizes disk mirroring where data is duplicated on an independent disk subsystem. Validation of data amongst the two independent drives is possible if the data is simultaneously accessed on both disks and subsequently compared. This tends to decrease data bandwidth from even that of a single comparable disk drive. In systems that offer hot swap capability, the failed drive is removed and a replacement drive is inserted. The data on the failed drive is then copied in the background while the entire system continues to operate in a performance degraded but fully operational mode. Once the data rebuild is complete, normal operation resumes. Hence, another problem with RAID systems is the high cost of increased reliability and associated decrease in performance.
  • RAID Level 5 employs disk data striping and parity error detection to increase both data bandwidth and reliability simultaneously. A minimum of three disk drives is required for this technique. In the event of a single disk drive failure, that drive may be rebuilt from parity and other data encoded on disk remaining disk drives. In systems that offer hot swap capability, the failed drive is removed and a replacement drive is inserted. The data on the failed drive is then rebuilt in the background while the entire system continues to operate in a performance degraded but fully operational mode. Once the data rebuild is complete, normal operation resumes. [0013]
  • Thus another problem with redundant modern mass storage devices is the degradation of data bandwidth when a storage device fails. Additional problems with bandwidth limitations and reliability similarly occur within the art by all other forms of sequential, pseudo-random, and random access mass storage devices. These and other limitations within the current art are addressed by the present invention. [0014]
  • SUMMARY OF THE INVENTION
  • The present invention is generally directed to data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration. [0015]
  • More particularly, in one aspect of the invention, a controller for controlling storage and retrieval of data to and from a data storage device comprises a data compression/decompression engine for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device, a first cache, operatively connected to the storage device and the data compression/decompression engine, for temporary storage of (i) compressed data that is read from the data storage device and (ii) compressed data from the data compression/decompression engine that is to be written to the data storage device, a second cache, operatively connected to the data compression/decompression engine and to a host interface bus, for temporary storage of (i) data that is received from a host system over the host interface bus for compression and storage and (ii) data that is to be sent to the host system over the host interface bus, and a cache manager for controlling the first and second data caches under commands received from the data compression/decompression engine. [0016]
  • In another aspect, the first cache, second cache and the data compression/decompression engine are operatively connected by a first local bus and the data compression/decompression engine is connected to the cache manager over a dedicated bus. [0017]
  • In another aspect of the invention, a magnetic disk controller for controlling storage and retrieval of data to and from a magnetic disk comprises an embedded data compression/decompression engine for compressing data stored to the magnetic disk and for decompressing data retrieved from the magnetic disk, an embedded first cache, operatively connected to the magnetic disk and the data compression/decompression engine, for temporary storage of (i) compressed data that is read from the magnetic disk and (ii) compressed data from the data compression/decompression engine that is to be written to the magnetic disk, an embedded second cache, operatively connected to the data compression/decompression engine and to a host interface bus, for temporary storage of (i) data that is received from a host system over the host interface bus for compression and storage and (ii) data that is to be sent to the host system over the host interface bus, and an embedded cache manager for controlling the first and second data caches under commands received from the data compression/decompression engine. [0018]
  • In yet another aspect of the invention, a magnetic disk controller for controlling storage and retrieval of data to and from a magnetic disk comprises an embedded data compression/decompression engine for compressing data stored to the magnetic disk and for decompressing data retrieved from the magnetic disk, an embedded bi-directional cache for temporary storage of (i) compressed data that is read from the magnetic disk and (ii) compressed data from the data compression/decompression engine that is to be written to the magnetic disk, an embedded cache manager for controlling the bi-directional cache, and an embedded virtual file management system for mapping compressed data blocks stored on the disk to corresponding uncompressed data blocks. [0019]
  • The present invention is realized due to recent improvements in processing speed, inclusive of dedicated analog and digital hardware circuits, central processing units, (and any hybrid combinations thereof), that, coupled with advanced data compression and decompression algorithms are enabling of ultra high bandwidth data compression and decompression methods that enable improved data storage and retrieval bandwidth [0020]
  • These and other aspects, features and advantages, of the present invention will become apparent from the following detailed description of preferred embodiments that is to be read in connection with the accompanying drawings.[0021]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of a data storage controller according to one embodiment of the present invention. [0022]
  • FIG. 2 is a block diagram of a data storage controller according to another embodiment of the present invention. [0023]
  • FIG. 3 is a block diagram of a data storage controller according to another embodiment of the present invention. [0024]
  • FIG. 4 is a block diagram of a data storage controller according to another embodiment of the present invention. [0025]
  • FIG. 5 is a block diagram of a data storage controller according to another embodiment of the present invention. [0026]
  • FIGS. 6[0027] a and 6 b comprise a flow diagram of a method for initializing a data storage controller according to one aspect of the present invention.
  • FIGS. 7[0028] a and 7 b comprise a flow diagram of a method for providing accelerated loading of an operating system and/or application programs upon system boot, according to one aspect of the present invention.
  • FIGS. 8[0029] a and 8 b comprise a flow diagram of a method for providing accelerated loading of application programs according to one aspect of the present invention.
  • FIG. 9 is a diagram of an exemplary data compression system that may be employed in a data storage controller according to the present invention. [0030]
  • FIG. 10 is a diagram of an exemplary data decompression system that may be employed in a data storage controller according to the present invention. [0031]
  • FIG. 11 is a block diagram of a data storage controller according to another embodiment of the present invention. [0032]
  • FIG. 12 is a block diagram of a data storage controller according to another embodiment of the present invention. [0033]
  • FIG. 13 is a block diagram of a data storage device comprising an embedded data storage accelerator, according to an embodiment of the present invention.[0034]
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • In the following description, it is to be understood that system elements having equivalent or similar functionality are designated with the same reference numerals in the Figures. It is to be further understood that the present invention may be implemented in various forms of hardware, software, firmware, or a combination thereof. Preferably, the present invention is implemented on a computer platform including hardware such as one or more central processing units (CPU) or digital signal processors (DSP), a random access memory (RAM), and input/output (I/O) interface(s). The computer platform may also include an operating system, microinstruction code, and dedicated processing hardware utilizing combinatorial logic or finite state machines. The various processes and functions described herein may be either part of the hardware, microinstruction code or application programs that are executed via the operating system, or any combination thereof. [0035]
  • It is to be further understood that, because some of the constituent system components described herein are preferably implemented as software modules, the actual system connections shown in the Figures may differ depending upon the manner in that the systems are programmed. It is to be appreciated that special purpose microprocessors, dedicated hardware, or and combination thereof may be employed to implement the present invention. Given the teachings herein, one of ordinary skill in the related art will be able to contemplate these and similar implementations or configurations of the present invention. [0036]
  • I. System Architectures [0037]
  • The present invention is directed to data storage controllers that provide increased data storage/retrieval rates that are not otherwise achievable using conventional disk controller systems and protocols to store/retrieve data to/from mass storage devices. The concept of “accelerated” data storage and retrieval was introduced in copending U.S. patent application Ser. No. 09/266,394, filed March 11, 1999, entitled “System and Methods For Accelerated Data Storage and Retrieval” and copending U.S. patent application Ser. No. 09/481,243, filed Jan. 11, 2000, entitled “System and Methods For Accelerated Data Storage and Retrieval,” both of which are commonly assigned and incorporated herein by reference. In general, as described in the above-incorporated applications, “accelerated” data storage comprises receiving a digital data stream at a data transmission rate which is greater that the data storage rate of a target storage device, compressing the input stream at a compression rate that increases the effective data storage rate of the target storage device and storing the compressed data in the target storage device. For instance, assume that a mass storage device (such as a hard disk) has a data storage rate of 20 megabytes per second. If a storage controller for the mass storage device is capable of compressing an input data stream with an average compression rate of 3:1, then data can be stored in the mass storage device at a rate of 60 megabytes per second, thereby effectively increasing the storage bandwidth (“storewidth”) of the mass storage device by a factor of three. Similarly, accelerated data retrieval comprises retrieving a compressed digital data stream from a target storage device at the rate equal to, e.g., the data access rate of the target storage device and then decompressing the compressed data at a rate that increases the effective data access rate of the target storage device. Advantageously, accelerated data storage/retrieval mitigates the traditional bottleneck associated with, e.g., local and network disk accesses. [0038]
  • Referring now to FIG. 1, a high-level block diagram illustrates a [0039] data storage controller 10 according to one embodiment of the present invention. The data storage controller 10 comprises a data compression engine 12 for compressing/decompressing data (preferably in real-time or psuedo real-time) stored/retrieved from a hard disk 11 (or any other type of mass storage device) to provide accelerated data storage/retrieval. The DCE 12 preferably employs the data compression/decompression techniques disclosed in U.S. Pat. No. 6,195,024, issued on Feb. 27, 2001, entitled “Content Independent Data Compression Method and System,” which is commonly assigned and which is fully incorporated herein by reference. It is to be appreciated that the compression and decompression systems and methods disclosed in U.S. Pat. No. 6,195,024 are suitable for compressing and decompressing data at rates, which provide accelerated data storage and retrieval. A detailed discussion of a preferred “content independent” data compression process will be provided below.
  • The [0040] data storage controller 10 further comprises a cache 13, a disk interface (or disk controller) 14 and a bus interface 15. The storage controller 10 is operatively connected to the hard disk 12 via the disk controller 14 and operatively connected to an expansion bus (or main bus) 16 of a computer system via the bus interface 15. The disk interface 14 may employ a known disk interface standard such as UltraDMA, SCSI, Serial Storage Architecture, FibreChannel or any other interface that provides suitable disk access data rates. In addition, the storage controller 10 preferably utilizes the American National Standard for Information Systems (ANSI) AT Attachment Interface (ATA/ATAPI-4) to connect the data storage controller 10 to the hard disk 12. As is known in the art, this standard defines the connectors and cables for the physical interconnects between the data storage controller and the storage devices, along with the electrical and logical characteristics of the interconnecting signals.
  • Further, the [0041] bus interface 15 may employ a known standard such as the PCI (Peripheral Component Interconnect) bus interface for interfacing with a computer system. The use of industry standard interfaces and protocols is preferable, as it allows the storage controller 10 to be backwards compatible and seamlessly integrated with current systems. However in new designs the present invention may be utilize any suitable computer interface or combination thereof.
  • It is to be understood that although FIG. 1 illustrates a [0042] hard disk 12, the storage controller 10 may be employed with any form of memory device including all forms of sequential, pseudo-random, and random access storage devices. Storage devices as known within the current art include all forms of random access memory, magnetic and optical tape, magnetic and optical disks, along with various other forms of solid-state mass storage devices. The current invention applies to all forms and manners of memory devices including, but not limited to, storage devices utilizing magnetic, optical, and chemical techniques, or any combination thereof. In addition, the cache 13 may comprise volatile or non-volatile memory, or any combination thereof. Preferably, the cache 13 is implemented in SDRAM (static dynamic random access memory).
  • The system of FIG. 1 generally operates as follows. When data is read from disk by the host computer, data flows from the [0043] disk 11 through the data storage controller 10 to the host computer. Data is stored in one of several proprietary compression formats on the disk 11 (e.g., “content independent” data compression). Data blocks are pre-specified in length, comprised of single or multiple sectors, and are typically handled in fractional or whole equivalents of tracks, e.g. ½ track, whole track, multiple tracks, etc. To read disk data, a DMA transfer is setup from the disk interface 14 to the onboard cache memory 13. The disk interface 14 comprises integral DMA control to allow transfer of data from the disk 11 directly to the onboard cache 13 without intervention by the DCE 12. It should be noted that the DCE 12 acts as a system level controller and sets-up specific registers within both the disk interface 14 and bus interface 15 to facilitate DMA transfers to and from the cache memory 13. To initiate a transfer from the disk 11 to the cache 13, the DMA transfer is setup via specifying the appropriate command (read disk), the source address (disk logical block number), amount of data to be transferred (number of disk logical blocks), and destination address within the onboard cache memory 13.
  • Then, a disk data interrupt signal (“DISKINT#”) is cleared (if previously set and not cleared) and the command is initiated by writing to the appropriate address space. Once data has been read from [0044] disk 11 and placed into onboard cache memory 13, the DISKINT# interrupt is asserted notifying the DCE 12 that requested data is now available in the cache memory 13. Data is then read by the DMA controller within the DCE 12 and placed into local memory for subsequent decompression. The decompressed data is then DMA transferred from the local memory of the DCE 12 back to the cache memory 13.
  • Finally, data is DMA transferred via the [0045] bus interface controller 15 from the cache memory 13 to the bus 16. It is to be understood that in the read mode, the data storage controller acts as a bus master. A bus DMA transfer is then setup via specifying the appropriate command (write to host computer), the source address within the cache memory 13, the quantity of data words to be transferred (transfers are preferably in 4 byte increments), and the destination address on the host computer. When a bus 16 read or write transaction has completed, the appropriate interrupt signals (respectively referred to as PCIRDINT# and PCIWRINT#) are asserted to the DCE 12. Either of these interrupts are cleared by a corresponding interrupt service routines through a read or write to the appropriate address of the DCE 12.
  • Similarly, when data is written to the [0046] disk 11 from the host computer, data flows from the host computer through the data storage controller 10 and onto disk 11. Data is normally received from the host computer in uncompressed (raw) format and is compressed by the DCE 12 and stored on the disk 11. Data blocks from the host are pre-specified in length and are typically handled in blocks that are a fixed multiplier higher than fractional or whole equivalents of tracks, e.g. ½ track, whole track, multiple tracks, etc. This multiplier is preferably derived from the expected average compression ratio that is selected when the disk is formatted with the virtual file management system. To read host computer data, a bus DMA transfer is setup from the host bus 16 to the onboard cache memory 13. The bus interface controller 15 comprises integral DMA control that allows large block transfers from the host computer directly to the onboard cache 13 without intervention by the DCE 12. The bus interface controller 15 acts as a host computer Bus Master when executing such transfer. Once data has been read from the host and placed into onboard cache memory 13, the data is read by the onboard DMA controller (residing on the DCE 12) and placed into local memory for subsequent compression. The compressed data is then DMA transferred from the local memory of the DCE 12 back to the cache memory 13. Finally, data is DMA transferred via the disk controller 14 from the cache 13 to the disk 11.
  • As discussed in greater detail below, upon host computer power-up or external user reset, the [0047] data storage controller 10 initializes the onboard interfaces 14, 5 prior to release of the external host bus 16 from reset. The processor of the host computer then requests initial data from the disk 11 to facilitate the computer's boot-up sequence. The host computer requests disk data over the Bus 16 via a command packet issued from the host computer. Command packets are preferably eight words long (in a preferred embodiment, each word comprises 32 bits). Commands are written from the host computer to the data storage controller 10 with the host computer as the Bus Master and the data storage controller 10 as the slave. The data storage controller 10 includes at least one Base Address Register (BAR) for decoding the address of a command queue of the data storage controller 10. The command queue resides within the cache 13 or within onboard memory of the DCE 12.
  • When a command is received from the host computer, an interrupt (referred to herein as PCICMDINT#) is generated to the DCE processor. The eight-word command is read by the [0048] DCE 12 and placed into the command queue. Because the commands occupy a very small amount of memory, the location of the command queue is at the discretion of software and the associated system level performance considerations. Commands may be moved from the bus interface 16 to the command queue by wither explicit reads and writes by the DCE processor or, as explained below, by utilizing programmed DMA from an Enhanced DMA Controller (EDMA) residing on the DCE 12. This second technique may better facilitate system throughput by allowing the EDMA to automatically load commands while the highly pipelined data compression and decompression processing in the DCE is executed fully undisturbed.
  • The [0049] DCE 12, disk interface 14 and bus interface 15 commonly share the cache 13. As explained in detail below, the storage controller 10 preferably provides maximum system bandwidth by allowing simultaneous data transfers between the disk 12 and cache 13, the DCE 12 and the cache 13, and the expansion bus 16 and the cache 13. This is realized by employing an integral DMA (direct memory access) protocol that allows the DCE 12, disk interface 14 and bus interface 15 to transfer data without interrupting or interfering with other ongoing processes. In particular, as explained in detail below, an integral bandwidth allocation controller (or arbitrator) is preferably employed to allow the DCE 12, disk controller 14, and bus interface 15 to access the onboard cache with a bandwidth proportional to the overall bandwidth of the respective interface or processing element. The bandwidth arbitration occurs transparently and does not introduce latency in memory accesses. Bandwidth division is preferably performed with a high degree of granularity to minimize the size of requisite onboard buffers to synchronize data from the disk interface 14 and bus interface 15.
  • It is to be appreciated that the implementation of a storage controller according to the present invention significantly accelerates the performance of a computer system and significantly increases hard disk data storage capacity. For instance, depending on the compression rate, for personal computers running standard Microsoft Windows® based business application software, the storage controller provides: (1) an increase of n: 1 in disk storage capacity(for example, assuming a compression ration of 3:1, a 20 gigabyte hard drive effectively becomes a 60 gigabyte hard drive) (2) a significant decrease in the computer boot-up time (turn-on and operating system load) and the time for loading application software and (3) User data storage and retrieval is increased by a factor of n:1. [0050]
  • Referring now to FIG. 2, a block diagram illustrates a [0051] data storage controller 20 according to another embodiment of the present invention. More specifically, FIG. 2 illustrates a PCB (printed circuit board) implementation of the data storage controller 10 of FIG. 1. The storage controller 20 comprises a DSP (digital signal processor) 21 (or any other micro-processor device) that implements the DCE 12 of FIG. 1. The storage controller 21 further comprises at least one programmable logic device 22 (or volatile logic device). The programmable logic device 22 preferably implements the logic (program code) for instantiating and driving both the disk interface 14 and the bus interface 15 and for providing full DMA capability for the disk and bus interfaces 14, 15. Further, as explained in detail below, upon host computer power-up and/or assertion of a system-level “reset” (e.g., PCI Bus reset), the DSP 21 initializes and programs the programmable logic device 22 before of the completion of initialization of the host computer. This advantageously allows the data storage controller 20 to be ready to accept and process commands from the host computer (via the bus 16) and retrieve boot data from the disk (assuming the data storage controller 20 is implemented as the boot device and the hard disk stores the boot data (e.g., operating system, etc.)).
  • The [0052] data storage controller 20 further comprises a plurality of memory devices including a RAM (random access memory) device 23 and a ROM (read only memory) device 24 (or FLASH memory or other types of non-volatile memory). The RAM device 23 is utilized as on-board cache and is preferably implemented as SDRAM (preferably, 32 megabytes minimum). The ROM device 24 is utilized for non-volatile storage of logic code associated with the DSP 21 and configuration data used by the DSP 21 to program the programmable logic device 22. The ROM device 24 preferably comprises a one time (erasable) programmable memory (OTP-EPROM) device.
  • The [0053] DSP 21 is operatively connected to the memory devices 23, 24 and the programmable logic device 22 via a local bus 25. The DSP 21 is also operatively connected to the programmable logic device 22 via an independent control bus 26. The programmable logic device 22 provides data flow control between the DSP 21 and the host computer system attached to the bus 16, as well as data flow control between the DSP 21 and the storage device. A plurality of external I/O ports 27 are included for data transmission and/or loading of one programmable logic devices. Preferably, the disk interface 14 driven by the programmable logic device 22 supports a plurality of hard drives.
  • The [0054] storage controller 20 further comprises computer reset and power up circuitry 28 (or “boot configuration circuit”) for controlling initialization (either cold or warm boots) of the host computer system and storage controller 20. A preferred boot configuration circuit and preferred computer initialization systems and protocols are described in U.S. patent application Ser. No. 09/775,897, filed on Feb. 2, 2001, entitled “Systems and Methods for Computer Initialization”, which is commonly assigned and incorporated herein by reference. Preferably, the boot configuration circuit 28 is employed for controlling the initializing and programming the programmable logic device 22 during configuration of the host computer system (i.e., while the CPU of the host is held in reset). The boot configuration circuit 28 ensures that the programmable logic device 22 (and possibly other volatile or partially volatile logic devices) is initialized and programmed before the bus 16 (such as a PCI bus) is fully reset.
  • In particular, when power is first applied to the [0055] boot configuration circuit 28, the boot configuration circuit 28 generates a control signal to reset the local system (e.g., storage controller 20) devices such as a DSP, memory, and I/O interfaces. Once the local system is powered-up and reset, the controlling device (such as the DSP 21) will then proceed to automatically determine the system environment and configure the local system to work within that environment. By way of example, the DSP 21 of the disk storage controller 20 would sense that the data storage controller 20 is on a PCI computer bus (expansion bus) and has attached to it a hard disk on an IDE interface. The DSP 21 would then load the appropriate PCI and IDE interfaces into the programmable logic device 22 prior to completion of the host system reset. It is to be appreciated that this can be done for all computer busses and boot device interfaces including: PCI, NuBus, ISA, Fiber Channel, SCSI, Ethernet, DSL, ADSL, IDE, DMA, Ultra DMA, and SONET. Once the programmable logic device 22 is configured for its environment, the boot device controller is reset and ready to accept commands over the computer/expansion bus 16. Details of the boot process using a boot device comprising a programmable logic device will be provided below.
  • It is to be understood that the [0056] data storage controller 20 may be utilized as a controller for transmitting data (compressed or uncompressed) to and from remote locations over the DSP I/O ports 27 or system bus 16, for example. Indeed, the I/O ports 27 of the DSP 21 may be used for transmitting data (compressed or uncompressed) that is either retrieved from the disk 11 or received from the host system via the bus 16, to remote locations for processing and/or storage. Indeed, the I/O ports may be operatively connected to other data storage controllers or to a network communication channels. Likewise, the data storage controller 20 may receive data (compressed or uncompressed) over the I/O ports 27 of the DSP 21 from remote systems that are connected to the I/O ports 27 of the DSP, for local processing by the data storage controller 20. For instance, a remote system may remotely access the data storage controller (via the I/O ports of the DSP or system bus 16) to utilize the data compression, in which case the data storage controller would transmit the compressed data back to the system that requested compression.
  • The [0057] DSP 21 may comprise any suitable commercially available DSP or processor. Preferably, the data storage controller 20 utilizes a DSP from Texas Instruments' 320 series, C62x family, of DSPs (such as TMS320C6211GFN-150), although any other DSP or processor comprising a similar architecture and providing similar functionalities may be employed. The preferred DSP is capable of up to 1.2 billion instructions per second. Additional features of the preferred DSP include a highly parallel eight processor single cycle instruction execution, onboard 4K byte LIP Program Cache, 4K LID Data Cache, and 64K byte Unified L2 Program/Data Cache. The preferred DSP further comprises a 32 bit External Memory Interface (EMIF) that provides for a glueless interface to the RAM 23 and the non-volatile memory 24 (ROM). The DSP further comprises two multi-channel buffered serial ports (McBSPs) and two 32 bit general purpose timers. Preferably, the storage controller disables the I/O capability of these devices and utilizes the I/O ports of the DSP as general purpose I/O for both programming the programmable logic device 22 using a strobed eight bit interface and signaling via a Light Emitting Diode (LED). Ancillary DSP features include a 16 bit Host Port Interface and full JTAG emulation capability for development support. The programmable logic device 22 may comprise any form of volatile or non-volatile memory. Preferably, the programmable logic device 22 comprises a dynamically reprogrammable FPGA (field programmable gate array) such as the commercially available Xilinx Spartan Series XCS40XL-PQ240-5 FPGA. As discussed in detail herein, the FPGA instantiates and drives the disk and bus interfaces 14, 15. The non-volatile memory device 24 preferably comprises a 128 Kbyte M27W101-80K one time (erasable) programmable read only memory, although other suitable non-volatile storage devices may be employed. The non-volatile memory device 24 is decoded at a designated memory space in the DSP 21. The non-volatile memory device 24 stores the logic for the DSP 21 and configuration data for the programmable logic device 22. More specifically, in a preferred embodiment, the lower 80 Kbytes of the non-volatile memory device 24 are utilized for storing DSP program code, wherein the first 1 k bytes are utilized for the DSP's boot loader. Upon reset of the DSP 21 (via boot configuration circuit 28), the first 1 K of memory of the non-volatile memory device 24 is copied into an internal RAM of the DSP 21 by e.g., the DSP's Enhanced DMA Controller (EDMA). Although the boot process begins when the CPU of the host system is released from external reset, the transfer of the boot code into the DSP and the DSP's initialization of the programmable logic device actually occurs while the CPU of the host system is held in reset. After completion of the 1K block transfer, the DSP executes the boot loader code and continues thereafter with executing the remainder of the code in non-volatile memory device to program the programmable logic device 22.
  • More specifically, in a preferred embodiment, the upper 48K bytes of the [0058] non-volatile memory device 24 are utilized for storing configuration data associated with the programmable logic device 22. If the data storage controller 20 is employed as the primary boot storage device for the host computer, the logic for instantiating and driving the disk and bus interfaces 14, 15 should be stored on the data storage controller 20 (although such code may be stored in remotely accessible memory locations) and loaded prior to release of the host system bus 16 from “reset”. For instance, revision 2.2 of the PCI Local Bus specification calls for a typical delay of 100 msec from power-stable before release of PCI Reset. In practice this delay is currently 200 msec although this varies amongst computer manufacturers. A detailed discussion of the power-on sequencing and boot operation of the data storage controller 20 will be provided below.
  • FIG. 3 illustrates another embodiment of a data storage controller [0059] 30 wherein the data storage controller 35 is embedded within the motherboard of the host computer system. This architecture provides the same functionality as the system of FIG. 2, and also adds the cost advantage of being embedded on the host motherboard. The system comprises additional RAM and ROM memory devices 23 a, 24 a, operatively connected to the DSP 21 via a local bus 25 a.
  • FIG. 4 illustrates another embodiment of a data storage controller. The [0060] data storage controller 40 comprises a PCB implementation that is capable of supporting RAID levels 0, 1 and 5. This architecture is similar to those of FIGS. 1 and 2, except that a plurality of programmable logic devices 22, 22 a are utilized. The programmable logic device 22 is dedicated to controlling the bus interface 15. The programmable logic device 22 a is dedicated to controlling a plurality of disk interfaces 14, preferably three interfaces. Each disk interface 14 can connect up to two drives. The DSP in conjunction with the programmable logic device 22 a can operate at RAID level 0, 1 or 5. At RAID level 0, which is disk striping, two interfaces are required. This is also true for RAID level 1, which is disk mirroring. At RAID level 5, all three interfaces are required.
  • FIG. 5 illustrates another embodiment of a data storage controller according to the present invention. The data storage controller [0061] 45 provides the same functionality as that of FIG. 4, and has the cost advantage of being embedded within the computer system motherboard.
  • II. Initializing A Programmable Logic Device [0062]
  • As discussed above with reference to FIG. 2, for example, the [0063] data storage controller 20 preferably employs an onboard Texas Instruments TMS320C6211 Digital Signal Processor (DSP) to program the onboard Xilinx Spartan Series XCS40XL FPGA upon power-up or system level PCI reset. The onboard boot configuration circuit 28 ensures that from system power-up and/or the assertion of a bus reset (e.g., PCI reset), the DSP 21 is allotted a predetermined amount of time (preferably a minimum of 10 msec) to boot the DSP 21 and load the programmable logic device 22. Because of a potential race condition between either the host computer power-up or assertion of PCI Bus reset and configuration of the programmable logic device 20 (which is used for controlling the boot device and accepting PCI Commands), an “Express Mode” programming mode for configuring the SpartanXL family XCS40XL device is preferably employed. The XCS40XL is factory set to byte-wide Express-Mode programming by setting both the M1/M0 bits of the XCS40XL to 0x0. Further, to accommodate express mode programming of the programmable logic device 22, the DSP 21 is programmed to utilize its serial ports reconfigured as general purpose I/O. However, after the logic device 22 is programmed, the DSP 21 may then reconfigure its serial ports for use with other devices. Advantageously, using the same DSP ports for multiple purposes affords greater flexibility while minimizing hardware resources and thus reducing product cost.
  • The volatile nature of the [0064] logic device 22 effectively affords the ability to have an unlimited number of hardware interfaces. Any number of programs for execution by the programmable logic device 22 can be kept in an accessible memory location (EPROM, hard disk, or other storage device). Each program can contain new disk interfaces, interface modes or subsets thereof. When necessary, the DSP 21 can clear the interface currently residing in the logic device 22 and reprogram it with a new interface. This feature allows the data storage controller 20 to have compatibility with a large number of interfaces while minimizing hardware resources and thus reducing product cost.
  • A preferred protocol for programming the programmable logic device can be summarized in the following steps: (1) Clearing the configuration memory; (2) Initialization; (3) Configuration; and (4) Start-Up. When either of three events occur: the host computer is first powered-up or a power failure and subsequent recovery occurs (cold boot), or a front panel computer reset is initiated (warm boot), the host computer asserts RST# (reset) on the PCI Bus. As noted above, the [0065] data storage controller 20 preferably comprises a boot configuration circuit 28 that senses initial host computer power turn-on and/or assertion of a PCI Bus Reset (“PCI RST#”). It is important to note that assuming the data storage controller 20 is utilized in the computer boot-up sequence, it should be available exactly 5 clock cycles after the PCI RST# is deasserted, as per PCI Bus Specification Revision 2.2. While exact timings vary from computer to computer, the typical PCI bus reset is asserted for approximately 200 msec from initial power turn-on.
  • In general, PCI RST# is asserted as soon as the computer's power exceeds a nominal threshold of about 1 volt (although this varies) and remains asserted for 200 msec thereafter. Power failure detection of the 5 volt or 3.3 volt bus typically resets the entire computer as if it is an initial power-up event (i.e., cold boot). Front panel resets (warm boots) are more troublesome and are derived from a debounced push-button switch input. [0066]
  • Typical front panel reset times are a minimum of 20 msec, although again the only governing specification limit is 1 msec reset pulse width. [0067]
  • As discussed in detail below, it may not be necessary to reload the [0068] programmable logic device 22 each time the DSP is reset. The boot configuration circuit 20 preferably comprises a state machine output signal that is readable by the DSP 21 to ascertain the type of boot process requested. For example, with a front-panel reset (warm boot), the power remains stable on the PCI Bus, thus the programmable logic device 22 should not require reloading.
  • Referring now to FIG. 6, a flow diagram illustrates a method for initializing the [0069] programmable logic device 22 according to one aspect of the invention. In the following discussion, it is assumed that the programmable logic device 22 is always reloaded, regardless of the type of boot process. Initially, in FIG. 6a, the DSP 21 is reset by asserting a DSP reset signal (step 50). Preferably, the DSP reset signal is generated by the boot circuit configuration circuit 28 (as described in the above-incorporated U.S. patent application Ser. No. 09/775,897). While the DSP reset signal is asserted (e.g., active low), the DSP is held in reset and is initialized to a prescribed state. Upon deassertion of the DSP Reset signal, the logic code for the DSP (referred to as the “boot loader”) is copied from the non-volatile logic device 24 into memory residing in the DSP 21 (step 51). This allows the DSP to execute the initialization of the programmable logic device 22. In a preferred embodiment, the lower 1K bytes of EPROM memory is copied to the first 1 k bytes of DSP's low memory (0x0000 0000 through 0x0000 03FF). As noted above, the memory mapping of the DSP 21 maps the CE1 memory space located at 0x9000 0000 through 0x9001 FFFF with the OTP EPROM. In a preferred embodiment using the Texas Instrument DSP TMS320c6211GFN-150, this ROM boot process is executed by the EDMA controller of the DSP. It is to be understood, however, that the EDMA controller may be instantiated in the programmable logic device (Xilinx), or shared between the DSP and programmable logic device.
  • After the logic is loaded in the [0070] DSP 21, the DSP 21 begins execution out of the lower 1K bytes of memory (step 52). In a preferred embodiment, the DSP 21 initializes with at least the functionality to read EPROM Memory (CE1) space. Then, as described above, the DSP preferably configures its serial ports as general purpose I/O (step 53).
  • Next, the [0071] DSP 21 will initialize the programmable logic device 22 using one or more suitable control signals. (step 54). After initialization, the DSP 21 begins reading the configuration data of the programmable logic device 22 from the non-volatile memory 24 (step 55). This process begins with clearing a Data Byte Counter and then reading the first data byte beginning at a prespecified memory location in the non-volatile memory 24 (step 56). Then, the first output byte is loaded into the DSP's I/O locations with LSB at D0 and MSB at D7 (step 57). Before the first byte is loaded to the logic device 22, a prespecified time delay (e.g., 5 usec) is provided to ensure that the logic device 22 has been initialized (step 58). In particular, this time delay should be of a duration at least equal to the internal setup time of the programmable logic device 22 from completion of initialization. Once this time delay has expired, the first data byte in the I/O bus 26 of the DSP 21 is latched into the programmable logic device 22 (step 59).
  • Next, a determination is made as to whether the Data Byte Counter is less than a prespecified value (step [0072] 60). If the Data Byte Counter is less than the prespecified value (affirmative determination in step 60), the next successive data byte for the programmable logic device 22 is read from the non-volatile memory 24 (step 61) and the Data Byte Counter is incremented (step 62).
  • Next, the read data byte is loaded into the I/O of the DSP (step [0073] 63). A time delay of, e.g., 20 nsec is allowed to expire before the data byte is latched to the programmable logic device to ensure that a minimum data set-up time to the programmable logic device 21 is observed (step 64) and the process is repeated (return to step 60). It is to be appreciated that steps 60-64 may be performed while the current data byte is being latched to the programmable logic device. This provides “pipeline” programming of the logic device 22 and minimizes programming duration. When the Data Byte Counter is not less than the prespecified count value negative determination in step 60), as shown in FIG. 6b, the last data byte is read from the non-volatile memory and latched to the programmable logic device 22, and the DSP 21 will then poll a control signal generated by the programmable logic device 22 to ensure that the programming of the logic device 22 is successful (step 65). If programming is complete (affirmative determination in step 66), the process continues with the remainder of the data storage controller initialization (step 67). Otherwise, a timeout occurs (step 68) and upon expiration of the timeout, an error signal is provided and the programming process is repeated (step 69).
  • III. Data Storage and Retrieval Protocols [0074]
  • A detailed discussion of operational modes of a data storage controller will now be provided with reference to the embodiment of FIG. 2 (although it is to be understood that the following discussion is applicable to all the above-described embodiments). The [0075] data storage controller 20 utilizes a plurality of commands to implement the data storage, retrieval, and disk maintenance functions described herein. Each command preferably comprises eight thirty-two bit data words stored and transmitted in little endian format.
  • The commands include: Read Disk Data; Write Disk Data; and Copy Disk Data, for example. For example, a preferred format for the “Read Disk Data” command is: [0076]
    31 16 15 8 7 0
    Command Packet Number Command Type Command 00h
    0000h to FFFFh 00h Parameters (00h)
    Starting Block Address (Least Significant Word) 04h
    Starting Block Address (Most Significant Word) 08h
    Number of Blocks (Least Significant Word) 0Ch
    Number of Blocks (Most Significant Word) 10h
    Destination Address (Least Significant Word) 14h
    Destination Address (Most Significant Word) 18h
    Checksum Reserved 1Ch
  • The host computer commands the [0077] data storage controller 20 over the PCI Bus 16, for example. Upon computer power-up or reset, the host computer issues a PCI Bus Reset with a minimum pulse width of 100 msec (in accordance with PCI Bus Specification Revision 2.2). Upon completion of the PCI Bus reset, the data storage controller 20 is fully initialized and waiting for completion of the PCI configuration cycle. Upon completion of the PCI configuration cycles, the data storage controller will wait in an idle state for the first disk command.
  • During operation, the host operating system may issue a command to the [0078] data storage controller 20 to store, retrieve, or copy specific logical data blocks. Each command is transmitted over the PCI Bus 16 at the Address assigned to the Base Address Register (BAR) of the data storage controller 20.
  • The commands issued by the host system to the data storage controller and the data transmitted to and from the data storage controller are preferably communicated via a 32 bit, 33 MHz, PCI Data Bus. As noted above, the PCI Interface is preferably housed within the onboard Xilinx Spartan XCS40XL-5 40,000 field programmable gate array which instantiates a [0079] PCI 32, 32 Bit, 33 MHz PCI Bus Interface (as per PCI Bus Revision 2.2).
  • The PCI Bus interface operates in Slave Mode when receiving commands and as a Bus Master when reading or writing data. The source and destination for all data is specified within each command packet. When setting up data transfers, the Enhanced Direct Memory Access (EDMA) Controller of the DSP (or the Xilinx) utilizes two Control Registers, a 16 Word Data Write to PCI Bus FIFO, a 16 Word Data Read From PCI Bus FIFO, and a PCI Data Interrupt (PCIDATINT). The 32 Bit PCI Address Register holds either the starting Source Address for data storage controller Disk Writes where data is read from the PCI Bus, or the starting Destination Address for data storage controller Disk Reads where data is written to the PCI Bus. The second control register is a PCI Count Register that specifies the direction of the data transfer along with the number of 32 bit Data words to be written to or from the PCI bus. [0080]
  • Data is written to the PCI Bus from the DSP via a [0081] 16 Word PCI Data Write FIFO located within a prespecified address range. Data writes from the DSP to anywhere within the address range place that data word in the next available location within the FIFO. Data is read from the PCI Bus to the DSP via a 16 Word PCI Data Read FIFO located within a prespecified address range and data read by the DSP from anywhere within this address range provides the next data word from the FIFO.
  • After completion of the Xilinx initialization by the DSP and subsequent negation of the PCI Bus Reset signal (RST#) by the host computer's PCI Bridge, the data storage controller is ready to accept commands from the host computer via the PCI Bus. When accepting commands it should be noted that the data storage controller is a PCI Target (Slave) Device. Commands are preferably fixed in length at exactly 8 (thirty-two bit) words long. Commands are written from the host computer to the data storage controller via the PCI Bus utilizing the data storage controller's Base Address Register 0 (BAR0). The PCI Bus Reset initially sets the Command FIFO's Counter to zero and also signals the Xilinx's PCI Bus State Controller that the Command FIFO is empty and enable to accept a command. [0082]
  • Whenever a data write occurs within the valid data range of BAR0, the data word is accepted from PCI Bus and placed in the next available memory position within the Command FIFO. When the last of the 8 thirty-two bit data words is accepted by the PCI Bus (thus completing the command, i.e. last word for the command FIFO to be full), the PCI Bus State Controller is automatically set to Target Abort (within same PCI Transaction) or Disconnect Without Data for all subsequent PCI transactions that try to writes to BAR0. This automatic setting is the responsibility of the Xilinx PCI Data Interface. [0083]
  • The PCI Command FIFO State Controller then asserts the Command Available Interrupt to the DSP. The DSP services the Command Available Interrupt by reading the command data from a prespecified address range. It should be noted that the command FIFO is read sequentially from any data access that reads data within such address range. It is the responsibility of the DSP to understand that the data is read sequentially from any order of accesses within the data range and should thus be stored accordingly. [0084]
  • Upon completion of the Command Available Interrupt Service Routine the DSP executes a memory read or write to desired location within the PCI Control Register Space mapped into the DSP's CE3 (Xilinx) memory space. This resets the Command FIFO Counter back to zero. Next, the DSP executes a memory read or write to location in the DSP Memory Space that clears the Command Available Interrupt. Nested interrupts are not possible since the PCI Bus State Machine is not yet able to accept any Command Data at BAR0. Once the Command Available Interrupt routine has cleared the interrupt and exited, the DSP may then enable the PCI State Machine to accept a new command by reading or writing to PCI Command Enable location within the PCI Command FIFO Control Register Space. [0085]
  • A preferred architecture has been selected to enable the data storage controller to operate on one command at a time or to accept multiple prioritized commands in future implementations. Specifically, the decoupling of the Command Available Interrupt Service Routine from the PCI State Machine that accepts Commands at BAR0 enables the DSP's “operating system kernel” to accept additional commands at any time by software command. In single command operation, a command is accepted, the Command Available Interrupt Cleared, and the Command executed by the data storage controller in PCI Master Mode prior to the enabling of the PCI State machine to accept new commands. [0086]
  • In a prioritized multi-command implementation, the “operating system kernel” may elect to immediately accept new commands or defer the acceptance of new commands based upon any software implemented decision criteria. In one embodiment, the O/S code might only allow a pre-specified number of commands to be queued. In another embodiment, commands might only be accepted during processor idle time or when the DSP is not executing time critical (i.e. highly pipelined) compress/decompress routines. In yet another embodiment, various processes are enabled based upon a pre-emptive prioritized based scheduling system. [0087]
  • As previously stated, the data storage controller retrieves commands from the input command FIFO in 8 thirty-two bit word packets. Prior to command interpretation and execution, a command's checksum value is computed to verify the integrity of the data command and associated parameters. If the checksum fails, the host computer is notified of the command packet that failed utilizing the Command Protocol Error Handler. Once the checksum is verified the command type and associated parameters are utilized as an offset into the command “pointer” table or nay other suitable command/data structure that transfers control to the appropriate command execution routine. [0088]
  • Commands are executed by the data storage controller with the data storage controller acting as a PCI Master. This is in direct contrast to command acceptance where the data storage controller acts as a PCI Slave. When acting as a PCI Bus Master, the data storage controller reads or writes data to the PCI Bus utilizing a separate PCI Bus Data FIFO (distinct & apart from the Command FIFO). The PCI Data FIFO is 64 (thirty-two bit) words deep and may be utilized for either data reads or data writes from the DSP to the PCI Bus, but not both simultaneously. [0089]
  • For data to be written from the data storage controller to the Host Computer, the DSP must first write the output data to the PCI Bus Data FIFO. The Data FIFO is commanded to PCI Bus Data Write Mode by writing to a desired location within the Xilinx (CE3) PCI Control Register Space. Upon PCI Bus Reset the default state for the PCI Data FIFO is write mode and the PCI Data FIFO Available Interrupt is cleared. The PCI Data FIFO Available Interrupt should also be software cleared by writing to a prespecified location. Preferably, the first task for the data storage controller is for system boot-up or application code to be downloaded from disk. For reference, PCI Data Read Mode is commanded by writing to location BFF0 0104. The PCI Bus Reset initializes the Data FIFO Pointer to the first data of the 64 data words within the FIFO. However this pointer should always be explicitly initialized by a memory write to location BFF0 0108. This ensures that the first data word written to the FIFO by the DSP performing the data write anywhere in address range B000 0000 to B000 01FF is placed at the beginning of the FIFO. Each subsequent write to any location within this address range then places one thirty-two bit data word into the next available location within the PCI Data FIFO. The FIFO accepts up to 64 thirty-two bit data words although it should be clearly understood that not all data transfers to and from the PCI Bus will consist of a full FIFO. Counting the number of thirty-two bit data words written to the PCI Data FIFO is the responsibility of the DSP Code. It is envisioned that the DSP will, in general, use 64 word DMA data transfers, thus alleviating any additional processor overhead. When the data has been transferred from the DSP to the PCI Data FIFO, the PCI Bus Controller also needs the address of the PCI Target along with the number of data words to be transmitted. In the current data storage controller implementation, the PCI Bus Address is thirty-two bits wide, although future PCI bus implementations may utilize multiword addressing and/or significantly larger (64 bit & up) address widths. The single thirty-two bit address word is written by the DSP to memory location aaaa+0×10 in the PCI Control Register Space. [0090]
  • Finally, the PCI Bus Data Write transaction is initiated by writing the PCI Data FIFO word count to a prespecified memory address. The word count value is always decimal 64 or less (0×3F). When the count register is written the value is automatically transferred to the PCI Controller for executing the PCI Bus Master writes. [0091]
  • When the PCI Bus has completed the transfer of all data words within the PCI Data FIFO the PCI Data FIFO Available Interrupt is set. The DSP PCI Data FIFO Available Interrupt handler will then check to see if additional data is waiting or expected to be written to the PCI Data Bus. If additional data is required the interrupt is cleared and the data transfer process repeats. If no additional data is required to be transferred then the interrupt is cleared and the routine must exit to a system state controller. For example, if the command is complete then master mode must be disabled and then slave mode (command mode) enabled—assuming a single command by command execution data storage controller. [0092]
  • For data to be read by the data storage controller from the Host Computer, the DSP must command the PCI Bus with the address and quantity of data to be received. [0093]
  • The PCI Data FIFO is commanded to PCI Bus Data Read Mode by writing to a desired location within the Xilinx (CE3) PCI Control Register Space. Upon PCI Bus Reset the default state for the PCI Data FIFO is Write Mode and the PCI Data FIFO Full Interrupt is cleared. The PCI Data FIFO Full Interrupt should also be cleared via software by writing to such location. The PCI Bus Reset also initializes the PCI Data FIFO Pointer to the first data word of the available 64 data words within the FIFO. However this pointer should always be explicitly initialized by a memory write to prespecified location. [0094]
  • For data to be read from the PCI Bus by the data storage controller, the Xilinx PCI Bus Controller requires the address of the PCI Target along with the number of data words to be received. In the current data storage controller implementation, the PCI Bus Address is thirty-two bits wide, although future PCI bus implementations may utilize multiword addressing and/or significantly larger (64 bit & up) address widths. The single thirty-two bit address word is written by the DSP to prespecified memory location in the PCI Control Register Space. [0095]
  • Finally, the PCI Bus Data Read transaction is initiated by writing the PCI Data FIFO word count to prespecified memory address. The word count value is always decimal 64 or less (0×3F). When the count register is written the value is automatically transferred to the PCI Controller for executing the PCI Bus Master Read. [0096]
  • When the PCI Bus has received all the requested data words PCI Data FIFO Full Interrupt is set. The DSP PCI Data FIFO Full Interrupt handler will then check to see if additional data is waiting or expected to be read from the PCI Data Bus. If additional data is required the interrupt is cleared and the data receipt process repeats. If no additional data is required to be transferred, then the interrupt is cleared and the routine exits to a system state controller. For example, if the command is complete then master mode must be disabled and then slave mode (command mode) enabled—assuming a single command by command execution data storage controller. [0097]
  • It is clearly understood that there are other techniques for handling the PCI Data transfers. The current methodology has been selected to minimize the complexity and resource utilization of the Xilinx Gate Array. It should also be understood that the utilization of asynchronous memory reads and writes to initialize system states and synchronize events at a software level aids in both hardware and system level debug at the expense of increase software overhead. Subsequent embodiments of the gate array may automate resource intensive tasks if system level performance mandates. [0098]
  • IV. Memory Bandwidth Allocation [0099]
  • The onboard cache of the data storage controller is shared by the DSP, Disk Interface, and PCI Bus. The best case, maximum bandwidth for the SDRAM memory is 70 megawords per second, or equivalently, 280 megabytes per second. The 32 bit PCI Bus interface has a best case bandwidth of 132 megabytes per second, or equivalently 33 megawords per second. In current practice, this bandwidth is only achieved in short bursts. The granularity of PCI data bursts to/from the data storage controller is governed by the PCI Bus interface data buffer depth of sixteen words (64 bytes). The time division multiplexing nature of the current PCI Data Transfer Buffering methodology cuts the 10 sustained PCI bandwidth down to 66 megabytes/second. [0100]
  • Data is transferred across the ultraDMA disk interface at a maximum burst rate of 66 megabytes/second. It should be noted that the burst rate is only achieved with disks that contain onboard cache memory. Currently this is becoming more and more popular within the industry. However assuming a disk cache miss, the maximum transfer rates from current disk drives is approximately six megabytes per second. Allotting for technology improvements over time, the data storage controller has been designed for a maximum sustained disk data rate of 20 megabytes second (5 megawords/second). A design challenge is created by the need for continuous access to the SDRAM memory. Disks are physical devices and it is necessary to continuously read data from disk and place it into memory, otherwise the disk will incur a full rotational latency prior to continuing the read transaction. The maximum SDRAM access latency that can be incurred is the depth of the each of the two disk FIFO s or sixteen data. Assuming the [0101]
  • FIFO is sixteen words deep the maximum latency time for emptying the other disk FIFO and restoring it to the disk interface is sixteen words at 5 megawords per second or (16×3.2 usec)=1 usec. Each EMIF clock cycle is 14.2857 nsec, thus the maximum latency translates to 224 clock cycles. It should be noted that transfers across the disk interface are 16 bits wide, thus the FPGA is required to translate 32 bit memory transfers to 16 bit disk transfers, and vice-versa. [0102]
  • The DSP services request for its external bus from two requesters, the Enhanced Direct Memory Access (EDMA) Controller and an external shared memory device controller. The DSP can typically utilize the full 280 megabytes of bus bandwidth on an 8k through 64K byte (2 k word through 16 k word) burst basis. It should be noted that the DSRA does not utilize the SDRAM memory for interim processing storage, and as such only utilizes bandwidth in direct proportion to disk read and write commands. [0103]
  • For a single read from disk transaction data is transferred from and DMA transfer into SDRAM memory. This data is then DMA transferred by the DSP into onboard DSP memory, processed, and re transferred back to SDRAM in decompressed format (3 words for every one word in). Finally the data is read from SDRAM by the PCI Bus Controller and placed into host computer memory. This equates to eight SDRAM accesses, one write from disk, one read by the DSP, three writes by the DSP and three by the PCI Bus. Disk write transactions similarly require eight SDRAM accesses, three from the PCI, three DSP reads, one DSP write, and one to the disk. [0104]
  • Neglecting overhead for setting up DMA transfers, arbitration latencies, and memory wait states for setting up SDRAM transactions, the maximum DSRA theoretical SDRAM bandwidth limit for disk reads or writes is 280/8 megabytes second or 35 megabytes second. It should be noted that the best case allocation of SDRAM bandwidth would be dynamic dependent upon the data compression and decompression ratios. Future enhancements to the data storage controller will utilize a programmable timeslice system to allocate SDRAM bandwidth, however this first embodiment will utilize a fixed allocation ratio as follows: [0105]
  • If all three requesters require SDRAM simultaneously: [0106]
    PCI Bus Interface 3/8
    DSP Accesses 4/8
    UltraDMA Disk Interface 1/8
  • If only the PCI Bus and DSP require SDRAM: [0107]
    PCI Bus Interface 4/8
    DSP Accesses 4/8
  • If only the DSP and Disk require SDRAM: [0108]
    DSP Accesses 6/8
    UltraDMA Disk Interface 2/8
  • If only the PCI Bus and Disk require SDRAM: [0109]
    PCI Bus Interface 6/8
    UltraDMA Disk Interface 2/8
  • If only one device requires SDRAM it receives the full SDRAM bandwidth. It should be noted that different ratios may be applied based upon the anticipated or actual compression and/or decompression ratios. For example in the case of all three requestors active the following equation applies. Assume that data storage accelerator achieves a compression ratio A:B for example 3:1. The Numerator and denominators of the various allocations are defined as follows: [0110]
    PCI Bus Interface A/K
    DSP Accesses (A + B)/K
    UltraDMA Disk Interface B/K
  • Where Further define a sum K equal to the sum of the numerators of the PCI Bus interface fraction, the DSP Access fraction, and the UltraDMA Disk Interfaces, i.e. K=2(A+B). Similarly: [0111]
  • If only the PCI Bus and DSP require SDRAM: [0112]
    PCI Bus Interface (A + B)/K
    DSP Accesses (A + B)/K
  • If only the DSP and Disk require SDRAM: [0113]
    DSP Accesses 2A/K
    UltraDMA Disk Interface 2B/K
  • If only the PCI Bus and Disk require SDRAM: [0114]
    PCI Bus Interface 2A/K
    UltraDMA Disk Interface 2B/K
  • It should be noted that the resultant ratios may all be scaled by a constant in order to most effectively utilize the bandwidths of the internal busses and external interfaces. In addition each ratio can be scale by an adjustment factor based upon the time required to complete individual cycles. For example if PCI Bus interface takes 20% longer than all other cycles, the PCI time slice should be adjusted longer accordingly. [0115]
  • V. Instant Boot Device For Operating System, Application Program and Loading [0116]
  • Typically, with conventional boot device controllers, after reset, the boot device controller will wait for a command over the computer bus (such as PCI). Since the boot device controller will typically be reset prior to bus reset and before the computer bus starts sending commands, this wait period is unproductive time. The initial bus commands inevitably instruct the boot device controller to retrieve data from the boot device (such as a disk) for the operating system. Since most boot devices are relatively slow compared to the speed of most computer busses, a long delay is seen by the computer user. This is evident in the time it takes for a typical computer to boot. [0117]
  • It is to be appreciated that a data storage controller (having an architecture as described herein) may employ a technique of data preloading to decrease the computer system boot time. Upon host system power-up or reset, the data storage controller will perform a self-diagnostic and program the programmable logic device (as discussed above) prior to completion of the host system reset (e.g., PCI bus reset) so that the logic device can accept PCI Bus commands after system reset. Further, prior to host system reset, the data storage controller can proceed to pre-load the portions of the computer operating system from the boot device (e.g., hard disk) into the on-board cache memory. The data storage controller preloads the needed sectors of data in the order in which they will be needed. Since the same portions of the operating system must be loaded upon each boot process, it is advantageous for the boot device controller to preload such portions and not wait until it is commanded to load the operating system. Preferably, the data storage controller employs a dedicated 10 channel of the DSP (with or without data compression) to pre-load computer operating systems and applications. [0118]
  • Once the data is preloaded, when the computer system bus issues its first read commands to the data storage controller seeking operating system data, the data will already be available in the cache memory of the data storage controller. The data storage controller will then be able to instantly start transmitting the data to the system bus. Before transmission to the bus, if the was stored in compressed format on the boot device, the data will be decompressed. The process of preloading required (compressed) portions of the operating system significantly reduces the computer boot process time. [0119]
  • In addition to preloading operating system data, the data storage controller could also preload other data that the user would likely want to use at startup. An example of this would be a frequently used application such as a word processor and any number of document files. [0120]
  • There are several techniques that may be employed in accordance with the present invention that would allow the data storage controller to know what data to preload from the boot device. One technique utilizes a custom utility program that would allow the user to specify what applications/data should be preloaded. [0121]
  • Another technique (illustrated by the flow diagram of FIGS. 7[0122] a and 7 b) that may be employed comprises an automatic process that requires no input from the user. With this technique, the data storage controller maintain a list comprising the data associated with the first series of data requests received by the data storage controller by the host system after a power-on/reset. In particular, referring to FIG. 7a, during the computer boot process, the data storage controller will receive requests for the boot data (step 70). In response, the data storage controller will retrieve the requested boot data from the boot device (e.g., hard disk) in the local cache memory (step 71). For each requested data block, the data storage controller will record the requested data block number in a list (step 72). The data storage controller will record the data block number of each data block requested by the host computer during the boot process (repeat steps 70-72). When the boot process is complete (affirmative determination in step 73), the data storage controller will store the data list on the boot device (or other storage device) (step 74).
  • Then, upon each subsequent power-on/reset (affirmative result in step [0123] 75), the data storage controller would retrieve and read the stored list (step 76) and proceed to preload the boot data specified on the list (i.e., the data associated with the expected data requests) into the onboard cache memory (step 77). It is to be understood that the depending on the resources of the given system (e.g., memory, etc.), the preloading process may be completed prior to commencement of the boot process, or continued after the boot process begins (in which case booting and preloading are performed simultaneously).
  • When the boot process begins (step [0124] 78) (i.e., the storage controller is initialized and the system bus reset is deasserted), the data storage controller will receive requests for boot data (step 79). If the host computer issues a request for boot data that is pre-loaded in the local memory of the data storage controller (affirmative result in step 80), the request is immediately serviced using the preloaded boot data (step 81). If the host computer issues a request for boot data that is not preloaded in the local memory of the data storage controller (negative determination in step 80), the controller will retrieve the requested data from the boot device, store the data in the local memory, and then deliver the requested boot data to the computer bus (step 82). In addition, the data storage controller would update the boot data list by recording any changes in the actual data requests as compared to the expected data requests already stored in the list (step 83). Then, upon the next boot sequence, the boot device controller would pre-load that data into the local cache memory along with the other boot data previously on the list.
  • Further, during the boot process, if no request is made by the host computer for a data block that was pre-loaded into the local memory of the data storage controller (affirmative result in step [0125] 84), then the boot data list will be updated by removing the non-requested data block from the list (step 85). Thereafter, upon the next boot sequence, the data storage controller will not pre-load that data into local memory.
  • VI. Quick Launch for Operating System, Application Programs and Loading [0126]
  • It is to be appreciated that the data storage controller (having an architecture as described herein) may employ a technique of data preloading to decrease the time to load application programs (referred to as “quick launch”). Conventionally, when a user launches an application, the file system reads the first few blocks of the file off the disk, and then the portion of the loaded software will request via the file system what additional data it needs from the disk. For example, a user may open a spreadsheet program, and the program may be configured to always load a company spreadsheet each time the program is started. In addition, the company spreadsheet may require data from other spreadsheet files. [0127]
  • In accordance with the present invention, the data storage controller may be configured to “remember” what data is typically loaded following the launch of the spreadsheet program, for example. The data storage controller may then proceed to preload the company spreadsheet and all the necessary data in the order is which such data is needed. Once this is accomplished, the data storage controller can service read commands using the preloaded data. Before transmission to the bus, if the preloaded data was stored in compressed format, the data will be decompressed. The process of preloading (compressed) program data significantly reduces the time for launching an application. [0128]
  • Preferably, a custom utility program is employed that would allow the user to specify what applications should be made ready for quick launch. [0129]
  • FIGS. 8[0130] a and 8 b comprise a flow diagram of a quick launch method according to one aspect of the present invention. With this technique, the data storage controller maintains a list comprising the data associated with launching an application. In particular, when an application is first launched, the data storage controller will receive requests for the application data (step 90). In response, the data storage controller will retrieve the requested application data from memory (e.g., hard disk) and store it in the local cache memory (step 91). The data storage controller will record the data block number of each data block requested by the host computer during the launch process (step 92). When the launch process is complete (affirmative determination in step 93), the data storage controller will store the data list in a designated memory location (step 94). Then, referring to FIG. 8b, upon each subsequent launch of the application (affirmative result in step 95), the data storage controller would retrieve and read the stored list (step 96) and then proceed to preload the application data specified on the list (i.e., the data associated with the expected data requests) into the onboard cache memory (step 97). During the application launch process, the data storage controller will receive requests for application data (step 98). If the host computer issues a request for application data that is pre-loaded in the local memory of the data storage controller (affirmative result in step 99), the request is immediately serviced using the preloaded data (step 100). If the host computer issues a request for application data that is not preloaded in the local memory of the data storage controller (negative result in step 99), the controller will retrieve the requested data from the hard disk memory, store the data in the local memory, and then deliver the requested application data to the computer bus (step 101). In addition, the data storage controller would update the application data list by recording any changes in the actual data requests as compared to the expected data requests already stored in the list (step 102).
  • Further, during the launch process, if no request is made by the host computer for a data block that was pre-loaded into the local memory of the data storage controller (affirmative result in step [0131] 103), then the application data list will be updated by removing the non-requested data block from the list (step 104). Thereafter, upon the next launch sequence for the given application, the data storage controller will not pre-load that data into local memory.
  • It is to be understood that the quick boot and quick launch methods described above are preferably implemented by a storage controller according to the present invention and may or may not utilize data compression/decompression by the DSP. However, it is to be understood that the quick boot and quick launch methods may be implemented by a separate device, processor, or system, or implemented in software. [0132]
  • VII. Content Independent Data Compression [0133]
  • It is to be understood that any conventional compression/decompression system and method (which comply with the above mentioned constraints) may be employed in the data storage controller for providing accelerated data storage and retrieval in accordance with the present invention. Preferably, the present invention employs the data compression/decompression techniques disclosed in the above-incorporated U.S. Pat. No. 6,195,024. [0134]
  • Referring to FIG. 9, a detailed block diagram illustrates an exemplary [0135] data compression system 110 that may be employed herein. Details of this data compression system are provided in U.S. Pat. No. 6,195,024. In this embodiment, the data compression system 110 accepts data blocks from an input data stream and stores the input data block in an input buffer or cache 115. It is to be understood that the system processes the input data stream in data blocks that may range in size from individual bits through complete files or collections of multiple files. Additionally, the input data block size may be fixed or variable. A counter 120 counts or otherwise enumerates the size of input data block in any convenient units including bits, bytes, words, and double words.
  • It should be noted that the [0136] input buffer 115 and counter 120 are not required elements of the present invention. The input data buffer 115 may be provided for buffering the input data stream in order to output an uncompressed data stream in the event that, as discussed in further detail below, every encoder fails to achieve a level of compression that exceeds an a priori specified minimum compression ratio threshold.
  • Data compression is performed by an [0137] encoder module 125 which may comprise a set of encoders E1, E2, E3 . . . En. The encoder set E1, E2, E3 . . . En may include any number “n” (where n may=1) of those lossless encoding techniques currently well known within the art such as run length, Huffman, Lempel-Ziv Dictionary Compression, arithmetic coding, data compaction, and data null suppression. It is to be understood that the encoding techniques are selected based upon their ability to effectively encode different types of input data. It is to be appreciated that a full complement of encoders are preferably selected to provide a broad coverage of existing and future data types.
  • The [0138] encoder module 125 successively receives as input each of the buffered input data blocks (or unbuffered input data blocks from the counter module 120). Data compression is performed by the encoder module 125 wherein each of the encoders E1 . . . En processes a given input data block and outputs a corresponding set of encoded data blocks. It is to be appreciated that the system affords a user the option to enable/disable any one or more of the encoders E1 . . . En prior to operation. As is understood by those skilled in the art, such feature allows the user to tailor the operation of the data compression system for specific applications. It is to be further appreciated that the encoding process may be performed either in parallel or sequentially. In particular, the encoders E1 through En of encoder module 125 may operate in parallel (i.e., simultaneously processing a given input data block by utilizing task multiplexing on a single central processor, via dedicated hardware, by executing on a plurality of processor or dedicated hardware systems, or any combination thereof). In addition, encoders E1 through En may operate sequentially on a given unbuffered or buffered input data block. This process is intended to eliminate the complexity and additional processing overhead associated with multiplexing concurrent encoding techniques on a single central processor and/or dedicated hardware, set of central processors and/or dedicated hardware, or any achievable combination. It is to be further appreciated that encoders of the identical type may be applied in parallel to enhance encoding speed. For instance, encoder E1 may comprise two parallel Huffman encoders for parallel processing of an input data block.
  • A buffer/counter module [0139] 130 is operatively connected to the encoder module 125 for buffering and counting the size of each of the encoded data blocks output from encoder module 125. Specifically, the buffer/counter 130 comprises a plurality of buffer/counters BC1, BC2, BC3 . . . .BCn, each operatively associated with a corresponding one of the encoders E1 . . . En. A compression ratio module 135, operatively connected to the output buffer/counter 130, determines the compression ratio obtained for each of the enabled encoders E1 . . . En by taking the ratio of the size of the input data block to the size of the output data block stored in the corresponding buffer/counters BC1 . . . BCn. In addition, the compression ratio module 135 compares each compression ratio with an a priori-specified compression ratio threshold limit to determine if at least one of the encoded data blocks output from the enabled encoders E1 . . . En achieves a compression that exceeds an a priori-specified threshold. As is understood by those skilled in the art, the threshold limit may be specified as any value inclusive of data expansion, no data compression or expansion, or any arbitrarily desired compression limit. A description module 138, operatively coupled to the compression ratio module 135, appends a corresponding compression type descriptor to each encoded data block which is selected for output so as to indicate the type of compression format of the encoded data block. A data compression type descriptor is defined as any recognizable data token or descriptor that indicates which data encoding technique has been applied to the data. It is to be understood that, since encoders of the identical type may be applied in parallel to enhance encoding speed (as discussed above), the data compression type descriptor identifies the corresponding encoding technique applied to the encoded data block, not necessarily the specific encoder. The encoded data block having the greatest compression ratio along with its corresponding data compression type descriptor is then output for subsequent data processing, storage, or transmittal. If there are no encoded data blocks having a compression ratio that exceeds the compression ratio threshold limit, then the original unencoded input data block is selected for output and a null data compression type descriptor is appended thereto. A null data compression type descriptor is defined as any recognizable data token or descriptor that indicates no data encoding has been applied to the input data block. Accordingly, the unencoded input data block with its corresponding null data compression type descriptor is then output for subsequent data processing, storage, or transmittal.
  • Again, it is to be understood that the embodiment of the data compression engine of FIG. 9 is exemplary of a preferred compression system which may be implemented in the present invention, and that other compression systems and methods known to those skilled in the art may be employed for providing accelerated data storage in accordance with the teachings herein. Indeed, in another embodiment of the compression system disclosed in the above-incorporated U.S. Pat. No. 6,195,024, a timer is included to measure the time elapsed during the encoding process against an a priori-specified time limit. When the time limit expires, only the data output from those encoders (in the encoder module [0140] 125) that have completed the present encoding cycle are compared to determine the encoded data with the highest compression ratio. The time limit ensures that the real-time or pseudo real-time nature of the data encoding is preserved. In addition, the results from each encoder in the encoder module 125 may be buffered to allow additional encoders to be sequentially applied to the output of the previous encoder, yielding a more optimal lossless data compression ratio. Such techniques are discussed in greater detail in the above-incorporated U.S. Pat. No. 6,195,.
  • Referring now to FIG. 10, a detailed block diagram illustrates an exemplary decompression system that may be employed herein or accelerated data retrieval as disclosed in the above-incorporated U.S. Pat. No. 6,195,024. In this embodiment, the [0141] data compression engine 180 retrieves or otherwise accepts compressed data blocks from one or more data storage devices and inputs the data via a data storage interface. It is to be understood that the system processes the input data stream in data blocks that may range in size from individual bits through complete files or collections of multiple files.
  • Additionally, the input data block size may be fixed or variable. The [0142] data decompression engine 180 comprises an input buffer 155 that receives as input an uncompressed or compressed data stream comprising one or more data blocks. The data blocks may range in size from individual bits through complete files or collections of multiple files. Additionally, the data block size may be fixed or variable.
  • The [0143] input data buffer 55 is preferably included (not required) to provide storage of input data for various hardware implementations. A descriptor extraction module 160 receives the buffered (or unbuffered) input data block and then parses, lexically, syntactically, or otherwise analyzes the input data block using methods known by those skilled in the art to extract the data compression type descriptor associated with the data block. The data compression type descriptor may possess values corresponding to null (no encoding applied), a single applied encoding technique, or multiple encoding techniques applied in a specific or random order (in accordance with the data compression system embodiments and methods discussed above).
  • A decoder module [0144] 165 includes one or more decoders D1 . . . Dn for decoding the input data block using a decoder, set of decoders, or a sequential set of decoders corresponding to the extracted compression type descriptor. The decoders D1 . . . Dn may include those lossless encoding techniques currently well known within the art, including: run length, Huffman, Lempel-Ziv Dictionary Compression, arithmetic coding, data compaction, and data null suppression. Decoding techniques are selected based upon their ability to effectively decode the various different types of encoded input data generated by the data compression systems described above or originating from any other desired source.
  • As with the data compression systems discussed in U.S. application Ser. No. 09/210,491, the decoder module [0145] 165 may include multiple decoders of the same type applied in parallel so as to reduce the data decoding time. An output data buffer or cache 170 may be included for buffering the decoded data block output from the decoder module 165. The output buffer 70 then provides data to the output data stream. It is to be appreciated by those skilled in the art that the data compression system 180 may also include an input data counter and output data counter operatively coupled to the input and output, respectively, of the decoder module 165. In this manner, the compressed and corresponding decompressed data block may be counted to ensure that sufficient decompression is obtained for the input data block.
  • Again, it is to be understood that the embodiment of the [0146] data decompression system 180 of FIG. 10 is exemplary of a preferred decompression system and method which may be implemented in the present invention, and that other data decompression systems and methods known to those skilled in the art may be employed for providing accelerated data retrieval in accordance with the teachings herein.
  • VIII. Data Acceleration Controller [0147]
  • The block diagrams of FIGS. 11 and 12 illustrate disk architectures according to additional embodiments of the present invention. FIG. 11 and FIGS. [0148] 12 illustrate composite implementations of disk controller frameworks. Novel aspects of these architectures include, for example, the incorporation of a separate disk controller function and the addition of a data compression/decompression engine.
  • The benefits of such architectures are numerous, including, for example, increased reliability due to fewer components, higher throughput performance by eliminating unnecessary interfaces and handling less data due to compression, compression will aid in the thirst for greater disk densities, lower overall system costs due to less components and mechanical interfaces, and the ability to implement transparent pipelining to the host for increased system performance. [0149]
  • In general, the disk controller architectures in FIGS. 11 and 12 essentially provide an interface directly from the disk to the host main bus. Any number of busses could be implemented such as PCI, PCMCIA, Pentium, VMEBUS, etc. [0150]
  • The disk controller framework illustrated in FIG. 11 comprises a disk controls and [0151] status module 1110, a cache management and interface control module 1120, a data cache 1130, a compression/decompression engine 1140, host interface busses 1150, a local high-speed bus 1160 and a data and command cache 1170. The data and command cache 1170 is operatively connected to the host interface busses 1150 (via a host interface buffered data bus 80) and to the data compression/decompression engine 1140 via the local bus 1160, to thereby allow data to be transferred to/from the host while the compression engine 1140 works on another buffered data block. The architecture of FIG. 11 maximizes pipelining and produces a maximum throughput.
  • FIG. 12 is a block diagram of a disk controller according to another embodiment of the present invention, comprising a disk controls and [0152] status module 1110, a cache management and interface control module 1120, a data cache 1130, a compression/decompression engine 1140, host interface busses 1150, and a local high-speed bus 1160. The architecture of FIG. 12 comprises a single buffer between the host and the compression engine 1140 and comprises a more cost effective architecture than that of FIG. 11, but with reduced throughput in certain applications.
  • In the frameworks of FIGS. 11 and 12, the [0153] data cache 1130 is connected to the data compression/decompression engine 1140 and the actual disk, which enable overlap of disk operations with data storage operations. The local high-speed bus 1160 in both architectures preferably operates primarily in block mode for optimal efficiency. The cache management & interface control module 1120, which communicates with the compression engine 1140 over a dedicated secondary high-speed bus 1190, controls the data flow through the disk system under commands from the compression/decompression engine 1140. This architecture allows data to flow from the disk and the host interface at the same time while the engine 1140 is operating on a separate block of data.
  • In a preferred embodiment of the present invention, the data compression/[0154] decompression engine 1140 employs the compression/decompression methods described in the above-incorporated U.S. Pat. No. 6,195,024, issued Feb. 27, 2001 to J. Fallon, U.S. Pat. No. 6,309,424, issued on Oct. 30, 2001 to J. Fallon, and/or the techniques described in U.S. patent application Ser. No. 10/016,355, filed on Oct. 29, 2001, which are all commonly assigned and incorporated herein by reference. It should be noted in the following discussion that the use of the term DSP (digital signal processor) may also refer to a plurality of DSP(s), one or a plurality of general purpose processors, finite state machines, micro code, logic, firmware, or software.
  • The data compression and decompression functions to accomplish data storewidth acceleration and or storage multiplication may be accomplished in either hardware, software, or any combination thereof. [0155]
  • In accordance with the present invention, minimizing the cost of the data storage and maximizing retrieval storewidth acceleration and or storage multiplication function is preferably achieved by sharing hardware and or software resources. [0156]
  • VIII. Data Accelerator Embedded in Disk and Other Data Storage Devices [0157]
  • FIG. 13 is a block diagram of a magnetic disk controller according to another embodiment of the present invention. It should be noted that although the exemplary embodiment of FIG. 13 describes a magnetic disk, the present invention is applicable to any mass storage device. A magnetic disk implementation according to an embodiment of the present invention comprises a [0158] host computer interface 1300 coupled to a compression/decompression engine 1301, a bi-directional cache 1302, a command and status control module 1303, a cache management/virtual file system 1304 and/or full host file system. The system further comprises high performance Giant Magneto Resistive Heads 1305, analog signal processing/data recognition module 1306, a decoding and tracking module 1307, a closed loop positioning module 1308, multistage linear actuators 1309 for positioning, ramp load/unloading of heads, closed loop brushless DC motors 1310 with liquid bearings and associated drivers 1311, and a power conversion and management system 1312. Additional functions (not shown) comprise dynamic head calibrations, static head calibrations, dynamic calibration functions, static calibration functions, and corrections for time, temperature, aging, stress, and radiation, along with error detection and correction functions.
  • In one embodiment of the present invention, a DSP is utilized for storewidth acceleration and or storage multiplication, as well as other disk functions or control thereof as mentioned above. For example, in one embodiment, the virtual file management system [0159] 1304 and/or cache system 1302 are implemented in the same DSP. In another embodiment, management of a bi-directional cache, separate read/write caches, and or compressed/uncompressed caches, or any combination thereof, is also managed by the DSP. In another embodiment of the present invention, the disk command and control functions are further implemented in the DSP.
  • In another embodiment of the present invention, one or more of the following functions may be advantageously implemented in the DSP: data recognition or correlation, decoding and tracking, closed loop servo positioning, multistage linear actuator control for positioning, ramp load/unload management and control, closed loop brushless DC motor control, liquid bearing monitoring (temperature, fluid level), and power conversion and management system. [0160]
  • Additional functions comprise on the fly dynamic head calibrations with read/write testing, or with pre-stored patterns on the disk, static head calibrations (performed at construction or periodically), dynamic and static calibration functions performed periodically or by command, along with corrections for time, temperature, aging, stress, radiation, along with canonical error detection and correction functions. [0161]
  • Accordingly, it is to be appreciated that either all the functions or any portion thereof might be implemented in the DSP, with the balance by any available means including dedicated logic, other processors, finite state machines, micro code, firmware, or software. [0162]
  • In yet another embodiment of the present invention, the virtual file management system [0163] 1304 may be executed in an alternate processor, for example in the host computer, to offload the DSP or other disk processing for other data acceleration, bandwidth multiplication, and aforementioned disk functions. The virtual file management system 1304 is utilized to map uncompressed/unaccelerated blocks to the disk when they are compressed. With the present invention, a compressed data block occupies the same or less space than the original data. As such, the file management system 1304 must be aware of the new data size in order to store data efficiently on the disk. Current storage methods for disks, along with most other mass storage devices, store data in blocks that are either fixed or variable in size. The virtual file management 1304 system allows the appropriate data to be stored or retrieved even when the actual data is different in size than the original uncompressed data. Embedding the virtual file management system 1304 within the mass storage device has the advantage of reducing costs by sharing the processing and virtual file management mapping tasks. Virtual file management and data block mapping may be accomplished via look up tables or mathematical hashing functions. The mapping or hashing function virtualizes the physical disk or mass storage space. Assuming a 3:1 compression ratio, a one terabyte physical disk appears as a three terabyte virtual disk. The virtual file system 1304 allows uncompressed data in the three terabyte virtual space to be stored efficiently in the one terabyte physical space. Mapping data in small blocks has the advantage of being able to store, retrieve, or append with smaller more efficient units of data at the expense of larger look-up tables or more complex hashing functions.
  • In another embodiment of the present invention cache management is employed to manage data caching in both the physical space to the virtual space. Data retrieved from the mass storage device is stored compressed in a cache awaiting a cache hit. Typically, when data is retrieved, physically adjacent data or data known to be frequently referenced within the context of the retrieved data is also read from disk. Caches are typically uncompressed and thus require more memory and additional bandwidth for transfer. By caching compressed data on data reads, the cache is capable of storing a significantly larger quantity of data, making the likelihood of cache hits better and thus increasing system performance. Data is then decompressed when called for or in the background when the disk or controller is idle. [0164]
  • For data writes, the compressed data is stored in the cache awaiting synchronization with the mass storage disk or memory device. Again, the cache is capable of storing a much larger quantity of data (a function of compression ratio) and thus increases overall system performance. [0165]
  • In other embodiments, any element of the above-mentioned disk functions may be implemented wholly or partially with the disk DSP(s), host processor(s), alternate processor(s), or any combination thereof. [0166]
  • In yet another embodiment, the virtual file management system and the host operating system file management system are merged, with the results of the compression/decompression process utilized to minimize redundant disk management tasks. This function may be resident within the disk, within the host(s), or any combination thereof. The virtual file management system can consume significant processing resources, as such it may not always be optimal to embed the virtual file system within the mass storage device. The processing can be resident in the host, thus allowing the disk processor to work on disk management and data acceleration tasks, split between the two, or wholly resident within the storage device. [0167]
  • In yet another embodiment of the present invention the data acceleration is performed solely with the host. For example in Network Attached Storage Services and other mass storage arrays it may be advantageous to have the data acceleration solely within one or more host CPUs. The CPU(s) can share workload with other functions, such as network interfacing and application processing. The virtual file system can also be allocated to one or more of the same CPUs or it can be performed within the mass storage or disk device. [0168]
  • In another embodiment of the present invention, the DSP utilized for the data storewidth acceleration or storage multiplication is also utilized to perform the monitoring and actuation functions for a bearing fluid replenishment system as described below. The monitoring and actuation functions for the bearing fluid replenishment system may be performed in a separate processor, DSP, one or a plurality of general purpose processors, finite state machines, micro code, logic, firmware, or software—in addition the control function may be implemented in the host computer. [0169]
  • A bearing fluid replenishment system according to one embodiment of the present invention is utilized with a bearing fluid reservoir to extend the life of the bearing system. An actuator is utilized to fill the fluid to a constant level. Further the fluid level or pressure within the system is maintained at a constant level. For example, in the case of fluid dynamic bearings, the pressure is preferably maintained a constant level to provide minimum frictional losses while still isolating the rotating parts from contact. In another aspect of the present invention, the pressure and or fluid level is adjusted to optimum as a function of spin rate. In yet another aspect of the present invention, the fluid level or pressure is adjusted to optimum as a function of temperature. In yet another aspect of the present invention, the fluid level and/or pressure is adjusted according to closed loop feedback from the motor current or power consumption to an optimal level. In yet another aspect of the present invention, any combination of the above parameters are utilized in optimal combination to achieve lowest wear, longest life, highest reliability, minimum breakaway friction, minimum frictional losses, lowest power consumption, etc. [0170]
  • Moving fluid from the reservoir to the bearing chamber and/or back is accomplished by any means including piezo actuators, expandable/compressible diaphragms, mechanical actuators, electromagnetic actuators, gas pressure by heat, or any other means. [0171]
  • Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims. [0172]

Claims (18)

What is claimed is:
1. A controller for controlling storage and retrieval of data to and from a data storage device, comprising:
a data compression/decompression engine for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device;
a first cache, operatively connected to the storage device and the data compression/decompression engine, for temporary storage of (i) compressed data that is read from the data storage device and (ii) compressed data from the data compression/decompression engine that is to be written to the data storage device;
a second cache, operatively connected to the data compression/decompression engine and to a host interface bus, for temporary storage of (i) data that is received from a host system over the host interface bus for compression and storage and (ii) data that is to be sent to the host system over the host interface bus; and
a cache manager for controlling the first and second data caches under commands received from the data compression/decompression engine.
2. The controller of claim 1, wherein the controller comprises a disk controller and wherein the storage device comprises a hard disk.
3. The controller of claim 1, wherein the first cache, second cache and the data compression/decompression engine are operatively connected by a first local bus.
4. The controller of claim 1, wherein the data compression/decompression engine is connected to the cache manager over a dedicated bus.
5. The controller of claim 1, further comprising a virtual file system.
6. The controller of claim 1, wherein the controller comprises a magnetic disk controller.
7. The controller of claim 1, wherein the data compression/decompression engine, the first cache, and the second cache are implemented on a digital signal processor.
8. The controller of claim 1, wherein the controller provides accelerated data storage.
9. The controller of claim 1, wherein the controller provides accelerated data retrieval.
10. The controller of claim 1, wherein the first cache, second cache and data compression/decompression engine are embedded components of the controller.
11. A magnetic disk controller for controlling storage and retrieval of data to and from a magnetic disk, comprising:
an embedded data compression/decompression engine for compressing data stored to the magnetic disk and for decompressing data retrieved from the magnetic disk;
an embedded first cache, operatively connected to the magnetic disk and the data compression/decompression engine, for temporary storage of (i) compressed data that is read from the magnetic disk and (ii) compressed data from the data compression/decompression engine that is to be written to the magnetic disk;
an embedded second cache, operatively connected to the data compression/decompression engine and to a host interface bus, for temporary storage of (i) data that is received from a host system over the host interface bus for compression and storage and (ii) data that is to be sent to the host system over the host interface bus; and
an embedded cache manager for controlling the first and second data caches under commands received from the data compression/decompression engine.
12. The magnetic disk controller of claim 11, wherein the first cache, second cache and the data compression/decompression engine are operatively connected by a first local bus.
13. The controller of claim 11, wherein the data compression/decompression engine is connected to the cache manager over a dedicated bus.
14. The controller of claim 11, further comprising an embedded virtual file system.
15. The controller of claim 11, wherein the data compression/decompression engine, the first cache, and the second cache are implemented on a digital signal processor.
16. The controller of claim 1, wherein the controller provides accelerated data storage.
17. The controller of claim 1, wherein the controller provides accelerated data retrieval.
18. A magnetic disk controller for controlling storage and retrieval of data to and from a magnetic disk, comprising:
an embedded data compression/decompression engine for compressing data stored to the magnetic disk and for decompressing data retrieved from the magnetic disk;
an embedded bi-directional cache for temporary storage of (i) compressed data that is read from the magnetic disk and (ii) compressed data from the data compression/decompression engine that is to be written to the magnetic disk;
an embedded cache manager for controlling the bi-directional cache; and
an embedded virtual file management system for mapping compressed data blocks stored on the disk to corresponding uncompressed data blocks.
US10/306,581 2000-02-03 2002-11-27 Data storewidth accelerator Abandoned US20030191876A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/306,581 US20030191876A1 (en) 2000-02-03 2002-11-27 Data storewidth accelerator
US11/400,712 US7376772B2 (en) 2000-02-03 2006-04-08 Data storewidth accelerator
US12/688,413 US20100332700A1 (en) 2000-02-03 2010-01-15 Data storewidth accelerator

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US18011400P 2000-02-03 2000-02-03
US09/775,905 US6748457B2 (en) 2000-02-03 2001-02-02 Data storewidth accelerator
US33391901P 2001-11-28 2001-11-28
US10/306,581 US20030191876A1 (en) 2000-02-03 2002-11-27 Data storewidth accelerator

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/775,905 Continuation-In-Part US6748457B2 (en) 2000-02-03 2001-02-02 Data storewidth accelerator

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/400,712 Continuation US7376772B2 (en) 2000-02-03 2006-04-08 Data storewidth accelerator
US12/688,413 Continuation US20100332700A1 (en) 2000-02-03 2010-01-15 Data storewidth accelerator

Publications (1)

Publication Number Publication Date
US20030191876A1 true US20030191876A1 (en) 2003-10-09

Family

ID=46281629

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/306,581 Abandoned US20030191876A1 (en) 2000-02-03 2002-11-27 Data storewidth accelerator
US11/400,712 Expired - Fee Related US7376772B2 (en) 2000-02-03 2006-04-08 Data storewidth accelerator
US12/688,413 Abandoned US20100332700A1 (en) 2000-02-03 2010-01-15 Data storewidth accelerator

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/400,712 Expired - Fee Related US7376772B2 (en) 2000-02-03 2006-04-08 Data storewidth accelerator
US12/688,413 Abandoned US20100332700A1 (en) 2000-02-03 2010-01-15 Data storewidth accelerator

Country Status (1)

Country Link
US (3) US20030191876A1 (en)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030171105A1 (en) * 2002-03-06 2003-09-11 Dunworth Jeremy D. Calibration techniques for frequency synthesizers
US20040042506A1 (en) * 2000-10-03 2004-03-04 Realtime Data, Llc System and method for data feed acceleration and encryption
US6789167B2 (en) * 2002-03-06 2004-09-07 Hewlett-Packard Development Company, L.P. Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements
US20070083746A1 (en) * 2000-02-03 2007-04-12 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US20070168569A1 (en) * 2005-11-04 2007-07-19 Sun Microsystems, Inc. Adaptive resilvering I/O scheduling
US20070237327A1 (en) * 2006-03-23 2007-10-11 Exegy Incorporated Method and System for High Throughput Blockwise Independent Encryption/Decryption
US20090060197A1 (en) * 2007-08-31 2009-03-05 Exegy Incorporated Method and Apparatus for Hardware-Accelerated Encryption/Decryption
US7714747B2 (en) 1998-12-11 2010-05-11 Realtime Data Llc Data compression systems and methods
US20110184844A1 (en) * 2006-06-19 2011-07-28 Exegy Incorporated High Speed Processing of Financial Information Using FPGA Devices
US8054879B2 (en) 2001-02-13 2011-11-08 Realtime Data Llc Bandwidth sensitive data compression and decompression
US8275897B2 (en) 1999-03-11 2012-09-25 Realtime Data, Llc System and methods for accelerated data storage and retrieval
US20130128947A1 (en) * 2011-11-18 2013-05-23 At&T Intellectual Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US8504710B2 (en) 1999-03-11 2013-08-06 Realtime Data Llc System and methods for accelerated data storage and retrieval
US8620881B2 (en) 2003-05-23 2013-12-31 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US8692695B2 (en) 2000-10-03 2014-04-08 Realtime Data, Llc Methods for encoding and decoding data
US8762249B2 (en) 2008-12-15 2014-06-24 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US8843408B2 (en) 2006-06-19 2014-09-23 Ip Reservoir, Llc Method and system for high speed options pricing
US20150058576A1 (en) * 2013-08-20 2015-02-26 International Business Machines Corporation Hardware managed compressed cache
US9047243B2 (en) 2011-12-14 2015-06-02 Ip Reservoir, Llc Method and apparatus for low latency data distribution
US9143546B2 (en) 2000-10-03 2015-09-22 Realtime Data Llc System and method for data feed acceleration and encryption
US20150278021A1 (en) * 2012-10-16 2015-10-01 Bull Sas Method and device for improving the reliability of data storage in a hard disk comprising a plurality of platters
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10037568B2 (en) 2010-12-09 2018-07-31 Ip Reservoir, Llc Method and apparatus for managing orders in financial markets
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
US20190138210A1 (en) * 2017-11-09 2019-05-09 Nvidia Corporation Queue manager for streaming multiprocessor systems
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
CN111680336A (en) * 2020-05-29 2020-09-18 绿晶半导体科技(北京)有限公司 Firmware safety protection method, device, system and equipment
US10846624B2 (en) 2016-12-22 2020-11-24 Ip Reservoir, Llc Method and apparatus for hardware-accelerated machine learning
US10909623B2 (en) 2002-05-21 2021-02-02 Ip Reservoir, Llc Method and apparatus for processing financial information at hardware speeds using FPGA devices
US10956346B1 (en) * 2017-01-13 2021-03-23 Lightbits Labs Ltd. Storage system having an in-line hardware accelerator
CN113552999A (en) * 2020-04-01 2021-10-26 株式会社日立制作所 Storage device
US11221778B1 (en) * 2019-04-02 2022-01-11 Pure Storage, Inc. Preparing data for deduplication
US20220129430A1 (en) * 2019-04-29 2022-04-28 Hitachi Vantara Llc Optimizing storage and retrieval of compressed data
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030191876A1 (en) * 2000-02-03 2003-10-09 Fallon James J. Data storewidth accelerator
US7831491B2 (en) 2003-11-05 2010-11-09 Chicago Mercantile Exchange Inc. Market data message format
US20050096999A1 (en) * 2003-11-05 2005-05-05 Chicago Mercantile Exchange Trade engine processing of mass quote messages and resulting production of market data
US8665955B2 (en) * 2004-06-11 2014-03-04 Nxp, B.V. Method of storing pictures in a memory using compression coding and cost function including power consumption
FI120422B (en) * 2007-07-02 2009-10-15 Tellabs Oy Method and apparatus for compressing a change log using flash transactions
US7739440B2 (en) * 2007-08-16 2010-06-15 Texas Instruments Incorporated ATA HDD interface for personal media player with increased data transfer throughput
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7916728B1 (en) 2007-09-28 2011-03-29 F5 Networks, Inc. Lockless atomic table update
US8312210B2 (en) * 2008-01-03 2012-11-13 Michael Thomas Benhase Apparatus, system, and method for storing and retrieving compressed data
US8306036B1 (en) 2008-06-20 2012-11-06 F5 Networks, Inc. Methods and systems for hierarchical resource allocation through bookmark allocation
US8769681B1 (en) 2008-08-11 2014-07-01 F5 Networks, Inc. Methods and system for DMA based distributed denial of service protection
US7844766B1 (en) * 2008-10-03 2010-11-30 XETA Technologies, Inc. System and method for location specific computer enabled services/monitoring
US8447884B1 (en) 2008-12-01 2013-05-21 F5 Networks, Inc. Methods for mapping virtual addresses to physical addresses in a network device and systems thereof
US8880696B1 (en) 2009-01-16 2014-11-04 F5 Networks, Inc. Methods for sharing bandwidth across a packetized bus and systems thereof
US8103809B1 (en) 2009-01-16 2012-01-24 F5 Networks, Inc. Network devices with multiple direct memory access channels and methods thereof
US9152483B2 (en) 2009-01-16 2015-10-06 F5 Networks, Inc. Network devices with multiple fully isolated and independently resettable direct memory access channels and methods thereof
US8112491B1 (en) 2009-01-16 2012-02-07 F5 Networks, Inc. Methods and systems for providing direct DMA
US8880632B1 (en) 2009-01-16 2014-11-04 F5 Networks, Inc. Method and apparatus for performing multiple DMA channel based network quality of service
US20110202150A1 (en) * 2009-10-16 2011-08-18 Newport Controls Controller system adapted for SPA
US20110093099A1 (en) * 2009-10-16 2011-04-21 Newport Controls Controller system adapted for spa
US9313047B2 (en) 2009-11-06 2016-04-12 F5 Networks, Inc. Handling high throughput and low latency network data packets in a traffic management device
US10732837B2 (en) * 2010-02-08 2020-08-04 International Business Machines Corporation Pseudo-volume for control and statistics of a storage controller
US20110225408A1 (en) * 2010-03-10 2011-09-15 Ren Guo Cache boot mechanism
KR101643273B1 (en) * 2010-04-09 2016-08-01 삼성전자주식회사 Method of storing data in storage media, data storage device using the same, and system including the same
US8683270B2 (en) * 2010-04-29 2014-03-25 Micron Technology, Inc. Signal line to indicate program-fail in memory
US10135831B2 (en) 2011-01-28 2018-11-20 F5 Networks, Inc. System and method for combining an access control system with a traffic management system
US9036822B1 (en) 2012-02-15 2015-05-19 F5 Networks, Inc. Methods for managing user information and devices thereof
US10033837B1 (en) 2012-09-29 2018-07-24 F5 Networks, Inc. System and method for utilizing a data reducing module for dictionary compression of encoded data
US9270602B1 (en) 2012-12-31 2016-02-23 F5 Networks, Inc. Transmit rate pacing of large network traffic bursts to reduce jitter, buffer overrun, wasted bandwidth, and retransmissions
US10375155B1 (en) 2013-02-19 2019-08-06 F5 Networks, Inc. System and method for achieving hardware acceleration for asymmetric flow connections
KR101978178B1 (en) * 2013-05-24 2019-05-15 삼성전자주식회사 Apparatus and method for processing ultrasonic data
US9864606B2 (en) 2013-09-05 2018-01-09 F5 Networks, Inc. Methods for configurable hardware logic device reloading and devices thereof
EP3085051A1 (en) 2013-12-16 2016-10-26 F5 Networks, Inc Methods for facilitating improved user authentication using persistent data and devices thereof
US9990298B2 (en) * 2014-05-12 2018-06-05 Western Digital Technologies, Inc System and method for caching solid state device read request results
US10015143B1 (en) 2014-06-05 2018-07-03 F5 Networks, Inc. Methods for securing one or more license entitlement grants and devices thereof
US11838851B1 (en) 2014-07-15 2023-12-05 F5, Inc. Methods for managing L7 traffic classification and devices thereof
US10182013B1 (en) 2014-12-01 2019-01-15 F5 Networks, Inc. Methods for managing progressive image delivery and devices thereof
US9952979B1 (en) * 2015-01-14 2018-04-24 Cavium, Inc. Methods and systems for direct memory access operations
US11895138B1 (en) 2015-02-02 2024-02-06 F5, Inc. Methods for improving web scanner accuracy and devices thereof
CN105182377B (en) * 2015-08-21 2018-06-19 上海海积信息科技股份有限公司 A kind of receiver board and receiver
US11164248B2 (en) 2015-10-12 2021-11-02 Chicago Mercantile Exchange Inc. Multi-modal trade execution with smart order routing
US11288739B2 (en) 2015-10-12 2022-03-29 Chicago Mercantile Exchange Inc. Central limit order book automatic triangulation system
US10346043B2 (en) 2015-12-28 2019-07-09 Pure Storage, Inc. Adaptive computing for data compression
US10133505B1 (en) * 2016-09-29 2018-11-20 EMC IP Holding Company LLC Cooperative host and data storage system services for compression and encryption
US10972453B1 (en) 2017-05-03 2021-04-06 F5 Networks, Inc. Methods for token refreshment based on single sign-on (SSO) for federated identity environments and devices thereof
US11855898B1 (en) 2018-03-14 2023-12-26 F5, Inc. Methods for traffic dependent direct memory access optimization and devices thereof
US10587287B2 (en) 2018-03-28 2020-03-10 International Business Machines Corporation Computer system supporting multiple encodings with static data support
US10720941B2 (en) 2018-04-09 2020-07-21 International Business Machines Corporation Computer system supporting migration between hardware accelerators through software interfaces
US10587284B2 (en) 2018-04-09 2020-03-10 International Business Machines Corporation Multi-mode compression acceleration
US11537716B1 (en) 2018-11-13 2022-12-27 F5, Inc. Methods for detecting changes to a firmware and devices thereof
US11791838B2 (en) 2021-01-15 2023-10-17 Samsung Electronics Co., Ltd. Near-storage acceleration of dictionary decoding

Citations (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593324A (en) * 1981-04-14 1986-06-03 Fuji Xerox Co., Ltd. Image data storing device
US4754351A (en) * 1984-08-22 1988-06-28 Maxtor Corporation Method and apparatus for controlling radial disk displacement in Winchester disk drives
US4804959A (en) * 1987-11-10 1989-02-14 International Business Machines Corporation Method and apparatus using multiple codes to increase storage capacity
US4929946A (en) * 1989-02-09 1990-05-29 Storage Technology Corporation Adaptive data compression apparatus including run length encoding for a tape drive system
US4988998A (en) * 1989-09-05 1991-01-29 Storage Technology Corporation Data compression system for successively applying at least two data compression methods to an input data stream
US5091782A (en) * 1990-04-09 1992-02-25 General Instrument Corporation Apparatus and method for adaptively compressing successive blocks of digital video
US5097261A (en) * 1989-11-22 1992-03-17 International Business Machines Corporation Data compression for recording on a record medium
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
US5121342A (en) * 1989-08-28 1992-06-09 Network Communications Corporation Apparatus for analyzing communication networks
US5179651A (en) * 1988-11-08 1993-01-12 Massachusetts General Hospital Apparatus for retrieval and processing of selected archived images for display at workstation terminals
US5209220A (en) * 1989-10-05 1993-05-11 Olympus Optical Co., Ltd. Endoscope image data compressing apparatus
US5212742A (en) * 1991-05-24 1993-05-18 Apple Computer, Inc. Method and apparatus for encoding/decoding image data
US5287420A (en) * 1992-04-08 1994-02-15 Supermac Technology Method for image compression on a personal computer
US5293379A (en) * 1991-04-22 1994-03-08 Gandalf Technologies, Inc. Packet-based data compression method
US5379036A (en) * 1992-04-01 1995-01-03 Storer; James A. Method and apparatus for data compression
US5381145A (en) * 1993-02-10 1995-01-10 Ricoh Corporation Method and apparatus for parallel decoding and encoding of data
US5379757A (en) * 1990-08-28 1995-01-10 Olympus Optical Co. Ltd. Method of compressing endoscope image data based on image characteristics
US5389922A (en) * 1993-04-13 1995-02-14 Hewlett-Packard Company Compression using small dictionaries with applications to network packets
US5394534A (en) * 1992-09-11 1995-02-28 International Business Machines Corporation Data compression/decompression and storage of compressed and uncompressed data on a same removable data storage medium
US5396228A (en) * 1992-01-16 1995-03-07 Mobile Telecommunications Technologies Methods and apparatus for compressing and decompressing paging data
US5400401A (en) * 1992-10-30 1995-03-21 Scientific Atlanta, Inc. System and method for transmitting a plurality of digital services
US5403639A (en) * 1992-09-02 1995-04-04 Storage Technology Corporation File server having snapshot application data groups
US5412384A (en) * 1993-04-16 1995-05-02 International Business Machines Corporation Method and system for adaptively building a static Ziv-Lempel dictionary for database compression
US5414850A (en) * 1991-08-23 1995-05-09 Stac Electronics, Inc. System for transparently compressing data files in a computer system
US5420639A (en) * 1993-04-01 1995-05-30 Scientific-Atlanta, Inc. Rate adaptive huffman coding
US5483470A (en) * 1990-03-06 1996-01-09 At&T Corp. Timing verification by successive approximation
US5486826A (en) * 1994-05-19 1996-01-23 Ps Venture 1 Llc Method and apparatus for iterative compression of digital data
US5495244A (en) * 1991-12-07 1996-02-27 Samsung Electronics Co., Ltd. Device for encoding and decoding transmission signals through adaptive selection of transforming methods
US5506872A (en) * 1994-04-26 1996-04-09 At&T Corp. Dynamic compression-rate selection arrangement
US5528628A (en) * 1994-11-26 1996-06-18 Samsung Electronics Co., Ltd. Apparatus for variable-length coding and variable-length-decoding using a plurality of Huffman coding tables
US5596674A (en) * 1992-06-24 1997-01-21 Sony Corporation State machine apparatus and methods for encoding data in serial form and decoding using multiple tables
US5611024A (en) * 1992-08-28 1997-03-11 Compaq Computer Corporation Data compression of bit map images
US5613069A (en) * 1994-12-16 1997-03-18 Tony Walker Non-blocking packet switching network with dynamic routing codes having incoming packets diverted and temporarily stored in processor inputs when network ouput is not available
US5627534A (en) * 1995-03-23 1997-05-06 International Business Machines Corporation Dual stage compression of bit mapped image data using refined run length and LZ compression
US5635632A (en) * 1994-04-26 1997-06-03 Cytec Technology Corp. Settling process analysis device and method
US5635932A (en) * 1994-10-17 1997-06-03 Fujitsu Limited Lempel-ziv compression with expulsion of dictionary buffer matches
US5638498A (en) * 1992-11-10 1997-06-10 Adobe Systems Incorporated Method and apparatus for reducing storage requirements for display data
US5640158A (en) * 1994-09-14 1997-06-17 Seiko Epson Corporation Reversible method of encoding data
US5642506A (en) * 1994-12-14 1997-06-24 International Business Machines Corporation Method and apparatus for initializing a multiprocessor system
US5717393A (en) * 1996-02-08 1998-02-10 Fujitsu Limited Apparatus for data compression and data decompression
US5717394A (en) * 1993-02-10 1998-02-10 Ricoh Company Ltd. Method and apparatus for encoding and decoding data
US5719862A (en) * 1996-05-14 1998-02-17 Pericom Semiconductor Corp. Packet-based dynamic de-skewing for network switch with local or central clock
US5729228A (en) * 1995-07-06 1998-03-17 International Business Machines Corp. Parallel compression and decompression using a cooperative dictionary
US5748904A (en) * 1996-09-13 1998-05-05 Silicon Integrated Systems Corp. Method and system for segment encoded graphic data compression
US5767898A (en) * 1994-06-23 1998-06-16 Sanyo Electric Co., Ltd. Three-dimensional image coding by merger of left and right images
US5771340A (en) * 1994-01-14 1998-06-23 Oki Electric Industry Co., Ltd. Data compression method and print processing device utilizing the same
US5861920A (en) * 1996-11-08 1999-01-19 Hughes Electronics Corporation Hierarchical low latency video compression
US5861824A (en) * 1995-06-20 1999-01-19 Ricoh Company, Ltd. Encoding method and system, and decoding method and system
US5864342A (en) * 1995-08-04 1999-01-26 Microsoft Corporation Method and system for rendering graphical objects to image chunks
US5867167A (en) * 1995-08-04 1999-02-02 Sun Microsystems, Inc. Compression of three-dimensional graphics data including quantization, delta-encoding, and variable-length encoding
US5867602A (en) * 1994-09-21 1999-02-02 Ricoh Corporation Reversible wavelet transform and embedded codestream manipulation
US5917438A (en) * 1995-06-30 1999-06-29 Victor Company Of Japan, Ltd. Data storing and outputting apparatus
US6014694A (en) * 1997-06-26 2000-01-11 Citrix Systems, Inc. System for adaptive video/audio transport over a network
US6031939A (en) * 1997-03-17 2000-02-29 Alcatel Method of optimizing the compression of image data, with automatic selection of compression conditions
US6169241B1 (en) * 1997-03-03 2001-01-02 Yamaha Corporation Sound source with free compression and expansion of voice independently of pitch
US6172936B1 (en) * 1998-05-28 2001-01-09 Fujitsu Limited Memory circuit
US6182125B1 (en) * 1998-10-13 2001-01-30 3Com Corporation Methods for determining sendable information content based on a determined network latency
US6192082B1 (en) * 1998-11-13 2001-02-20 Compaq Computer Corporation Digital television data format conversion with automatic parity detection
US6195465B1 (en) * 1994-09-21 2001-02-27 Ricoh Company, Ltd. Method and apparatus for compression using reversible wavelet transforms and an embedded codestream
US6195024B1 (en) * 1998-12-11 2001-02-27 Realtime Data, Llc Content independent data compression method and system
US6222886B1 (en) * 1996-06-24 2001-04-24 Kabushiki Kaisha Toshiba Compression based reduced memory video decoder
US6225922B1 (en) * 1998-03-16 2001-05-01 Hewlett-Packard Company System and method for compressing data using adaptive field encoding
US6345307B1 (en) * 1999-04-30 2002-02-05 General Instrument Corporation Method and apparatus for compressing hypertext transfer protocol (HTTP) messages
US6392567B2 (en) * 2000-03-31 2002-05-21 Fijitsu Limited Apparatus for repeatedly compressing a data string and a method thereof
US6404931B1 (en) * 1998-12-14 2002-06-11 Microsoft Corporation Code book construction for variable to variable length entropy encoding
US20020080871A1 (en) * 2000-10-03 2002-06-27 Realtime Data, Llc System and method for data feed acceleration and encryption
US6513113B1 (en) * 1998-06-19 2003-01-28 Ricoh Company, Ltd. Electronic instrument adapted to be selectively booted either from externally-connectable storage unit or from internal nonvolatile rewritable memory
US20030030575A1 (en) * 2001-05-07 2003-02-13 Harmonic Data Systems Ltd. Lossless data compression
US20030034905A1 (en) * 2001-05-17 2003-02-20 Cyber Operations, Llc System and method for encoding and decoding data files
US6529633B1 (en) * 1998-09-16 2003-03-04 Texas Instruments Incorporated Parallel difference coding method for lossless compression and real time decompression
US6532121B1 (en) * 1999-10-25 2003-03-11 Hewlett-Packard Company Compression algorithm with embedded meta-data for partial record operation augmented with expansion joints
US20030084238A1 (en) * 1995-01-13 2003-05-01 Yoshiyuki Okada Storage control apparatus and method for compressing data for disk storage
US20030090397A1 (en) * 2001-11-14 2003-05-15 Rasmussen Brent D. Data compression/decompression system
US20040042506A1 (en) * 2000-10-03 2004-03-04 Realtime Data, Llc System and method for data feed acceleration and encryption
US20040052038A1 (en) * 2002-09-12 2004-03-18 Wei-Chung Wu Stand for a flat panel display
US6711709B1 (en) * 1998-06-24 2004-03-23 Unisys Corporation Integrated block checking system for rapid file transfer of compressed data
US6717534B2 (en) * 2002-01-18 2004-04-06 Fuji Xerox Co., Ltd. Data encoding device and data decoding device
US20040073710A1 (en) * 1999-03-11 2004-04-15 Fallon James J. System and methods for accelerated data storage and retrieval
US6731814B2 (en) * 2000-05-01 2004-05-04 Xerox Corporation Method for compressing digital documents with control of image quality and compression rate
US6885319B2 (en) * 1999-01-29 2005-04-26 Quickshift, Inc. System and method for generating optimally compressed data from a plurality of data compression/decompression engines implementing different data compression algorithms
US6885316B2 (en) * 2001-02-05 2005-04-26 Carsten Mehring System and method for keyboard independent touch typing
US7161506B2 (en) * 1998-12-11 2007-01-09 Realtime Data Llc Systems and methods for data compression such as content dependent data compression
US7181608B2 (en) * 2000-02-03 2007-02-20 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US20070050514A1 (en) * 1999-03-11 2007-03-01 Realtime Data Llc System and methods for accelerated data storage and retrieval
US7190284B1 (en) * 1994-11-16 2007-03-13 Dye Thomas A Selective lossless, lossy, or no compression of data based on address range, data type, and/or requesting agent
US7376772B2 (en) * 2000-02-03 2008-05-20 Realtime Data Llc Data storewidth accelerator

Family Cites Families (146)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3490690A (en) * 1964-10-26 1970-01-20 Ibm Data reduction system
US4302775A (en) 1978-12-15 1981-11-24 Compression Labs, Inc. Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback
US4394774A (en) 1978-12-15 1983-07-19 Compression Labs, Inc. Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback
US4494108A (en) * 1981-11-09 1985-01-15 International Business Machines Corporation Adaptive source modeling for data file compression within bounded memory
US4499499A (en) * 1982-12-29 1985-02-12 International Business Machines Corporation Method for identification and compression of facsimile symbols in text processing systems
US4574351A (en) 1983-03-03 1986-03-04 International Business Machines Corporation Apparatus for compressing and buffering data
US4814746A (en) * 1983-06-01 1989-03-21 International Business Machines Corporation Data compression method
US5045848A (en) 1984-04-10 1991-09-03 Fnn Method of encoding market data and transmitting by radio to a plurality of receivers
US4646061A (en) * 1985-03-13 1987-02-24 Racal Data Communications Inc. Data communication with modified Huffman coding
US4682150A (en) 1985-12-09 1987-07-21 Ncr Corporation Data compression method and apparatus
US5247646A (en) 1986-05-15 1993-09-21 Aquidneck Systems International, Inc. Compressed data optical disk storage system
US4730348A (en) 1986-09-19 1988-03-08 Adaptive Computer Technologies Adaptive data compression system
US4813040A (en) * 1986-10-31 1989-03-14 Futato Steven P Method and apparatus for transmitting digital data and real-time digitalized voice information over a communications channel
US4906995A (en) 1986-12-12 1990-03-06 Sangamo Weston, Inc. Data compression apparatus and method for data recorder
JPH0815263B2 (en) 1986-12-12 1996-02-14 株式会社日立製作所 Data compression / decompression method
US4965675A (en) 1987-05-15 1990-10-23 Canon Kabushiki Kaisha Method and apparatus for after-recording sound on a medium having pre-recorded video thereon
US4729020A (en) * 1987-06-01 1988-03-01 Delta Information Systems System for formatting digital signals to be transmitted
US5079630A (en) * 1987-10-05 1992-01-07 Intel Corporation Adaptive video compression system
US4876541A (en) 1987-10-15 1989-10-24 Data Compression Corporation Stem for dynamically compressing and decompressing electronic data
US4870415A (en) 1987-10-19 1989-09-26 Hewlett-Packard Company Data compression system with expansion protection
US4888812A (en) 1987-12-18 1989-12-19 International Business Machines Corporation Document image processing system
US4897717A (en) * 1988-03-30 1990-01-30 Starsignal, Inc. Computer-based video compression system
US4906991A (en) * 1988-04-29 1990-03-06 Xerox Corporation Textual substitution data compression with finite length search windows
US5046027A (en) 1988-11-08 1991-09-03 Massachusetts General Hospital Apparatus and method for processing and displaying images in a digital procesor based system
US5187793A (en) 1989-01-09 1993-02-16 Intel Corporation Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache
US5003307A (en) * 1989-01-13 1991-03-26 Stac, Inc. Data compression apparatus with shift register search means
EP0418396B1 (en) 1989-03-16 1998-06-03 Fujitsu Limited Video/audio multiplex transmission system
IL91221A (en) 1989-08-04 1995-03-30 Ibm Israel Method for the compression of binary text
US5191431A (en) 1989-08-29 1993-03-02 Canon Kabushiki Kaisha Recording apparatus having plural operating modes involving diverse signal compression rates and different apportioning of pilot signal recording area
US5028922A (en) 1989-10-30 1991-07-02 Industrial Technology Research Institute Multiplexed encoder and decoder with address mark generation/check and precompensation circuits
GB9001335D0 (en) * 1990-01-19 1990-03-21 Hewlett Packard Ltd Data storage on tape
GB9001312D0 (en) * 1990-01-19 1990-03-21 Hewlett Packard Ltd Storage of compressed data
US5270832A (en) 1990-03-14 1993-12-14 C-Cube Microsystems System for compression and decompression of video data using discrete cosine transform and coding techniques
US5045852A (en) 1990-03-30 1991-09-03 International Business Machines Corporation Dynamic model selection during data compression
US5309555A (en) 1990-05-15 1994-05-03 International Business Machines Corporation Realtime communication of hand drawn images in a multiprogramming window environment
US5237675A (en) 1990-06-04 1993-08-17 Maxtor Corporation Apparatus and method for efficient organization of compressed data on a hard disk utilizing an estimated compression factor
US5049881A (en) 1990-06-18 1991-09-17 Intersecting Concepts, Inc. Apparatus and method for very high data rate-compression incorporating lossless data compression and expansion utilizing a hashing technique
US5247638A (en) 1990-06-18 1993-09-21 Storage Technology Corporation Apparatus for compressing data in a dynamically mapped virtual data storage subsystem
US5307497A (en) 1990-06-25 1994-04-26 International Business Machines Corp. Disk operating system loadable from read only memory using installable file system interface
US5226176A (en) 1990-08-20 1993-07-06 Microsystems, Inc. System for selectively aborting operation or waiting to load required data based upon user response to non-availability of network load device
US5227893A (en) 1990-10-31 1993-07-13 International Business Machines Corporation Pseudo-bar code control of image transmission
US5627995A (en) 1990-12-14 1997-05-06 Alfred P. Gnadinger Data compression and decompression using memory spaces of more than one size
US5237460A (en) 1990-12-14 1993-08-17 Ceram, Inc. Storage of compressed data on random access storage devices
JPH04241681A (en) * 1991-01-16 1992-08-28 Fujitsu Ltd Storage device of compression switching system
US5150430A (en) 1991-03-15 1992-09-22 The Board Of Trustees Of The Leland Stanford Junior University Lossless data compression circuit and method
US5289580A (en) * 1991-05-10 1994-02-22 Unisys Corporation Programmable multiple I/O interface controller
US5263168A (en) 1991-06-03 1993-11-16 Motorola, Inc. Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal
US5159336A (en) 1991-08-13 1992-10-27 Iomega Corporation Tape controller with data compression and error correction sharing a common buffer
JPH0561951A (en) 1991-08-30 1993-03-12 Fujitsu Ltd Image processor
DE4229710B4 (en) 1991-09-09 2008-06-05 Samsung Electronics Co., Ltd. Digital audio data storage system and digital audio system equipped therewith
US5243341A (en) 1992-06-01 1993-09-07 Hewlett Packard Company Lempel-Ziv compression scheme with enhanced adapation
US5175543A (en) 1991-09-25 1992-12-29 Hewlett-Packard Company Dictionary reset performance enhancement for data compression applications
US5293576A (en) * 1991-11-21 1994-03-08 Motorola, Inc. Command authentication process
GB2264838B (en) 1992-02-21 1995-08-30 Samsung Electronics Co Ltd Video recording apparatus
US5355498A (en) 1992-02-25 1994-10-11 Sun Microsystems, Inc. Method and apparatus for booting a computer system without loading a device driver into memory
US5406278A (en) 1992-02-28 1995-04-11 Intersecting Concepts, Inc. Method and apparatus for data compression having an improved matching algorithm which utilizes a parallel hashing technique
US5243348A (en) 1992-04-27 1993-09-07 Motorola, Inc. Partitioned digital encoder and method for encoding bit groups in parallel
US5408542A (en) * 1992-05-12 1995-04-18 Apple Computer, Inc. Method and apparatus for real-time lossless compression and decompression of image data
WO1993023811A2 (en) 1992-05-13 1993-11-25 Southwestern Bell Technology Resources, Inc. Open architecture interface storage controller
AU4653593A (en) 1992-06-25 1994-01-24 Teledata Solutions, Inc. Call distributor
JPH0628108A (en) 1992-07-09 1994-02-04 Hitachi Ltd Data storage system
US5802290A (en) * 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5406279A (en) 1992-09-02 1995-04-11 Cirrus Logic, Inc. General purpose, hash-based technique for single-pass lossless data compression
US5479587A (en) 1992-09-03 1995-12-26 Hewlett-Packard Company Page printer having adaptive data compression for memory minimization
US5590306A (en) 1992-09-08 1996-12-31 Fuji Photo Film Co., Ltd. Memory card management system for writing data with usage and recording codes made significant
US5357614A (en) 1992-09-17 1994-10-18 Rexon/Tecmar, Inc. Data compression controller
US5557749A (en) 1992-10-15 1996-09-17 Intel Corporation System for automatically compressing and decompressing data for sender and receiver processes upon determination of a common compression/decompression method understood by both sender and receiver processes
US5467087A (en) 1992-12-18 1995-11-14 Apple Computer, Inc. High speed lossless data compression system
US5583500A (en) 1993-02-10 1996-12-10 Ricoh Corporation Method and apparatus for parallel encoding and decoding of data
US5533051A (en) 1993-03-12 1996-07-02 The James Group Method for data compression
GB2280566B (en) 1993-07-30 1997-06-11 Sony Uk Ltd Video data compression
US5610657A (en) * 1993-09-14 1997-03-11 Envistech Inc. Video compression using an iterative error data coding method
US5452287A (en) 1993-09-20 1995-09-19 Motorola, Inc. Method of negotiation of protocols, classes, and options in computer and communication networks providing mixed packet, frame, cell, and circuit services
EP0651314A1 (en) 1993-10-27 1995-05-03 International Business Machines Corporation An apparatus and method for thermally protecting a processing device
JP3161189B2 (en) * 1993-12-03 2001-04-25 株式会社日立製作所 Storage system
US5488364A (en) * 1994-02-28 1996-01-30 Sam H. Eulmi Recursive data compression
US5488365A (en) * 1994-03-01 1996-01-30 Hewlett-Packard Company Method and apparatus for compressing and decompressing short blocks of data
US5563961A (en) 1994-03-03 1996-10-08 Radius Inc. Video data compression method and system which measures compressed data storage time to optimize compression rate
US5629732A (en) 1994-03-29 1997-05-13 The Trustees Of Columbia University In The City Of New York Viewer controllable on-demand multimedia service
US5574952A (en) 1994-05-11 1996-11-12 International Business Machines Corporation Data storage system and method for operating a disk controller including allocating disk space for compressed data
US6031937A (en) * 1994-05-19 2000-02-29 Next Software, Inc. Method and apparatus for video compression using block and wavelet techniques
US5506844A (en) 1994-05-20 1996-04-09 Compression Labs, Inc. Method for configuring a statistical multiplexer to dynamically allocate communication channel bandwidth
US5574953A (en) 1994-08-19 1996-11-12 Hewlett-Packard Company Storing compressed data in non-contiguous memory
US6549666B1 (en) * 1994-09-21 2003-04-15 Ricoh Company, Ltd Reversible embedded wavelet system implementation
US5604824A (en) 1994-09-22 1997-02-18 Houston Advanced Research Center Method and apparatus for compression and decompression of documents and the like using splines and spline-wavelets
US5561824A (en) 1994-10-04 1996-10-01 International Business Machines Corporation Storage management of data for ensuring communication of minimal length data
JPH08116534A (en) * 1994-10-18 1996-05-07 Seiko Epson Corp Image data coder, its method, image data encoder and its method
US5652795A (en) * 1994-11-14 1997-07-29 Hughes Electronics Method and apparatus for an adapter card providing conditional access in a communication system
US6002411A (en) * 1994-11-16 1999-12-14 Interactive Silicon, Inc. Integrated video and memory controller with data processing and graphical processing capabilities
US6170047B1 (en) * 1994-11-16 2001-01-02 Interactive Silicon, Inc. System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities
US5684478A (en) * 1994-12-06 1997-11-04 Cennoid Technologies, Inc. Method and apparatus for adaptive data compression
US5870036A (en) * 1995-02-24 1999-02-09 International Business Machines Corporation Adaptive multiple dictionary data compression
JP3749752B2 (en) * 1995-03-24 2006-03-01 アイティーティー・マニュファクチャリング・エンタープライジズ・インコーポレーテッド Block adaptive differential pulse code modulation system
US5655138A (en) * 1995-04-11 1997-08-05 Elonex I. P. Holdings Apparatus and method for peripheral device control with integrated data compression
US5724475A (en) * 1995-05-18 1998-03-03 Kirsten; Jeff P. Compressed digital video reload and playback system
US5623701A (en) 1995-06-06 1997-04-22 International Business Machines Corporation Data compression method and structure for a direct access storage device
US5537658A (en) 1995-06-07 1996-07-16 International Business Machines Corporation Distributed directory method and structure for direct access storage device (DASD) data compression
US5825830A (en) * 1995-08-17 1998-10-20 Kopf; David A. Method and apparatus for the compression of audio, video or other data
TW439380B (en) * 1995-10-09 2001-06-07 Hitachi Ltd Terminal apparatus
US5799110A (en) * 1995-11-09 1998-08-25 Utah State University Foundation Hierarchical adaptive multistage vector quantization
US6021433A (en) * 1996-01-26 2000-02-01 Wireless Internet, Inc. System and method for transmission of data
JP3277792B2 (en) * 1996-01-31 2002-04-22 株式会社日立製作所 Data compression method and apparatus
US6618728B1 (en) * 1996-01-31 2003-09-09 Electronic Data Systems Corporation Multi-process compression
US5818369A (en) * 1996-03-07 1998-10-06 Pegasus Imaging Corporation Rapid entropy coding for data compression or decompression
US5987590A (en) * 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods
JP3977426B2 (en) * 1996-04-18 2007-09-19 ノキア コーポレイション Video data encoder and decoder
US5864678A (en) * 1996-05-08 1999-01-26 Apple Computer, Inc. System for detecting and reporting data flow imbalance between computers using grab rate outflow rate arrival rate and play rate
US6026217A (en) * 1996-06-21 2000-02-15 Digital Equipment Corporation Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition storage and retrieval
US6175856B1 (en) * 1996-09-30 2001-01-16 Apple Computer, Inc. Method and apparatus for dynamic selection of compression processing during teleconference call initiation
US5956487A (en) * 1996-10-25 1999-09-21 Hewlett-Packard Company Embedding web access mechanism in an appliance for user interface functions including a web server and web browser
US5974235A (en) * 1996-10-31 1999-10-26 Sensormatic Electronics Corporation Apparatus having flexible capabilities for analysis of video information
US5870087A (en) * 1996-11-13 1999-02-09 Lsi Logic Corporation MPEG decoder system and method having a unified memory for transport decode and system controller functions
US6185625B1 (en) * 1996-12-20 2001-02-06 Intel Corporation Scaling proxy server sending to the client a graphical user interface for establishing object encoding preferences after receiving the client's request for the object
US5920326A (en) * 1997-05-30 1999-07-06 Hewlett Packard Company Caching and coherency control of multiple geometry accelerators in a computer graphics system
US6028725A (en) * 1997-06-30 2000-02-22 Emc Corporation Method and apparatus for increasing disc drive performance
US6032148A (en) * 1997-09-15 2000-02-29 Hewlett-Packard Company Multilevel storage system with hybrid data compression
US5874907A (en) * 1997-09-19 1999-02-23 International Business Machines Corporation Method and apparatus for providing improved data compression efficiency for an adaptive data compressor
US6032197A (en) * 1997-09-25 2000-02-29 Microsoft Corporation Data packet header compression for unidirectional transmission
US6138164A (en) * 1997-11-14 2000-10-24 E-Parcel, Llc System for minimizing screen refresh time using selectable compression speeds
US6105130A (en) * 1997-12-23 2000-08-15 Adaptec, Inc. Method for selectively booting from a desired peripheral device
US6279045B1 (en) * 1997-12-29 2001-08-21 Kawasaki Steel Corporation Multimedia interface having a multimedia processor and a field programmable gate array
US6175650B1 (en) * 1998-01-26 2001-01-16 Xerox Corporation Adaptive quantization compatible with the JPEG baseline sequential mode
US6421387B1 (en) * 1998-05-15 2002-07-16 North Carolina State University Methods and systems for forward error correction based loss recovery for interactive video transmission
US6192155B1 (en) * 1998-09-16 2001-02-20 Xerox Corporation Systems and methods for reducing boundary artifacts in hybrid compression
US6272627B1 (en) * 1998-10-30 2001-08-07 Ati International Srl Method and apparatus for booting up a computing system with enhanced graphics
US6282641B1 (en) * 1998-11-18 2001-08-28 Phoenix Technologies Ltd. System for reconfiguring a boot device by swapping the logical device number of a user selected boot drive to a currently configured boot drive
US6272628B1 (en) * 1998-12-14 2001-08-07 International Business Machines Corporation Boot code verification and recovery
US6434695B1 (en) * 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6185659B1 (en) * 1999-03-23 2001-02-06 Storage Technology Corporation Adapting resource use to improve performance in a caching memory system
US6609223B1 (en) * 1999-04-06 2003-08-19 Kencast, Inc. Method for packet-level fec encoding, in which on a source packet-by-source packet basis, the error correction contributions of a source packet to a plurality of wildcard packets are computed, and the source packet is transmitted thereafter
US6071777A (en) * 1999-04-29 2000-06-06 Winbond Electronics Corporation Method for a self-aligned select gate for a split-gate flash memory structure
US7007099B1 (en) * 1999-05-03 2006-02-28 Lucent Technologies Inc. High speed multi-port serial-to-PCI bus interface
US6308311B1 (en) * 1999-05-14 2001-10-23 Xilinx, Inc. Method for reconfiguring a field programmable gate array from a host
US6449682B1 (en) * 1999-06-18 2002-09-10 Phoenix Technologies Ltd. System and method for inserting one or more files onto mass storage
US6851047B1 (en) * 1999-10-15 2005-02-01 Xilinx, Inc. Configuration in a configurable system on a chip
US6452602B1 (en) * 1999-12-13 2002-09-17 Ati International Srl Method and apparatus for storing compressed data
WO2001046892A1 (en) * 1999-12-23 2001-06-28 Concept Shopping, Inc. Techniques for optimizing promotion delivery
US6523102B1 (en) * 2000-04-14 2003-02-18 Interactive Silicon, Inc. Parallel compression/decompression system and method for implementation of in-memory compressed cache improving storage density and access speed for industry standard memory subsystems and in-line memory modules
US6856651B2 (en) * 2000-07-25 2005-02-15 Peribit Networks, Inc. System and method for incremental and continuous data compression
US7319667B1 (en) * 2000-11-15 2008-01-15 Cisco Technology, Inc. Communication system with priority data compression
EP1215096B1 (en) * 2000-12-14 2011-04-06 Sumitomo Rubber Industries, Ltd. Apparatus and method for identifying tires and apparatus and method for evaluating road surface conditions
US6606040B2 (en) * 2001-02-13 2003-08-12 Mosaid Technologies, Inc. Method and apparatus for adaptive data compression
US6756922B2 (en) * 2001-05-21 2004-06-29 International Business Machines Corporation Method and system for compression of a set of mostly similar strings allowing fast retrieval
US6944740B2 (en) * 2002-03-27 2005-09-13 International Business Machines Corporation Method for performing compressed I/O with memory expansion technology
KR101143282B1 (en) * 2002-10-05 2012-05-08 디지털 파운튼, 인크. Systematic encoding and decoding of chain reaction codes
US7102544B1 (en) * 2005-05-31 2006-09-05 Altera Corporation Method and system for improving memory interface data integrity in PLDs

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593324A (en) * 1981-04-14 1986-06-03 Fuji Xerox Co., Ltd. Image data storing device
US4754351A (en) * 1984-08-22 1988-06-28 Maxtor Corporation Method and apparatus for controlling radial disk displacement in Winchester disk drives
US4804959A (en) * 1987-11-10 1989-02-14 International Business Machines Corporation Method and apparatus using multiple codes to increase storage capacity
US5179651A (en) * 1988-11-08 1993-01-12 Massachusetts General Hospital Apparatus for retrieval and processing of selected archived images for display at workstation terminals
US4929946A (en) * 1989-02-09 1990-05-29 Storage Technology Corporation Adaptive data compression apparatus including run length encoding for a tape drive system
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
US5121342A (en) * 1989-08-28 1992-06-09 Network Communications Corporation Apparatus for analyzing communication networks
US4988998A (en) * 1989-09-05 1991-01-29 Storage Technology Corporation Data compression system for successively applying at least two data compression methods to an input data stream
US5209220A (en) * 1989-10-05 1993-05-11 Olympus Optical Co., Ltd. Endoscope image data compressing apparatus
US5097261A (en) * 1989-11-22 1992-03-17 International Business Machines Corporation Data compression for recording on a record medium
US5483470A (en) * 1990-03-06 1996-01-09 At&T Corp. Timing verification by successive approximation
US5091782A (en) * 1990-04-09 1992-02-25 General Instrument Corporation Apparatus and method for adaptively compressing successive blocks of digital video
US5379757A (en) * 1990-08-28 1995-01-10 Olympus Optical Co. Ltd. Method of compressing endoscope image data based on image characteristics
US5293379A (en) * 1991-04-22 1994-03-08 Gandalf Technologies, Inc. Packet-based data compression method
US5212742A (en) * 1991-05-24 1993-05-18 Apple Computer, Inc. Method and apparatus for encoding/decoding image data
US5414850A (en) * 1991-08-23 1995-05-09 Stac Electronics, Inc. System for transparently compressing data files in a computer system
US5495244A (en) * 1991-12-07 1996-02-27 Samsung Electronics Co., Ltd. Device for encoding and decoding transmission signals through adaptive selection of transforming methods
US5396228A (en) * 1992-01-16 1995-03-07 Mobile Telecommunications Technologies Methods and apparatus for compressing and decompressing paging data
US5379036A (en) * 1992-04-01 1995-01-03 Storer; James A. Method and apparatus for data compression
US5287420A (en) * 1992-04-08 1994-02-15 Supermac Technology Method for image compression on a personal computer
US5596674A (en) * 1992-06-24 1997-01-21 Sony Corporation State machine apparatus and methods for encoding data in serial form and decoding using multiple tables
US5611024A (en) * 1992-08-28 1997-03-11 Compaq Computer Corporation Data compression of bit map images
US5403639A (en) * 1992-09-02 1995-04-04 Storage Technology Corporation File server having snapshot application data groups
US5394534A (en) * 1992-09-11 1995-02-28 International Business Machines Corporation Data compression/decompression and storage of compressed and uncompressed data on a same removable data storage medium
US5400401A (en) * 1992-10-30 1995-03-21 Scientific Atlanta, Inc. System and method for transmitting a plurality of digital services
US5638498A (en) * 1992-11-10 1997-06-10 Adobe Systems Incorporated Method and apparatus for reducing storage requirements for display data
US5381145A (en) * 1993-02-10 1995-01-10 Ricoh Corporation Method and apparatus for parallel decoding and encoding of data
US5717394A (en) * 1993-02-10 1998-02-10 Ricoh Company Ltd. Method and apparatus for encoding and decoding data
US5420639A (en) * 1993-04-01 1995-05-30 Scientific-Atlanta, Inc. Rate adaptive huffman coding
US5389922A (en) * 1993-04-13 1995-02-14 Hewlett-Packard Company Compression using small dictionaries with applications to network packets
US5412384A (en) * 1993-04-16 1995-05-02 International Business Machines Corporation Method and system for adaptively building a static Ziv-Lempel dictionary for database compression
US5771340A (en) * 1994-01-14 1998-06-23 Oki Electric Industry Co., Ltd. Data compression method and print processing device utilizing the same
US5506872A (en) * 1994-04-26 1996-04-09 At&T Corp. Dynamic compression-rate selection arrangement
US5635632A (en) * 1994-04-26 1997-06-03 Cytec Technology Corp. Settling process analysis device and method
US5486826A (en) * 1994-05-19 1996-01-23 Ps Venture 1 Llc Method and apparatus for iterative compression of digital data
US5767898A (en) * 1994-06-23 1998-06-16 Sanyo Electric Co., Ltd. Three-dimensional image coding by merger of left and right images
US5640158A (en) * 1994-09-14 1997-06-17 Seiko Epson Corporation Reversible method of encoding data
US5867602A (en) * 1994-09-21 1999-02-02 Ricoh Corporation Reversible wavelet transform and embedded codestream manipulation
US6195465B1 (en) * 1994-09-21 2001-02-27 Ricoh Company, Ltd. Method and apparatus for compression using reversible wavelet transforms and an embedded codestream
US5635932A (en) * 1994-10-17 1997-06-03 Fujitsu Limited Lempel-ziv compression with expulsion of dictionary buffer matches
US7190284B1 (en) * 1994-11-16 2007-03-13 Dye Thomas A Selective lossless, lossy, or no compression of data based on address range, data type, and/or requesting agent
US5528628A (en) * 1994-11-26 1996-06-18 Samsung Electronics Co., Ltd. Apparatus for variable-length coding and variable-length-decoding using a plurality of Huffman coding tables
US5642506A (en) * 1994-12-14 1997-06-24 International Business Machines Corporation Method and apparatus for initializing a multiprocessor system
US5613069A (en) * 1994-12-16 1997-03-18 Tony Walker Non-blocking packet switching network with dynamic routing codes having incoming packets diverted and temporarily stored in processor inputs when network ouput is not available
US20030084238A1 (en) * 1995-01-13 2003-05-01 Yoshiyuki Okada Storage control apparatus and method for compressing data for disk storage
US5627534A (en) * 1995-03-23 1997-05-06 International Business Machines Corporation Dual stage compression of bit mapped image data using refined run length and LZ compression
US5861824A (en) * 1995-06-20 1999-01-19 Ricoh Company, Ltd. Encoding method and system, and decoding method and system
US5917438A (en) * 1995-06-30 1999-06-29 Victor Company Of Japan, Ltd. Data storing and outputting apparatus
US5729228A (en) * 1995-07-06 1998-03-17 International Business Machines Corp. Parallel compression and decompression using a cooperative dictionary
US5864342A (en) * 1995-08-04 1999-01-26 Microsoft Corporation Method and system for rendering graphical objects to image chunks
US5867167A (en) * 1995-08-04 1999-02-02 Sun Microsystems, Inc. Compression of three-dimensional graphics data including quantization, delta-encoding, and variable-length encoding
US5717393A (en) * 1996-02-08 1998-02-10 Fujitsu Limited Apparatus for data compression and data decompression
US5719862A (en) * 1996-05-14 1998-02-17 Pericom Semiconductor Corp. Packet-based dynamic de-skewing for network switch with local or central clock
US6222886B1 (en) * 1996-06-24 2001-04-24 Kabushiki Kaisha Toshiba Compression based reduced memory video decoder
US5748904A (en) * 1996-09-13 1998-05-05 Silicon Integrated Systems Corp. Method and system for segment encoded graphic data compression
US5861920A (en) * 1996-11-08 1999-01-19 Hughes Electronics Corporation Hierarchical low latency video compression
US6169241B1 (en) * 1997-03-03 2001-01-02 Yamaha Corporation Sound source with free compression and expansion of voice independently of pitch
US6031939A (en) * 1997-03-17 2000-02-29 Alcatel Method of optimizing the compression of image data, with automatic selection of compression conditions
US6014694A (en) * 1997-06-26 2000-01-11 Citrix Systems, Inc. System for adaptive video/audio transport over a network
US6225922B1 (en) * 1998-03-16 2001-05-01 Hewlett-Packard Company System and method for compressing data using adaptive field encoding
US6172936B1 (en) * 1998-05-28 2001-01-09 Fujitsu Limited Memory circuit
US6513113B1 (en) * 1998-06-19 2003-01-28 Ricoh Company, Ltd. Electronic instrument adapted to be selectively booted either from externally-connectable storage unit or from internal nonvolatile rewritable memory
US6711709B1 (en) * 1998-06-24 2004-03-23 Unisys Corporation Integrated block checking system for rapid file transfer of compressed data
US6529633B1 (en) * 1998-09-16 2003-03-04 Texas Instruments Incorporated Parallel difference coding method for lossless compression and real time decompression
US6182125B1 (en) * 1998-10-13 2001-01-30 3Com Corporation Methods for determining sendable information content based on a determined network latency
US6192082B1 (en) * 1998-11-13 2001-02-20 Compaq Computer Corporation Digital television data format conversion with automatic parity detection
US20070109155A1 (en) * 1998-12-11 2007-05-17 Fallon James J Data compression systems and methods
US20070109154A1 (en) * 1998-12-11 2007-05-17 Fallon James J Data compression systems and methods
US7161506B2 (en) * 1998-12-11 2007-01-09 Realtime Data Llc Systems and methods for data compression such as content dependent data compression
US7378992B2 (en) * 1998-12-11 2008-05-27 Realtime Data Llc Content independent data compression method and system
US20070109156A1 (en) * 1998-12-11 2007-05-17 Fallon James J Data compression system and methods
US7358867B2 (en) * 1998-12-11 2008-04-15 Realtime Data Llc Content independent data compression method and system
US6195024B1 (en) * 1998-12-11 2001-02-27 Realtime Data, Llc Content independent data compression method and system
US7352300B2 (en) * 1998-12-11 2008-04-01 Realtime Data Llc Data compression systems and methods
US6404931B1 (en) * 1998-12-14 2002-06-11 Microsoft Corporation Code book construction for variable to variable length entropy encoding
US6885319B2 (en) * 1999-01-29 2005-04-26 Quickshift, Inc. System and method for generating optimally compressed data from a plurality of data compression/decompression engines implementing different data compression algorithms
US20070067483A1 (en) * 1999-03-11 2007-03-22 Realtime Data Llc System and methods for accelerated data storage and retrieval
US20060015650A1 (en) * 1999-03-11 2006-01-19 Fallon James J System and methods for accelerated data storage and retrieval
US20070050515A1 (en) * 1999-03-11 2007-03-01 Realtime Data Llc System and methods for accelerated data storage and retrieval
US20040073710A1 (en) * 1999-03-11 2004-04-15 Fallon James J. System and methods for accelerated data storage and retrieval
US20070050514A1 (en) * 1999-03-11 2007-03-01 Realtime Data Llc System and methods for accelerated data storage and retrieval
US7321937B2 (en) * 1999-03-11 2008-01-22 Realtime Data Llc System and methods for accelerated data storage and retrieval
US6345307B1 (en) * 1999-04-30 2002-02-05 General Instrument Corporation Method and apparatus for compressing hypertext transfer protocol (HTTP) messages
US6532121B1 (en) * 1999-10-25 2003-03-11 Hewlett-Packard Company Compression algorithm with embedded meta-data for partial record operation augmented with expansion joints
US7181608B2 (en) * 2000-02-03 2007-02-20 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US20070043939A1 (en) * 2000-02-03 2007-02-22 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US7376772B2 (en) * 2000-02-03 2008-05-20 Realtime Data Llc Data storewidth accelerator
US20070083746A1 (en) * 2000-02-03 2007-04-12 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US6392567B2 (en) * 2000-03-31 2002-05-21 Fijitsu Limited Apparatus for repeatedly compressing a data string and a method thereof
US6731814B2 (en) * 2000-05-01 2004-05-04 Xerox Corporation Method for compressing digital documents with control of image quality and compression rate
US20040042506A1 (en) * 2000-10-03 2004-03-04 Realtime Data, Llc System and method for data feed acceleration and encryption
US20020080871A1 (en) * 2000-10-03 2002-06-27 Realtime Data, Llc System and method for data feed acceleration and encryption
US6885316B2 (en) * 2001-02-05 2005-04-26 Carsten Mehring System and method for keyboard independent touch typing
US20030030575A1 (en) * 2001-05-07 2003-02-13 Harmonic Data Systems Ltd. Lossless data compression
US20030034905A1 (en) * 2001-05-17 2003-02-20 Cyber Operations, Llc System and method for encoding and decoding data files
US6577254B2 (en) * 2001-11-14 2003-06-10 Hewlett-Packard Development Company, L.P. Data compression/decompression system
US20030090397A1 (en) * 2001-11-14 2003-05-15 Rasmussen Brent D. Data compression/decompression system
US6717534B2 (en) * 2002-01-18 2004-04-06 Fuji Xerox Co., Ltd. Data encoding device and data decoding device
US20040052038A1 (en) * 2002-09-12 2004-03-18 Wei-Chung Wu Stand for a flat panel display

Cited By (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8717203B2 (en) 1998-12-11 2014-05-06 Realtime Data, Llc Data compression systems and methods
US9054728B2 (en) 1998-12-11 2015-06-09 Realtime Data, Llc Data compression systems and methods
US10033405B2 (en) 1998-12-11 2018-07-24 Realtime Data Llc Data compression systems and method
US7714747B2 (en) 1998-12-11 2010-05-11 Realtime Data Llc Data compression systems and methods
US8643513B2 (en) 1998-12-11 2014-02-04 Realtime Data Llc Data compression systems and methods
US8933825B2 (en) 1998-12-11 2015-01-13 Realtime Data Llc Data compression systems and methods
US8502707B2 (en) 1998-12-11 2013-08-06 Realtime Data, Llc Data compression systems and methods
US10019458B2 (en) 1999-03-11 2018-07-10 Realtime Data Llc System and methods for accelerated data storage and retrieval
US8504710B2 (en) 1999-03-11 2013-08-06 Realtime Data Llc System and methods for accelerated data storage and retrieval
US9116908B2 (en) 1999-03-11 2015-08-25 Realtime Data Llc System and methods for accelerated data storage and retrieval
US8719438B2 (en) 1999-03-11 2014-05-06 Realtime Data Llc System and methods for accelerated data storage and retrieval
US8275897B2 (en) 1999-03-11 2012-09-25 Realtime Data, Llc System and methods for accelerated data storage and retrieval
US8756332B2 (en) 1999-03-11 2014-06-17 Realtime Data Llc System and methods for accelerated data storage and retrieval
US20070083746A1 (en) * 2000-02-03 2007-04-12 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US8880862B2 (en) 2000-02-03 2014-11-04 Realtime Data, Llc Systems and methods for accelerated loading of operating systems and application programs
US8090936B2 (en) 2000-02-03 2012-01-03 Realtime Data, Llc Systems and methods for accelerated loading of operating systems and application programs
US8112619B2 (en) 2000-02-03 2012-02-07 Realtime Data Llc Systems and methods for accelerated loading of operating systems and application programs
US9792128B2 (en) 2000-02-03 2017-10-17 Realtime Data, Llc System and method for electrical boot-device-reset signals
US10284225B2 (en) 2000-10-03 2019-05-07 Realtime Data, Llc Systems and methods for data compression
US9859919B2 (en) 2000-10-03 2018-01-02 Realtime Data Llc System and method for data compression
US10419021B2 (en) 2000-10-03 2019-09-17 Realtime Data, Llc Systems and methods of data compression
US9141992B2 (en) 2000-10-03 2015-09-22 Realtime Data Llc Data feed acceleration
US9143546B2 (en) 2000-10-03 2015-09-22 Realtime Data Llc System and method for data feed acceleration and encryption
US20040042506A1 (en) * 2000-10-03 2004-03-04 Realtime Data, Llc System and method for data feed acceleration and encryption
US9967368B2 (en) 2000-10-03 2018-05-08 Realtime Data Llc Systems and methods for data block decompression
US7777651B2 (en) 2000-10-03 2010-08-17 Realtime Data Llc System and method for data feed acceleration and encryption
US8742958B2 (en) 2000-10-03 2014-06-03 Realtime Data Llc Methods for encoding and decoding data
US9667751B2 (en) 2000-10-03 2017-05-30 Realtime Data, Llc Data feed acceleration
US8723701B2 (en) 2000-10-03 2014-05-13 Realtime Data Llc Methods for encoding and decoding data
US8717204B2 (en) 2000-10-03 2014-05-06 Realtime Data Llc Methods for encoding and decoding data
US8692695B2 (en) 2000-10-03 2014-04-08 Realtime Data, Llc Methods for encoding and decoding data
US8867610B2 (en) 2001-02-13 2014-10-21 Realtime Data Llc System and methods for video and audio data distribution
US10212417B2 (en) 2001-02-13 2019-02-19 Realtime Adaptive Streaming Llc Asymmetric data decompression systems
US8054879B2 (en) 2001-02-13 2011-11-08 Realtime Data Llc Bandwidth sensitive data compression and decompression
US9762907B2 (en) 2001-02-13 2017-09-12 Realtime Adaptive Streaming, LLC System and methods for video and audio data distribution
US8553759B2 (en) 2001-02-13 2013-10-08 Realtime Data, Llc Bandwidth sensitive data compression and decompression
US8073047B2 (en) 2001-02-13 2011-12-06 Realtime Data, Llc Bandwidth sensitive data compression and decompression
US9769477B2 (en) 2001-02-13 2017-09-19 Realtime Adaptive Streaming, LLC Video data compression systems
US8934535B2 (en) 2001-02-13 2015-01-13 Realtime Data Llc Systems and methods for video and audio data storage and distribution
US8929442B2 (en) 2001-02-13 2015-01-06 Realtime Data, Llc System and methods for video and audio data distribution
US6789167B2 (en) * 2002-03-06 2004-09-07 Hewlett-Packard Development Company, L.P. Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements
US20030171105A1 (en) * 2002-03-06 2003-09-11 Dunworth Jeremy D. Calibration techniques for frequency synthesizers
US10909623B2 (en) 2002-05-21 2021-02-02 Ip Reservoir, Llc Method and apparatus for processing financial information at hardware speeds using FPGA devices
US10929152B2 (en) 2003-05-23 2021-02-23 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10719334B2 (en) 2003-05-23 2020-07-21 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US11275594B2 (en) 2003-05-23 2022-03-15 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US8768888B2 (en) 2003-05-23 2014-07-01 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US9898312B2 (en) 2003-05-23 2018-02-20 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
US9176775B2 (en) 2003-05-23 2015-11-03 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US10346181B2 (en) 2003-05-23 2019-07-09 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US8751452B2 (en) 2003-05-23 2014-06-10 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US8620881B2 (en) 2003-05-23 2013-12-31 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US7657671B2 (en) 2005-11-04 2010-02-02 Sun Microsystems, Inc. Adaptive resilvering I/O scheduling
US20070168569A1 (en) * 2005-11-04 2007-07-19 Sun Microsystems, Inc. Adaptive resilvering I/O scheduling
US20070237327A1 (en) * 2006-03-23 2007-10-11 Exegy Incorporated Method and System for High Throughput Blockwise Independent Encryption/Decryption
US8737606B2 (en) 2006-03-23 2014-05-27 Ip Reservoir, Llc Method and system for high throughput blockwise independent encryption/decryption
US8379841B2 (en) 2006-03-23 2013-02-19 Exegy Incorporated Method and system for high throughput blockwise independent encryption/decryption
US8983063B1 (en) 2006-03-23 2015-03-17 Ip Reservoir, Llc Method and system for high throughput blockwise independent encryption/decryption
US10360632B2 (en) 2006-06-19 2019-07-23 Ip Reservoir, Llc Fast track routing of streaming data using FPGA devices
US9916622B2 (en) 2006-06-19 2018-03-13 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US10169814B2 (en) 2006-06-19 2019-01-01 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US8626624B2 (en) 2006-06-19 2014-01-07 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US9672565B2 (en) 2006-06-19 2017-06-06 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US11182856B2 (en) 2006-06-19 2021-11-23 Exegy Incorporated System and method for routing of streaming data as between multiple compute resources
US20110184844A1 (en) * 2006-06-19 2011-07-28 Exegy Incorporated High Speed Processing of Financial Information Using FPGA Devices
US8407122B2 (en) 2006-06-19 2013-03-26 Exegy Incorporated High speed processing of financial information using FPGA devices
US10817945B2 (en) 2006-06-19 2020-10-27 Ip Reservoir, Llc System and method for routing of streaming data as between multiple compute resources
US8458081B2 (en) 2006-06-19 2013-06-04 Exegy Incorporated High speed processing of financial information using FPGA devices
US8600856B2 (en) 2006-06-19 2013-12-03 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US8655764B2 (en) 2006-06-19 2014-02-18 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US10504184B2 (en) 2006-06-19 2019-12-10 Ip Reservoir, Llc Fast track routing of streaming data as between multiple compute resources
US8843408B2 (en) 2006-06-19 2014-09-23 Ip Reservoir, Llc Method and system for high speed options pricing
US10467692B2 (en) 2006-06-19 2019-11-05 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US8478680B2 (en) 2006-06-19 2013-07-02 Exegy Incorporated High speed processing of financial information using FPGA devices
US9582831B2 (en) 2006-06-19 2017-02-28 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US8595104B2 (en) 2006-06-19 2013-11-26 Ip Reservoir, Llc High speed processing of financial information using FPGA devices
US9363078B2 (en) 2007-03-22 2016-06-07 Ip Reservoir, Llc Method and apparatus for hardware-accelerated encryption/decryption
US8879727B2 (en) 2007-08-31 2014-11-04 Ip Reservoir, Llc Method and apparatus for hardware-accelerated encryption/decryption
US20090060197A1 (en) * 2007-08-31 2009-03-05 Exegy Incorporated Method and Apparatus for Hardware-Accelerated Encryption/Decryption
US10229453B2 (en) 2008-01-11 2019-03-12 Ip Reservoir, Llc Method and system for low latency basket calculation
US8762249B2 (en) 2008-12-15 2014-06-24 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US8768805B2 (en) 2008-12-15 2014-07-01 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US10929930B2 (en) 2008-12-15 2021-02-23 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US11676206B2 (en) 2008-12-15 2023-06-13 Exegy Incorporated Method and apparatus for high-speed processing of financial market depth data
US10062115B2 (en) 2008-12-15 2018-08-28 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
US11397985B2 (en) 2010-12-09 2022-07-26 Exegy Incorporated Method and apparatus for managing orders in financial markets
US11803912B2 (en) 2010-12-09 2023-10-31 Exegy Incorporated Method and apparatus for managing orders in financial markets
US10037568B2 (en) 2010-12-09 2018-07-31 Ip Reservoir, Llc Method and apparatus for managing orders in financial markets
US20130128947A1 (en) * 2011-11-18 2013-05-23 At&T Intellectual Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US9942580B2 (en) * 2011-11-18 2018-04-10 At&T Intellecutal Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US11589088B2 (en) 2011-11-18 2023-02-21 At&T Intellectual Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US10834440B2 (en) 2011-11-18 2020-11-10 At&T Intellectual Property I, L.P. System and method for automatically selecting encoding/decoding for streaming media
US9047243B2 (en) 2011-12-14 2015-06-02 Ip Reservoir, Llc Method and apparatus for low latency data distribution
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
US10963962B2 (en) 2012-03-27 2021-03-30 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US10872078B2 (en) 2012-03-27 2020-12-22 Ip Reservoir, Llc Intelligent feed switch
US20150278021A1 (en) * 2012-10-16 2015-10-01 Bull Sas Method and device for improving the reliability of data storage in a hard disk comprising a plurality of platters
US10108495B2 (en) * 2012-10-16 2018-10-23 Bull Sas Method and device for improving the reliability of data storage in a hard disk comprising a plurality of platters
US20150058576A1 (en) * 2013-08-20 2015-02-26 International Business Machines Corporation Hardware managed compressed cache
US9582426B2 (en) * 2013-08-20 2017-02-28 International Business Machines Corporation Hardware managed compressed cache
US20150100736A1 (en) * 2013-08-20 2015-04-09 International Business Machines Corporation Hardware managed compressed cache
US9720841B2 (en) * 2013-08-20 2017-08-01 International Business Machines Corporation Hardware managed compressed cache
US11416778B2 (en) 2016-12-22 2022-08-16 Ip Reservoir, Llc Method and apparatus for hardware-accelerated machine learning
US10846624B2 (en) 2016-12-22 2020-11-24 Ip Reservoir, Llc Method and apparatus for hardware-accelerated machine learning
US11256431B1 (en) 2017-01-13 2022-02-22 Lightbits Labs Ltd. Storage system having a field programmable gate array
US10963393B1 (en) 2017-01-13 2021-03-30 Lightbits Labs Ltd. Storage system and a method for application aware processing
US10956346B1 (en) * 2017-01-13 2021-03-23 Lightbits Labs Ltd. Storage system having an in-line hardware accelerator
US10983699B2 (en) 2017-11-09 2021-04-20 Nvidia Corporation Queue manager for streaming multiprocessor systems
US10489056B2 (en) * 2017-11-09 2019-11-26 Nvidia Corporation Queue manager for streaming multiprocessor systems
US20190138210A1 (en) * 2017-11-09 2019-05-09 Nvidia Corporation Queue manager for streaming multiprocessor systems
US11221778B1 (en) * 2019-04-02 2022-01-11 Pure Storage, Inc. Preparing data for deduplication
US20220129430A1 (en) * 2019-04-29 2022-04-28 Hitachi Vantara Llc Optimizing storage and retrieval of compressed data
CN113552999A (en) * 2020-04-01 2021-10-26 株式会社日立制作所 Storage device
CN111680336A (en) * 2020-05-29 2020-09-18 绿晶半导体科技(北京)有限公司 Firmware safety protection method, device, system and equipment

Also Published As

Publication number Publication date
US20100332700A1 (en) 2010-12-30
US7376772B2 (en) 2008-05-20
US20060190644A1 (en) 2006-08-24

Similar Documents

Publication Publication Date Title
US7376772B2 (en) Data storewidth accelerator
US8880862B2 (en) Systems and methods for accelerated loading of operating systems and application programs
US10212417B2 (en) Asymmetric data decompression systems
US6360300B1 (en) System and method for storing compressed and uncompressed data on a hard disk drive
US6092071A (en) Dedicated input/output processor method and apparatus for access and storage of compressed data
CA2385492C (en) Raid controller system and method with ata emulation host interface
CN100383762C (en) Storage device cache memory management

Legal Events

Date Code Title Description
AS Assignment

Owner name: REALTIME DATA, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FALLON, JAMES J.;REEL/FRAME:014205/0544

Effective date: 20030508

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION