US20050132128A1 - Flash memory device and flash memory system including buffer memory - Google Patents
Flash memory device and flash memory system including buffer memory Download PDFInfo
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- US20050132128A1 US20050132128A1 US10/957,302 US95730204A US2005132128A1 US 20050132128 A1 US20050132128 A1 US 20050132128A1 US 95730204 A US95730204 A US 95730204A US 2005132128 A1 US2005132128 A1 US 2005132128A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
Definitions
- This disclosure generally relates to flash memory devices and, more specifically, to a flash memory device and a flash memory system including a buffer memory having the same structure as the flash memory.
- Flash memories are high-integration non-volatile memories. Flash memories have been used as a main memory in systems due to excellent data preservation. In addition, flash memories can be available to a DRAM (Dynamic RAM) or a SRAM (Static RAM).
- DRAM Dynamic RAM
- SRAM Static RAM
- the flash memory device comprises: a flash memory divided into a main region and a spare region; a buffer memory for temporarily storing data to be written in the flash memory or data to be read from the flash memory, the buffer memory being divided into a main region and a spare region so as to have the same address structure as the flash memory; and control means for mapping an address of the flash memory applied from a host to be suitable to the buffer memory, and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
- a host interface for changing a control signal, an address and data, which are applied from the host into an internal signal for operating the flash memory device, is further included.
- the buffer memory is a random access memory.
- control means comprises: a register for temporarily storing an address of the flash memory, an address of the buffer memory, and a command; a buffer controller for controlling read and write operations of the buffer memory; a flash controller for controlling read and write operations of the flash memory; and a state machine for controlling the buffer controller and the flash controller so as to respectively store data of the buffer memory or the flash memory in the flash memory or the buffer memory according to values stored in the register.
- control means further includes a decoder for mapping an address applied from the buffer controller.
- the decoder separates an address input to the buffer memory into a main region and a spare region.
- the flash memory, the buffer memory and the control means are structured on one chip, respectively.
- control means further includes a decoder for mapping an address applied from the buffer controller.
- FIG. 1 is block diagram showing a flash memory device and a flash memory system according to the present invention.
- FIG. 3 is a table showing a value of a command register of FIG. 2 and operations according to thereof.
- FIG. 4 is a table showing that an address allocated in a host maps to an address of a buffer address allocated in a memory.
- FIG. 1 is a block diagram of a flash memory device including a buffer memory being a random access memory.
- a flash memory device 200 according to the present invention is connected through a bus to a host 100 .
- the flash memory device 200 inputs data to a flash memory 260 or outputs data stored in the flash memory 260 depending on a control of the host 100 .
- a host interface 210 is directly connected to the host 100 .
- the host interface 210 receives signals input from the host 100 through the bus. Signals input from the host 100 are a control signal, an address, and data. The signals are changed into internal signals for operating the flash memory device 200 . The internal signals become applied to a register 220 and a buffer controller 270 , which are located in the flash memory device 200 .
- the flash memory device 200 includes the flash memory 260 and a buffer memory 290 .
- the host 100 transmits data to be stored in the flash memory 260 to the flash memory device 200 through the bus.
- the flash memory device 200 temporarily stores transmitted data in the buffer memory 290 before the transmitted data is input to the flash memory 260 .
- the flash memory 260 is constituted by a page unit.
- the page is a basic unit of write and read.
- the page is divided into a main region and a spare region.
- memory capacity of one page is 528 Bytes.
- the main region is 512 Bytes
- the spare region is 16 Bytes.
- the buffer memory 290 temporarily stores data of the flash memory 260 .
- the buffer memory 290 is capable of performing a random access.
- the buffer memory may be embodied employing a SRAM or a DRAM, which is capable of performing a random access.
- a host interface mode is determined according to an interface mode of the RAM used as the buffer memory 290 .
- the buffer memory 290 and the flash memory 260 it is essential for the buffer memory 290 and the flash memory 260 to have the same address structure so as to efficiently operate the flash memory device 200 .
- the buffer memory is constituted by a page unit in the same way as the flash memory 260 .
- Each page unit should be formed to be divided into a main region and a spare region.
- the page capacity of the buffer memory 290 should be the same as that of the flash memory 260 .
- the register 220 receives a register control signal REG_CTRL, a register address REG_ADDR, and register data REG_DATA from the host interface 210 .
- the register control signal controls a whole operation of the register 220 .
- the register 220 performs various tasks with respect to each address. Also, the meaning of each address leading to the performed task is defined previously.
- the register data is applied to a corresponding register address.
- the register data includes an address of a flash memory (hereinafter inclusively referred to as “a flash address”), an address of a buffer memory (hereinafter inclusively referred to as “a buffer address”) and a command.
- the flash address means the address of the flash memory 260 where data will be stored.
- the buffer address means an address of the buffer memory 290 for temporarily storing data before data is stored in the flash memory 260 or is transmitted to the host 100 .
- the command instructs read or write operations.
- FIG. 2 is a table showing an address and a meaning of a register.
- the register 220 has addresses from F 000 h to F 003 h. Specific data is written in the addresses.
- the data value stored in the F 000 h address is a device ID for indicating information about the flash memory device.
- the data value stored in the F 001 h address is an address of the flash memory 260 for storing data or reading the stored data.
- the data value stored in the F 0002 h address is an address of the buffer memory 290 for temporarily storing data or reading the stored data.
- the data value stored in the F 003 h address is an operation command of the flash memory 260 .
- FIG. 3 is a table showing data values stored in the F 003 address and the operations implied by these data values.
- 0000h is a command for instructing a read operation of the flash memory 260 .
- 0001 h is a command for instructing a write operation of the flash memory 260 .
- 0002 h is a command for instructing an erase operation of the flash memory 260 .
- 0003 h is a command for instructing a reset operation of the flash memory 260 .
- the flash memory device 200 performs the following operations.
- the F 003 h address stores an operation command of the flash memory 260
- 000 h input to F 003 h means a command for instructing a read operation of the flash memory 260 . Accordingly, a read operation is performed with respect to data of a flash address being held in the F 001 h address of the register 220 .
- data read form the flash memory 260 is stored in a buffer address being held in the F 002 h address of the register 220 .
- the buffer controller 270 receives commands from the state machine 230 and the host interface 210 to be performed.
- the buffer controller 270 controls the data read/write operation of the buffer memory 290 .
- the buffer controller 270 receives a control signal BUF_CTRL 2 and an address BUF_ADDR 2 from the state machine 230 .
- the control signal BUF_CTRL 2 controls the buffer controller 270 .
- the address BUF_ADDR 2 is a buffer address, which is allocated internally in the flash memory device 200 .
- the buffer controller 270 receives a command flag CMD_FLAG from the state machine 230 .
- the command flag signal is a command signal for reading data from the buffer memory 290 .
- the buffer controller 270 performs a function to transfer a control signal, an address, and data sent from the host 100 to the buffer memory 290 . Additionally, the buffer controller 270 performs a function to selectively transfer a control signal and an address, which are applied from state machine 230 to the buffer memory 290 .
- the buffer controller 270 receives the addresses BUF_ADDR 1 and BUF_ADDR 2 respectively applied from the host 100 and the state machine 230 and then selectively transfers to a decoder 280 located at the output of the buffer controller.
- the buffer controller 270 While a write operation is performed by reading data from the flash memory 260 depending on a control of the state machine 230 , the buffer controller 270 performs a function of switching to perform both operations in case the buffer memory read command is received from the host 100 .
- the flash memory device 200 further includes the decoder 280 located in front of the buffer memory.
- the decoder 280 performs a function to change the address BUF_ADDR 1 applied to the host 100 into a buffer address allocated internally.
- a buffer address applied to the host 100 is not identical to a buffer address allocated internal to the flash memory device 200 .
- FIG. 4 is a table showing that an address allocated in the host maps to an address allocated in memory.
- (b) in FIG. 4 shows a buffer address allocated internally to be suitable to the buffer memory.
- 000h through 5 FFFh are represented by the main data region of the buffer memory 290 .
- 600 h through 62 Fh are represented by the spare data region.
- the 16 bit address allocated from the host 100 maps to the 12 bit address allocated internally in the flash memory device 200 .
- the flash controller 250 receives a control signal F-CTRL from the state machine to generate a control signal CTRL for controlling a data read or write operation of the flash memory 260 .
- the ECC & DQ block 240 receives control signals ECC_CTRL, DQ_CTRL, and an address F_ADDR from the state machine 230 .
- the control signals ECC_CTRL and DQ_CTRL control an operation of the ECC & DQ block 240 .
- the address F_ADDR is the address of the flash memory 260 for storing data.
- the address F_ADDR is transferred through the ECC & DQ block 240 to the flash memory 260 .
- FIG. 1 An operation of the flash memory device according to the present invention will be more fully described referring to FIG. 1 .
- the host 100 transmits a control signal, an address, and data to the flash memory device 200 through a bus.
- the host interface 210 changes the control signal, the address, and data into an internal signal and then transmits them to the register 220 or the buffer controller 270 .
- the register 220 receives a register control signal REG_CTRL, a register address REG-ADDR, and register data REG_DATA from the host interface 210 .
- a flash address, a buffer address, and a command among the register data REG_DATA are stored in the register address REG_ADDR.
- the buffer controller 270 receives the addresses BUF_ADDR 1 and BUF_ADDR 2 to selectively transfer to the buffer memory 290 . If the address BUF_ADDR 1 is selected in the buffer controller 270 , the address BUF_ADDR 1 becomes mapped to an address allocated internally. The mapping operation is performed by the decoder 280 . A mapped address is applied to the buffer memory 290 .
- the register control signal REG_CTRL, the register address REG-ADDR, and register data REG_DATA may be applied to the register 220 before the control signal BUF_CTRL 1 , the address BUF_ADDR 1 , and data BUF-DATA 1 are applied to the buffer controller 270 .
- the buffer address allocated in the host 100 is divided into a main region and a spare region in the mapping operation. As a result, it is possible to perform a burst read operation by only spare data. Furthermore, there is an advantage to control an addressmore easily.
- the present invention it is possible to control an operation of the flash memory device by controlling the address structure of the buffer memory and memory capacity to be suitable to the characteristics of the flash memory.
Abstract
A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
Description
- This application claims priority from Korean Patent Application No. 2003-91307, filed on Dec. 15, 2003, the contents of which is herein incorporated by reference in its entirety.
- This disclosure generally relates to flash memory devices and, more specifically, to a flash memory device and a flash memory system including a buffer memory having the same structure as the flash memory.
- Flash memories are high-integration non-volatile memories. Flash memories have been used as a main memory in systems due to excellent data preservation. In addition, flash memories can be available to a DRAM (Dynamic RAM) or a SRAM (Static RAM).
- Flash memories have been a main concern as alternate devices of hard and floppy disks in the memory field because of their high-integration and capacity. These flash memories are widely useful in the field of digital storage media of portable digital electronic machines such as cellular telephones, MP3 players, camcoders and personal digital assistants (PDAs), and so on.
- However, these flash memories have several disadvantages in comparison with RAM. For example, they require a relatively long time to read and write data, and it is impossible to perform random access. To overcome these disadvantages, new methods of supporting random access by locating buffer memories in flash memory devices have been developed in recent years. The buffer memories are random access memories (e.g., DRAM or SRAM).
- Data is not directly stored in a flash memory from a host but stored in a random access buffer memory in advance. Next, data stored in the buffer memory is stored in the flash memory. In the same way, data stored in the flash memory is not directly transmitted to the host but is stored in the buffer memory in advance. Next, data stored in the buffer memory is transmitted to the host.
- In order to support random access, before data is written in the flash memory or is transmitted to the host, a buffer memory for temporarily holding data is required. Accordingly, the buffer memory is indispensable in systems for randomly accessing data employing the flash memory.
- However, flash memories being non-volatile memory and buffer memories being volatile memory have different address structures, respectively. The flash memories consist of pages being a basic unit of write and read. The page is divided into a main region and a spare region. Generally, memory capacity of one page is 528 Bytes. Among 528 Bytes, the main region is 512 Bytes, and the spare region is 16 Bytes. The buffer memory is not divided into a page, nor main and spare regions. Accordingly, in order to use a buffer memory efficiently, it is essential to coordinate the buffer memory structure with the flash memory structure.
- One purpose of the present invention provides a flash memory device and a flash memory system, which are capable of efficiently performing a random access by including a buffer memory having the same structure as the flash memory.
- According to the present invention, the flash memory device comprises: a flash memory divided into a main region and a spare region; a buffer memory for temporarily storing data to be written in the flash memory or data to be read from the flash memory, the buffer memory being divided into a main region and a spare region so as to have the same address structure as the flash memory; and control means for mapping an address of the flash memory applied from a host to be suitable to the buffer memory, and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
- In this embodiment, the flash memory, the buffer memory, and the control means are structured on one chip, respectively.
- In this embodiment, a host interface for changing a control signal, an address and data, which are applied from the host into an internal signal for operating the flash memory device, is further included.
- In this embodiment, the buffer memory is a random access memory.
- In this embodiment, the random access memory is a SRAM or a DRAM.
- In this embodiment, the control means comprises: a register for temporarily storing an address of the flash memory, an address of the buffer memory, and a command; a buffer controller for controlling read and write operations of the buffer memory; a flash controller for controlling read and write operations of the flash memory; and a state machine for controlling the buffer controller and the flash controller so as to respectively store data of the buffer memory or the flash memory in the flash memory or the buffer memory according to values stored in the register.
- In this embodiment, the control means further includes an error correction and data input/output circuit. The error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.
- In this embodiment, the control means further includes a decoder for mapping an address applied from the buffer controller. In this embodiment, the decoder separates an address input to the buffer memory into a main region and a spare region.
- A memory system according to the present invention comprises: a host; and a flash memory device for storing data or outputting a stored data according to a request of the host. The flash memory device comprises: a flash memory divided into a main region and a spare region; a buffer memory for temporarily storing data to be written in the flash memory or data to be read from the flash memory, the buffer memory being divided into a main region and a spare region so as to have the same address structure as the flash memory; and control means for mapping an address applied from a host to be suitable to the buffer memory, and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory, or to store data of the flash memory in the buffer memory.
- In this embodiment, the flash memory, the buffer memory and the control means are structured on one chip, respectively.
- In this embodiment, a host interface for changing a control signal, an address and data, which are applied from the host into an internal signal for operating the flash memory device is further included.
- In this embodiment, the buffer memory is a random access memory.
- In this embodiment, the random access memory is a SRAM or a DRAM.
- In this embodiment, the control means comprises: a register for storing an address of the flash memory, an address of the buffer memory, and a command; a buffer controller for controlling read and write operations of the buffer memory; a flash controller for controlling read and write operations of the flash memory; and a state machine for controlling the buffer controller and the flash controller so as to respectively store data of the buffer memory or the flash memory in the flash memory or the buffer memory according to values stored in the register.
- In this embodiment, the control means further includes an error correction and data input/output circuit. The error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.
- In this embodiment, the control means further includes a decoder for mapping an address applied from the buffer controller.
- In this embodiment, the decoder separates an address input to the buffer memory into a main region and a spare region.
-
FIG. 1 is block diagram showing a flash memory device and a flash memory system according to the present invention. -
FIG. 2 is a table showing an address and a meaning of a register ofFIG. 1 . -
FIG. 3 is a table showing a value of a command register ofFIG. 2 and operations according to thereof. -
FIG. 4 is a table showing that an address allocated in a host maps to an address of a buffer address allocated in a memory. - The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
-
FIG. 1 is a block diagram of a flash memory device including a buffer memory being a random access memory. Aflash memory device 200 according to the present invention is connected through a bus to ahost 100. Theflash memory device 200 inputs data to aflash memory 260 or outputs data stored in theflash memory 260 depending on a control of thehost 100. - A
host interface 210 is directly connected to thehost 100. Thehost interface 210 receives signals input from thehost 100 through the bus. Signals input from thehost 100 are a control signal, an address, and data. The signals are changed into internal signals for operating theflash memory device 200. The internal signals become applied to aregister 220 and abuffer controller 270, which are located in theflash memory device 200. - The
host interface 210 may be embodied through various interface modes. For example, thehost interface 210 may be embodied by a SRAM interface mode. Also, thehost interface 210 may be embodied by a NOR flash memory interface mode similar to the SRAM interface mode. - The
flash memory device 200 includes theflash memory 260 and abuffer memory 290. Thehost 100 transmits data to be stored in theflash memory 260 to theflash memory device 200 through the bus. Theflash memory device 200 temporarily stores transmitted data in thebuffer memory 290 before the transmitted data is input to theflash memory 260. - Conversely, data stored in the
flash memory 260 is temporarily stored in thebuffer memory 290 before it is transmitted to thehost 100. Data stored in thebuffer memory 290 becomes read internally. The read data is transmitted to thehost 100. Theflash memory device 200 becomes capable of performing a random access by data read and write operations employing thebuffer memory 290. - The
flash memory 260 is constituted by a page unit. The page is a basic unit of write and read. The page is divided into a main region and a spare region. For example, memory capacity of one page is 528 Bytes. Among 528 Bytes, the main region is 512 Bytes, and the spare region is 16 Bytes. - The
buffer memory 290 temporarily stores data of theflash memory 260. Thebuffer memory 290 is capable of performing a random access. The buffer memory may be embodied employing a SRAM or a DRAM, which is capable of performing a random access. In this case, a host interface mode is determined according to an interface mode of the RAM used as thebuffer memory 290. - It is essential for the
buffer memory 290 and theflash memory 260 to have the same address structure so as to efficiently operate theflash memory device 200. In other words, the buffer memory is constituted by a page unit in the same way as theflash memory 260. Each page unit should be formed to be divided into a main region and a spare region. In addition, the page capacity of thebuffer memory 290 should be the same as that of theflash memory 260. - For instance, the
buffer memory 290 has a memory capacity of 528 Bytes per page. Out of 528 Bytes, the main region is 512 Bytes, and the spare region is 16 Bytes. If the page of thebuffer memory 290 is smaller than 528 Bytes or not an integral times as many as 528 Bytes, it cannot be efficiently used as the buffer memory of theflash memory device 200 where read and write operations are performed by 528 Byte units. - Referring to
FIG. 1 , theflash memory device 200 includes aregister 220, astate machine 230, abuffer controller 270, an error correction and data I/O block (hereinafter inclusively referred to as “ECC & DQ block”) 240, and aflash controller 250. - The
register 220 receives a register control signal REG_CTRL, a register address REG_ADDR, and register data REG_DATA from thehost interface 210. The register control signal controls a whole operation of theregister 220. Theregister 220 performs various tasks with respect to each address. Also, the meaning of each address leading to the performed task is defined previously. - The register data is applied to a corresponding register address. The register data includes an address of a flash memory (hereinafter inclusively referred to as “a flash address”), an address of a buffer memory (hereinafter inclusively referred to as “a buffer address”) and a command. The flash address means the address of the
flash memory 260 where data will be stored. The buffer address means an address of thebuffer memory 290 for temporarily storing data before data is stored in theflash memory 260 or is transmitted to thehost 100. The command instructs read or write operations. -
FIG. 2 is a table showing an address and a meaning of a register. For example, theregister 220 has addresses from F000h to F003h. Specific data is written in the addresses. InFIG. 2 , the data value stored in the F000h address is a device ID for indicating information about the flash memory device. The data value stored in the F001h address is an address of theflash memory 260 for storing data or reading the stored data. The data value stored in the F0002h address is an address of thebuffer memory 290 for temporarily storing data or reading the stored data. The data value stored in the F003h address is an operation command of theflash memory 260. -
FIG. 3 is a table showing data values stored in the F003 address and the operations implied by these data values. InFIG. 3, 0000h is a command for instructing a read operation of theflash memory 260. 0001h is a command for instructing a write operation of theflash memory 260. 0002h is a command for instructing an erase operation of theflash memory 260. 0003h is a command for instructing a reset operation of theflash memory 260. - If 0000h is input to the F003h address of the
register 220, theflash memory device 200 performs the following operations. The F003h address stores an operation command of theflash memory 260, and 000h input to F003h means a command for instructing a read operation of theflash memory 260. Accordingly, a read operation is performed with respect to data of a flash address being held in the F001h address of theregister 220. Next, data read form theflash memory 260 is stored in a buffer address being held in the F002h address of theregister 220. - If 0001h is input to the F003h address of the
register 220, first of all, a read operation is performed with respect to data of the buffer address being held in the F002h address of theregister 220. Next, data read from thebuffer memory 290 is sequentially stored in the flash address being held in the F001h of theregister 220. - If 0002h is input to the F003h address of the
register 220, an erase operation is performed with respect to data of the flash address being held in the F001h address of theregister 220. If 0003h value is input to the F001h value, a reset operation is performed with respect to data of the flash address being held in the F001h address of theregister 220. - Referring to
FIG. 1 , thestate machine 230 is operated referring to data values stored in theregister 220. Thestate machine 230 controls thebuffer controller 270, the ECC &DQ block 240, and theflash controller 250. - The
buffer controller 270 receives commands from thestate machine 230 and thehost interface 210 to be performed. Thebuffer controller 270 controls the data read/write operation of thebuffer memory 290. - The
buffer controller 270 receives a control signal BUF_CTRL1, an address BUF_ADDR1, and data BUF_DATA1 from thehost interface 210. The control signal BUF_CTRL1 controls an operation of thebuffer controller 270. The address BUF_ADDR1 is the address where the data BUF_DATA1 is temporarily stored in thebuffer memory 290. The address BUF_ADDR1 is directly from thehost 100 input through thehost interface 210. - In another approach, the
buffer controller 270 receives a control signal BUF_CTRL2 and an address BUF_ADDR2 from thestate machine 230. The control signal BUF_CTRL2 controls thebuffer controller 270. The address BUF_ADDR2 is a buffer address, which is allocated internally in theflash memory device 200. In addition, thebuffer controller 270 receives a command flag CMD_FLAG from thestate machine 230. For example, the command flag signal is a command signal for reading data from thebuffer memory 290. - The
buffer controller 270 performs a function to transfer a control signal, an address, and data sent from thehost 100 to thebuffer memory 290. Additionally, thebuffer controller 270 performs a function to selectively transfer a control signal and an address, which are applied fromstate machine 230 to thebuffer memory 290. Thebuffer controller 270 receives the addresses BUF_ADDR1 and BUF_ADDR2 respectively applied from thehost 100 and thestate machine 230 and then selectively transfers to adecoder 280 located at the output of the buffer controller. - While a write operation is performed by reading data from the
flash memory 260 depending on a control of thestate machine 230, thebuffer controller 270 performs a function of switching to perform both operations in case the buffer memory read command is received from thehost 100. - Continuously, referring to
FIG. 1 , theflash memory device 200 further includes thedecoder 280 located in front of the buffer memory. Thedecoder 280 performs a function to change the address BUF_ADDR1 applied to thehost 100 into a buffer address allocated internally. In general, a buffer address applied to thehost 100 is not identical to a buffer address allocated internal to theflash memory device 200. -
FIG. 4 is a table showing that an address allocated in the host maps to an address allocated in memory. - (a) in
FIG. 4 shows buffer addresses allocated in the host. Referring to (a) inFIG. 4, 000h through 05FFh are represented by a main data region of thebuffer memory 290. 8000h through 802Fh are represented by a spare data region. And, except for the main and spare data regions, the remaining is classified into regions 0600h˜7FFF and 8050h˜EFFFh preserved as needed, and a register region F000h˜F003h. The address BUF_ADDR1 applied by thehost 100 is a 16 bit address. - (b) in
FIG. 4 shows a buffer address allocated internally to be suitable to the buffer memory. Referring to (b) inFIG. 4, 000h through 5FFFh are represented by the main data region of thebuffer memory 290. 600h through 62Fh are represented by the spare data region. The 16 bit address allocated from thehost 100 maps to the 12 bit address allocated internally in theflash memory device 200. - The
decoder 280 performs the function of mapping the 16 bit address to the 12 bit address. As shown in (b) ofFIG. 4 , thedecoder 280 maps by separating the main data region and the spare data region. However, it is also capable of mapping without separating the main data region and the spare data region. - Meanwhile, the address BUF_ADDR2 applied by the
state machine 230 is a 12 bit address allocated internally to be suitable for thebuffer memory 290. Since the 12 bit address is allocated internally, it is not mapped in thedecoder 280. - Continuously referring to
FIG. 1 , theflash controller 250 receives a control signal F-CTRL from the state machine to generate a control signal CTRL for controlling a data read or write operation of theflash memory 260. - The ECC &
DQ block 240 receives control signals ECC_CTRL, DQ_CTRL, and an address F_ADDR from thestate machine 230. The control signals ECC_CTRL and DQ_CTRL control an operation of the ECC &DQ block 240. The address F_ADDR is the address of theflash memory 260 for storing data. The address F_ADDR is transferred through the ECC &DQ block 240 to theflash memory 260. - The ECC &
DQ block 240 transfers data input from thebuffer controller 270 to theflash memory 260. In addition, the ECC &DQ block 240 transfers data input from theflash memory 260 to thebuffer controller 270. The ECC &DQ block 240 corrects an error of data transmitted between thebuffer controller 270 and theflash memory 260. - Elements constituted with the
flash memory device 200 may be formed on one chip. In addition, it will be understood to those skilled in the art that theflash memory device 200 may be embodied employing multi-chip techniques. - Now, an operation of the flash memory device according to the present invention will be more fully described referring to
FIG. 1 . - The
host 100 transmits a control signal, an address, and data to theflash memory device 200 through a bus. Thehost interface 210 changes the control signal, the address, and data into an internal signal and then transmits them to theregister 220 or thebuffer controller 270. - The
register 220 receives a register control signal REG_CTRL, a register address REG-ADDR, and register data REG_DATA from thehost interface 210. A flash address, a buffer address, and a command among the register data REG_DATA are stored in the register address REG_ADDR. - The
state machine 230 controls the ECC &DQ block 240, theflash controller 250, and thebuffer controller 270 according to values stored in theregister 220. - The
buffer controller 270 receives the control signal BUF_CTRL 1, the address BUF_ADDR1, and data BUF_DATA1 from thehost interface 210. The address BUF_ADDR1 is a buffer address allocated by thehost 100. In addition, the address BUF_ADDR1 is an address of thebuffer memory 290 for temporarily storing data before data is stored in the flash memory. The data BUF_DATA1 is stored in the address BUF_ADDR1. - In another approach, the
buffer controller 270 receives the control signal BUF_CTRL2 and the address BUF_ADDR2 from thestate machine 230. The address BUF_ADDR2 is a buffer address allocated internally. - The
buffer controller 270 receives the addresses BUF_ADDR1 and BUF_ADDR2 to selectively transfer to thebuffer memory 290. If the address BUF_ADDR1 is selected in thebuffer controller 270, the address BUF_ADDR1 becomes mapped to an address allocated internally. The mapping operation is performed by thedecoder 280. A mapped address is applied to thebuffer memory 290. - Meanwhile, the register control signal REG_CTRL, the register address REG-ADDR, and register data REG_DATA may be applied to the
register 220 before the control signal BUF_CTRL1, the address BUF_ADDR1, and data BUF-DATA1 are applied to thebuffer controller 270. - The
state machine 230 controls thebuffer controller 270, the ECC &DQ block 240 and theflash controller 250 so that data stored in thebuffer memory 290, according to values stored in theregister 220, becomes read and the read data becomes stored in theflash memory 260. - For example, the
state machine 230 outputs a command flag signal CM˜_FLAG, a control signal BUF_CTRL2, and an address BUF_ADDR2. If a read operation is performed by the command flag signal CMD_FLAG, thebuffer controller 270 controls data to be read in a buffer memory region corresponding to the address BUF_ADDR2. The read data is transmitted to the ECC &DQ block 240. - Next, the
state machine 230 generates an address F_ADDR referring to a flash address value stored in theregister 220. The ECC &DQ block 240 receives a control signal ECC_CTRL and the address F_ADDR from thestate machine 230. The ECC &DQ block 240 corrects an error of data transmitted between theflash memory 260 and thebuffer memory 290. In addition, the ECC &DQ block 240 outputs a command, an address, and data according to a predetermined timing. - The
flash controller 250 converts a control signal F_CTRL from thestate machine 230 into a control signal CTRL suitable for theflash memory 260 and then outputs it. Then, a data read or write operation of the flash memory is performed in a known manner. - The
flash memory 260 consists of pages being a basic unit of read and write operations. The page is divided into a main region and a spare region. Theflash memory 260 does not support a random access operation. To support the random access, there is a need to have thebuffer memory 290. Thebuffer memory 290 is capable of performing the random access. - The
buffer memory 290 has the same address structure as theflash memory 260. That is, thebuffer memory 290 consists of pages. The page is divided into a main region and a spare region. A page capacity of thebuffer memory 290 is the same as that of theflash memory 260. - In another approach, a buffer address allocated in the
host 100 may not be identical to a buffer address allocated internally. In this case, a mapping operation, which changes the buffer address allocated in thehost 100 into the buffer address allocated internally, is performed. The mapping operation is performed in thedecoder 280. - As shown in
FIG. 4 , the buffer address allocated in thehost 100 is divided into a main region and a spare region in the mapping operation. As a result, it is possible to perform a burst read operation by only spare data. Furthermore, there is an advantage to control an addressmore easily. - According to the present invention, it is possible to control an operation of the flash memory device by controlling the address structure of the buffer memory and memory capacity to be suitable to the characteristics of the flash memory.
- Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.
Claims (20)
1. A flash memory device comprising:
a flash memory divided into a flash main region and a flash spare region;
a buffer memory to temporarily store data to be written to the flash memory or data to be read from the flash memory, the buffer memory being divided into a buffer main region and a buffer spare region so as to have a same address structure as the flash memory; and
control means to map an address of the flash memory applied from a host to be suitable for the buffer memory and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
2. The flash memory device of claim 1 , wherein the flash memory, the buffer memory and the control means are structured on one chip.
3. The flash memory device of claim 1 , further including a host interface to change a control signal, an address, and data, which are applied from the host, into an internal signal to operate the flash memory device.
4. The flash memory device of claim 1 , wherein the buffer memory is a random access memory.
5. The flash memory device of claim 4 , wherein the random access memory is a SRAM.
6. The flash memory device of claim 4 , wherein the random access memory is a DRAM.
7. The flash memory device of claim 1 , wherein the control means comprises:
a register to store an address of the flash memory, an address of the buffer memory and a command;
a buffer controller to control read and write operations of the buffer memory;
a flash controller to control read and write operations of the flash memory; and
a state machine to control the buffer controller and the flash controller so as to store data of the buffer memory in the flash memory or store data of the flash memory in the buffer memory according to values stored in the register.
8. The flash memory device of claim 7 , wherein the control means further includes an error correction and data input/output circuit, and
wherein the error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.
9. The flash memory device of claim 7 , wherein the control means further includes a decoder to map an address applied from the buffer controller.
10. The flash memory device of claim 9 , wherein the decoder separates an address input to the buffer memory into the buffer main region and the buffer spare region.
11. A flash memory system comprising:
a host; and
a flash memory device to store data or output stored data according to a request of the host, wherein the flash memory device includes a flash memory divided into a flash main region and a flash spare region, a buffer memory to temporarily store data to be written in the flash memory or data to be read from the flash memory, the buffer memory being divided into a buffer main region and a buffer spare region so as to have a same address structure as the flash memory, and a control means to map an address of the flash memory applied from the host to be suitable to the buffer memory and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
12. The flash memory system of claim 11 , wherein the flash memory, the buffer memory, and the control means are structured on one chip, respectively.
13. The flash memory system of claim 11 , further including a host interface to change a control signal, an address, and the data, which are applied from the host into an internal signal to operate the flash memory device.
14. The flash memory system of claim 11 , wherein the buffer memory is a random access memory.
15. The flash memory system of claim 14 , wherein the random access memory is a SRAM.
16. The flash memory system of claim 14 , wherein the random access memory is a DRAM.
17. The flash memory system of claim 11 , wherein the control means comprises:
a register to store an address of the flash memory, an address of the buffer memory, and a command;
a buffer controller to control read and write operations of the buffer memory;
a flash controller to control read and write operations of the flash memory; and
a state machine to control the buffer controller and the flash controller so as to respectively store data of the buffer memory in the flash memory or store data of the flash memory in the buffer memory according to values stored in the register.
18. The flash memory system of claim 17 , wherein the control means further includes an error correction and data input/output circuit, and
wherein the error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.
19. The flash memory system of claim 17 , wherein the control means further includes a decoder to map an address applied from the buffer controller.
20. The flash memory system of claim 19 , wherein the decoder separates an address input to the buffer memory into a buffer main region and a buffer spare region.
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US13/108,687 US8301829B2 (en) | 2003-12-15 | 2011-05-16 | Flash memory device and flash memory system including buffer memory |
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US13/108,687 Continuation US8301829B2 (en) | 2003-12-15 | 2011-05-16 | Flash memory device and flash memory system including buffer memory |
Publications (1)
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US20050132128A1 true US20050132128A1 (en) | 2005-06-16 |
Family
ID=34651454
Family Applications (2)
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---|---|---|---|
US10/957,302 Abandoned US20050132128A1 (en) | 2003-12-15 | 2004-09-30 | Flash memory device and flash memory system including buffer memory |
US13/108,687 Active US8301829B2 (en) | 2003-12-15 | 2011-05-16 | Flash memory device and flash memory system including buffer memory |
Family Applications After (1)
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Country Status (3)
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US (2) | US20050132128A1 (en) |
JP (1) | JP4628750B2 (en) |
KR (1) | KR100780861B1 (en) |
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Also Published As
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KR20050059984A (en) | 2005-06-21 |
US8301829B2 (en) | 2012-10-30 |
US20110219179A1 (en) | 2011-09-08 |
JP4628750B2 (en) | 2011-02-09 |
JP2005182983A (en) | 2005-07-07 |
KR100780861B1 (en) | 2007-11-29 |
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